1 /* 2 * QEMU RS/6000 memory controller 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) version 3 or any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/isa/isa.h" 22 #include "exec/address-spaces.h" 23 #include "hw/boards.h" 24 #include "qapi/error.h" 25 #include "trace.h" 26 27 #define TYPE_RS6000MC "rs6000-mc" 28 #define RS6000MC_DEVICE(obj) \ 29 OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC) 30 31 typedef struct RS6000MCState { 32 ISADevice parent_obj; 33 /* see US patent 5,684,979 for details (expired 2001-11-04) */ 34 uint32_t ram_size; 35 bool autoconfigure; 36 MemoryRegion simm[6]; 37 unsigned int simm_size[6]; 38 uint32_t end_address[8]; 39 uint8_t port0820_index; 40 PortioList portio; 41 } RS6000MCState; 42 43 /* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */ 44 45 static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr) 46 { 47 RS6000MCState *s = opaque; 48 uint32_t val = 0; 49 int socket; 50 51 /* (1 << socket) indicates 32 MB SIMM at given socket */ 52 for (socket = 0; socket < 6; socket++) { 53 if (s->simm_size[socket] == 32) { 54 val |= (1 << socket); 55 } 56 } 57 58 trace_rs6000mc_id_read(addr, val); 59 return val; 60 } 61 62 /* PORT 0804 -- SIMM Presence Register (Read Only) */ 63 64 static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr) 65 { 66 RS6000MCState *s = opaque; 67 uint32_t val = 0xff; 68 int socket; 69 70 /* (1 << socket) indicates SIMM absence at given socket */ 71 for (socket = 0; socket < 6; socket++) { 72 if (s->simm_size[socket]) { 73 val &= ~(1 << socket); 74 } 75 } 76 s->port0820_index = 0; 77 78 trace_rs6000mc_presence_read(addr, val); 79 return val; 80 } 81 82 /* Memory Controller Size Programming Register */ 83 84 static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr) 85 { 86 RS6000MCState *s = opaque; 87 uint32_t val = s->end_address[s->port0820_index] & 0x1f; 88 s->port0820_index = (s->port0820_index + 1) & 7; 89 trace_rs6000mc_size_read(addr, val); 90 return val; 91 } 92 93 static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val) 94 { 95 RS6000MCState *s = opaque; 96 uint8_t socket = val >> 5; 97 uint32_t end_address = val & 0x1f; 98 99 trace_rs6000mc_size_write(addr, val); 100 s->end_address[socket] = end_address; 101 if (socket > 0 && socket < 7) { 102 if (s->simm_size[socket - 1]) { 103 uint32_t size; 104 uint32_t start_address = 0; 105 if (socket > 1) { 106 start_address = s->end_address[socket - 1]; 107 } 108 109 size = end_address - start_address; 110 memory_region_set_enabled(&s->simm[socket - 1], size != 0); 111 memory_region_set_address(&s->simm[socket - 1], 112 start_address * 8 * 1024 * 1024); 113 } 114 } 115 } 116 117 /* Read Memory Parity Error */ 118 119 enum { 120 PORT0841_NO_ERROR_DETECTED = 0x01, 121 }; 122 123 static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr) 124 { 125 uint32_t val = PORT0841_NO_ERROR_DETECTED; 126 trace_rs6000mc_parity_read(addr, val); 127 return val; 128 } 129 130 static const MemoryRegionPortio rs6000mc_port_list[] = { 131 { 0x803, 1, 1, .read = rs6000mc_port0803_read }, 132 { 0x804, 1, 1, .read = rs6000mc_port0804_read }, 133 { 0x820, 1, 1, .read = rs6000mc_port0820_read, 134 .write = rs6000mc_port0820_write, }, 135 { 0x841, 1, 1, .read = rs6000mc_port0841_read }, 136 PORTIO_END_OF_LIST() 137 }; 138 139 static void rs6000mc_realize(DeviceState *dev, Error **errp) 140 { 141 RS6000MCState *s = RS6000MC_DEVICE(dev); 142 int socket = 0; 143 unsigned int ram_size = s->ram_size / (1024 * 1024); 144 145 while (socket < 6) { 146 if (ram_size >= 64) { 147 s->simm_size[socket] = 32; 148 s->simm_size[socket + 1] = 32; 149 ram_size -= 64; 150 } else if (ram_size >= 16) { 151 s->simm_size[socket] = 8; 152 s->simm_size[socket + 1] = 8; 153 ram_size -= 16; 154 } else { 155 /* Not enough memory */ 156 break; 157 } 158 socket += 2; 159 } 160 161 for (socket = 0; socket < 6; socket++) { 162 if (s->simm_size[socket]) { 163 char name[] = "simm.?"; 164 name[5] = socket + '0'; 165 memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev), 166 name, s->simm_size[socket] 167 * 1024 * 1024); 168 memory_region_add_subregion_overlap(get_system_memory(), 0, 169 &s->simm[socket], socket); 170 } 171 } 172 if (ram_size) { 173 /* unable to push all requested RAM in SIMMs */ 174 error_setg(errp, "RAM size incompatible with this board. " 175 "Try again with something else, like %d MB", 176 s->ram_size / 1024 / 1024 - ram_size); 177 return; 178 } 179 180 if (s->autoconfigure) { 181 uint32_t start_address = 0; 182 for (socket = 0; socket < 6; socket++) { 183 if (s->simm_size[socket]) { 184 memory_region_set_enabled(&s->simm[socket], true); 185 memory_region_set_address(&s->simm[socket], start_address); 186 start_address += memory_region_size(&s->simm[socket]); 187 } 188 } 189 } 190 191 isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, 192 rs6000mc_port_list, s, "rs6000mc"); 193 } 194 195 static const VMStateDescription vmstate_rs6000mc = { 196 .name = "rs6000-mc", 197 .version_id = 1, 198 .minimum_version_id = 1, 199 .fields = (VMStateField[]) { 200 VMSTATE_UINT8(port0820_index, RS6000MCState), 201 VMSTATE_END_OF_LIST() 202 }, 203 }; 204 205 static Property rs6000mc_properties[] = { 206 DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), 207 DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), 208 DEFINE_PROP_END_OF_LIST() 209 }; 210 211 static void rs6000mc_class_initfn(ObjectClass *klass, void *data) 212 { 213 DeviceClass *dc = DEVICE_CLASS(klass); 214 215 dc->realize = rs6000mc_realize; 216 dc->vmsd = &vmstate_rs6000mc; 217 dc->props = rs6000mc_properties; 218 } 219 220 static const TypeInfo rs6000mc_info = { 221 .name = TYPE_RS6000MC, 222 .parent = TYPE_ISA_DEVICE, 223 .instance_size = sizeof(RS6000MCState), 224 .class_init = rs6000mc_class_initfn, 225 }; 226 227 static void rs6000mc_types(void) 228 { 229 type_register_static(&rs6000mc_info); 230 } 231 232 type_init(rs6000mc_types) 233