1 /* 2 * QEMU PReP System I/O emulation 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/isa/isa.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "exec/address-spaces.h" 31 #include "qom/object.h" 32 #include "qemu/error-report.h" /* for error_report() */ 33 #include "qemu/module.h" 34 #include "sysemu/runstate.h" 35 #include "cpu.h" 36 #include "trace.h" 37 38 #define TYPE_PREP_SYSTEMIO "prep-systemio" 39 OBJECT_DECLARE_SIMPLE_TYPE(PrepSystemIoState, PREP_SYSTEMIO) 40 41 /* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */ 42 #define PREP_BIT(n) (1 << (7 - (n))) 43 44 struct PrepSystemIoState { 45 ISADevice parent_obj; 46 MemoryRegion ppc_parity_mem; 47 48 qemu_irq non_contiguous_io_map_irq; 49 uint8_t sreset; /* 0x0092 */ 50 uint8_t equipment; /* 0x080c */ 51 uint8_t system_control; /* 0x081c */ 52 uint8_t iomap_type; /* 0x0850 */ 53 uint8_t ibm_planar_id; /* 0x0852 */ 54 qemu_irq softreset_irq; 55 PortioList portio; 56 }; 57 58 /* PORT 0092 -- Special Port 92 (Read/Write) */ 59 60 enum { 61 PORT0092_SOFTRESET = PREP_BIT(7), 62 PORT0092_LE_MODE = PREP_BIT(6), 63 }; 64 65 static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val) 66 { 67 PrepSystemIoState *s = opaque; 68 69 trace_prep_systemio_write(addr, val); 70 71 s->sreset = val & PORT0092_SOFTRESET; 72 qemu_set_irq(s->softreset_irq, s->sreset); 73 74 if ((val & PORT0092_LE_MODE) != 0) { 75 /* XXX Not supported yet */ 76 error_report("little-endian mode not supported"); 77 vm_stop(RUN_STATE_PAUSED); 78 } else { 79 /* Nothing to do */ 80 } 81 } 82 83 static uint32_t prep_port0092_read(void *opaque, uint32_t addr) 84 { 85 PrepSystemIoState *s = opaque; 86 trace_prep_systemio_read(addr, s->sreset); 87 return s->sreset; 88 } 89 90 /* PORT 0808 -- Hardfile Light Register (Write Only) */ 91 92 enum { 93 PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7), 94 }; 95 96 static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val) 97 { 98 trace_prep_systemio_write(addr, val); 99 } 100 101 /* PORT 0810 -- Password Protect 1 Register (Write Only) */ 102 103 /* reset by port 0x4D in the SIO */ 104 static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val) 105 { 106 trace_prep_systemio_write(addr, val); 107 } 108 109 /* PORT 0812 -- Password Protect 2 Register (Write Only) */ 110 111 /* reset by port 0x4D in the SIO */ 112 static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val) 113 { 114 trace_prep_systemio_write(addr, val); 115 } 116 117 /* PORT 0814 -- L2 Invalidate Register (Write Only) */ 118 119 static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val) 120 { 121 trace_prep_systemio_write(addr, val); 122 } 123 124 /* PORT 0818 -- Reserved for Keylock (Read Only) */ 125 126 enum { 127 PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7), 128 }; 129 130 static uint32_t prep_port0818_read(void *opaque, uint32_t addr) 131 { 132 uint32_t val = 0; 133 trace_prep_systemio_read(addr, val); 134 return val; 135 } 136 137 /* PORT 080C -- Equipment */ 138 139 enum { 140 PORT080C_SCSIFUSE = PREP_BIT(1), 141 PORT080C_L2_COPYBACK = PREP_BIT(4), 142 PORT080C_L2_256 = PREP_BIT(5), 143 PORT080C_UPGRADE_CPU = PREP_BIT(6), 144 PORT080C_L2 = PREP_BIT(7), 145 }; 146 147 static uint32_t prep_port080c_read(void *opaque, uint32_t addr) 148 { 149 PrepSystemIoState *s = opaque; 150 trace_prep_systemio_read(addr, s->equipment); 151 return s->equipment; 152 } 153 154 /* PORT 081C -- System Control Register (Read/Write) */ 155 156 enum { 157 PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3), 158 PORT081C_MASK_TEA = PREP_BIT(2), 159 PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1), 160 PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0), 161 }; 162 163 static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val) 164 { 165 static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT | 166 PORT081C_MASK_TEA | 167 PORT081C_L2_UPDATE_INHIBIT | 168 PORT081C_L2_CACHEMISS_INHIBIT; 169 PrepSystemIoState *s = opaque; 170 trace_prep_systemio_write(addr, val); 171 s->system_control = val & mask; 172 } 173 174 static uint32_t prep_port081c_read(void *opaque, uint32_t addr) 175 { 176 PrepSystemIoState *s = opaque; 177 trace_prep_systemio_read(addr, s->system_control); 178 return s->system_control; 179 } 180 181 /* System Board Identification */ 182 183 static uint32_t prep_port0852_read(void *opaque, uint32_t addr) 184 { 185 PrepSystemIoState *s = opaque; 186 trace_prep_systemio_read(addr, s->ibm_planar_id); 187 return s->ibm_planar_id; 188 } 189 190 /* PORT 0850 -- I/O Map Type Register (Read/Write) */ 191 192 enum { 193 PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7), 194 }; 195 196 static uint32_t prep_port0850_read(void *opaque, uint32_t addr) 197 { 198 PrepSystemIoState *s = opaque; 199 trace_prep_systemio_read(addr, s->iomap_type); 200 return s->iomap_type; 201 } 202 203 static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val) 204 { 205 PrepSystemIoState *s = opaque; 206 207 trace_prep_systemio_write(addr, val); 208 qemu_set_irq(s->non_contiguous_io_map_irq, 209 val & PORT0850_IOMAP_NONCONTIGUOUS); 210 s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS; 211 } 212 213 static const MemoryRegionPortio ppc_io800_port_list[] = { 214 { 0x092, 1, 1, .read = prep_port0092_read, 215 .write = prep_port0092_write, }, 216 { 0x808, 1, 1, .write = prep_port0808_write, }, 217 { 0x80c, 1, 1, .read = prep_port080c_read, }, 218 { 0x810, 1, 1, .write = prep_port0810_write, }, 219 { 0x812, 1, 1, .write = prep_port0812_write, }, 220 { 0x814, 1, 1, .write = prep_port0814_write, }, 221 { 0x818, 1, 1, .read = prep_port0818_read }, 222 { 0x81c, 1, 1, .read = prep_port081c_read, 223 .write = prep_port081c_write, }, 224 { 0x850, 1, 1, .read = prep_port0850_read, 225 .write = prep_port0850_write, }, 226 { 0x852, 1, 1, .read = prep_port0852_read, }, 227 PORTIO_END_OF_LIST() 228 }; 229 230 static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr, 231 unsigned int size) 232 { 233 uint32_t val = 0; 234 trace_prep_systemio_read((unsigned int)addr, val); 235 return val; 236 } 237 238 static const MemoryRegionOps ppc_parity_error_ops = { 239 .read = ppc_parity_error_readl, 240 .valid = { 241 .min_access_size = 4, 242 .max_access_size = 4, 243 }, 244 }; 245 246 static void prep_systemio_realize(DeviceState *dev, Error **errp) 247 { 248 ISADevice *isa = ISA_DEVICE(dev); 249 PrepSystemIoState *s = PREP_SYSTEMIO(dev); 250 PowerPCCPU *cpu; 251 252 qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1); 253 s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS; 254 qemu_set_irq(s->non_contiguous_io_map_irq, 255 s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); 256 cpu = POWERPC_CPU(first_cpu); 257 s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 258 259 isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s, 260 "systemio800"); 261 262 memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev), 263 &ppc_parity_error_ops, s, "ppc-parity", 0x4); 264 memory_region_add_subregion(get_system_memory(), 0xbfffeff0, 265 &s->ppc_parity_mem); 266 } 267 268 static const VMStateDescription vmstate_prep_systemio = { 269 .name = "prep_systemio", 270 .version_id = 1, 271 .minimum_version_id = 1, 272 .fields = (VMStateField[]) { 273 VMSTATE_UINT8(sreset, PrepSystemIoState), 274 VMSTATE_UINT8(system_control, PrepSystemIoState), 275 VMSTATE_UINT8(iomap_type, PrepSystemIoState), 276 VMSTATE_END_OF_LIST() 277 }, 278 }; 279 280 static Property prep_systemio_properties[] = { 281 DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0), 282 DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0), 283 DEFINE_PROP_END_OF_LIST() 284 }; 285 286 static void prep_systemio_class_initfn(ObjectClass *klass, void *data) 287 { 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 290 dc->realize = prep_systemio_realize; 291 dc->vmsd = &vmstate_prep_systemio; 292 device_class_set_props(dc, prep_systemio_properties); 293 } 294 295 static TypeInfo prep_systemio800_info = { 296 .name = TYPE_PREP_SYSTEMIO, 297 .parent = TYPE_ISA_DEVICE, 298 .instance_size = sizeof(PrepSystemIoState), 299 .class_init = prep_systemio_class_initfn, 300 }; 301 302 static void prep_systemio_register_types(void) 303 { 304 type_register_static(&prep_systemio800_info); 305 } 306 307 type_init(prep_systemio_register_types) 308