1 /* 2 * QEMU PReP System I/O emulation 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/isa/isa.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "exec/address-spaces.h" 31 #include "qom/object.h" 32 #include "qemu/error-report.h" /* for error_report() */ 33 #include "qemu/module.h" 34 #include "sysemu/runstate.h" 35 #include "cpu.h" 36 #include "trace.h" 37 38 #define TYPE_PREP_SYSTEMIO "prep-systemio" 39 typedef struct PrepSystemIoState PrepSystemIoState; 40 DECLARE_INSTANCE_CHECKER(PrepSystemIoState, PREP_SYSTEMIO, 41 TYPE_PREP_SYSTEMIO) 42 43 /* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */ 44 #define PREP_BIT(n) (1 << (7 - (n))) 45 46 struct PrepSystemIoState { 47 ISADevice parent_obj; 48 MemoryRegion ppc_parity_mem; 49 50 qemu_irq non_contiguous_io_map_irq; 51 uint8_t sreset; /* 0x0092 */ 52 uint8_t equipment; /* 0x080c */ 53 uint8_t system_control; /* 0x081c */ 54 uint8_t iomap_type; /* 0x0850 */ 55 uint8_t ibm_planar_id; /* 0x0852 */ 56 qemu_irq softreset_irq; 57 PortioList portio; 58 }; 59 60 /* PORT 0092 -- Special Port 92 (Read/Write) */ 61 62 enum { 63 PORT0092_SOFTRESET = PREP_BIT(7), 64 PORT0092_LE_MODE = PREP_BIT(6), 65 }; 66 67 static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val) 68 { 69 PrepSystemIoState *s = opaque; 70 71 trace_prep_systemio_write(addr, val); 72 73 s->sreset = val & PORT0092_SOFTRESET; 74 qemu_set_irq(s->softreset_irq, s->sreset); 75 76 if ((val & PORT0092_LE_MODE) != 0) { 77 /* XXX Not supported yet */ 78 error_report("little-endian mode not supported"); 79 vm_stop(RUN_STATE_PAUSED); 80 } else { 81 /* Nothing to do */ 82 } 83 } 84 85 static uint32_t prep_port0092_read(void *opaque, uint32_t addr) 86 { 87 PrepSystemIoState *s = opaque; 88 trace_prep_systemio_read(addr, s->sreset); 89 return s->sreset; 90 } 91 92 /* PORT 0808 -- Hardfile Light Register (Write Only) */ 93 94 enum { 95 PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7), 96 }; 97 98 static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val) 99 { 100 trace_prep_systemio_write(addr, val); 101 } 102 103 /* PORT 0810 -- Password Protect 1 Register (Write Only) */ 104 105 /* reset by port 0x4D in the SIO */ 106 static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val) 107 { 108 trace_prep_systemio_write(addr, val); 109 } 110 111 /* PORT 0812 -- Password Protect 2 Register (Write Only) */ 112 113 /* reset by port 0x4D in the SIO */ 114 static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val) 115 { 116 trace_prep_systemio_write(addr, val); 117 } 118 119 /* PORT 0814 -- L2 Invalidate Register (Write Only) */ 120 121 static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val) 122 { 123 trace_prep_systemio_write(addr, val); 124 } 125 126 /* PORT 0818 -- Reserved for Keylock (Read Only) */ 127 128 enum { 129 PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7), 130 }; 131 132 static uint32_t prep_port0818_read(void *opaque, uint32_t addr) 133 { 134 uint32_t val = 0; 135 trace_prep_systemio_read(addr, val); 136 return val; 137 } 138 139 /* PORT 080C -- Equipment */ 140 141 enum { 142 PORT080C_SCSIFUSE = PREP_BIT(1), 143 PORT080C_L2_COPYBACK = PREP_BIT(4), 144 PORT080C_L2_256 = PREP_BIT(5), 145 PORT080C_UPGRADE_CPU = PREP_BIT(6), 146 PORT080C_L2 = PREP_BIT(7), 147 }; 148 149 static uint32_t prep_port080c_read(void *opaque, uint32_t addr) 150 { 151 PrepSystemIoState *s = opaque; 152 trace_prep_systemio_read(addr, s->equipment); 153 return s->equipment; 154 } 155 156 /* PORT 081C -- System Control Register (Read/Write) */ 157 158 enum { 159 PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3), 160 PORT081C_MASK_TEA = PREP_BIT(2), 161 PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1), 162 PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0), 163 }; 164 165 static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val) 166 { 167 static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT | 168 PORT081C_MASK_TEA | 169 PORT081C_L2_UPDATE_INHIBIT | 170 PORT081C_L2_CACHEMISS_INHIBIT; 171 PrepSystemIoState *s = opaque; 172 trace_prep_systemio_write(addr, val); 173 s->system_control = val & mask; 174 } 175 176 static uint32_t prep_port081c_read(void *opaque, uint32_t addr) 177 { 178 PrepSystemIoState *s = opaque; 179 trace_prep_systemio_read(addr, s->system_control); 180 return s->system_control; 181 } 182 183 /* System Board Identification */ 184 185 static uint32_t prep_port0852_read(void *opaque, uint32_t addr) 186 { 187 PrepSystemIoState *s = opaque; 188 trace_prep_systemio_read(addr, s->ibm_planar_id); 189 return s->ibm_planar_id; 190 } 191 192 /* PORT 0850 -- I/O Map Type Register (Read/Write) */ 193 194 enum { 195 PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7), 196 }; 197 198 static uint32_t prep_port0850_read(void *opaque, uint32_t addr) 199 { 200 PrepSystemIoState *s = opaque; 201 trace_prep_systemio_read(addr, s->iomap_type); 202 return s->iomap_type; 203 } 204 205 static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val) 206 { 207 PrepSystemIoState *s = opaque; 208 209 trace_prep_systemio_write(addr, val); 210 qemu_set_irq(s->non_contiguous_io_map_irq, 211 val & PORT0850_IOMAP_NONCONTIGUOUS); 212 s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS; 213 } 214 215 static const MemoryRegionPortio ppc_io800_port_list[] = { 216 { 0x092, 1, 1, .read = prep_port0092_read, 217 .write = prep_port0092_write, }, 218 { 0x808, 1, 1, .write = prep_port0808_write, }, 219 { 0x80c, 1, 1, .read = prep_port080c_read, }, 220 { 0x810, 1, 1, .write = prep_port0810_write, }, 221 { 0x812, 1, 1, .write = prep_port0812_write, }, 222 { 0x814, 1, 1, .write = prep_port0814_write, }, 223 { 0x818, 1, 1, .read = prep_port0818_read }, 224 { 0x81c, 1, 1, .read = prep_port081c_read, 225 .write = prep_port081c_write, }, 226 { 0x850, 1, 1, .read = prep_port0850_read, 227 .write = prep_port0850_write, }, 228 { 0x852, 1, 1, .read = prep_port0852_read, }, 229 PORTIO_END_OF_LIST() 230 }; 231 232 static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr, 233 unsigned int size) 234 { 235 uint32_t val = 0; 236 trace_prep_systemio_read((unsigned int)addr, val); 237 return val; 238 } 239 240 static const MemoryRegionOps ppc_parity_error_ops = { 241 .read = ppc_parity_error_readl, 242 .valid = { 243 .min_access_size = 4, 244 .max_access_size = 4, 245 }, 246 }; 247 248 static void prep_systemio_realize(DeviceState *dev, Error **errp) 249 { 250 ISADevice *isa = ISA_DEVICE(dev); 251 PrepSystemIoState *s = PREP_SYSTEMIO(dev); 252 PowerPCCPU *cpu; 253 254 qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1); 255 s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS; 256 qemu_set_irq(s->non_contiguous_io_map_irq, 257 s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); 258 cpu = POWERPC_CPU(first_cpu); 259 s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 260 261 isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s, 262 "systemio800"); 263 264 memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev), 265 &ppc_parity_error_ops, s, "ppc-parity", 0x4); 266 memory_region_add_subregion(get_system_memory(), 0xbfffeff0, 267 &s->ppc_parity_mem); 268 } 269 270 static const VMStateDescription vmstate_prep_systemio = { 271 .name = "prep_systemio", 272 .version_id = 1, 273 .minimum_version_id = 1, 274 .fields = (VMStateField[]) { 275 VMSTATE_UINT8(sreset, PrepSystemIoState), 276 VMSTATE_UINT8(system_control, PrepSystemIoState), 277 VMSTATE_UINT8(iomap_type, PrepSystemIoState), 278 VMSTATE_END_OF_LIST() 279 }, 280 }; 281 282 static Property prep_systemio_properties[] = { 283 DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0), 284 DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0), 285 DEFINE_PROP_END_OF_LIST() 286 }; 287 288 static void prep_systemio_class_initfn(ObjectClass *klass, void *data) 289 { 290 DeviceClass *dc = DEVICE_CLASS(klass); 291 292 dc->realize = prep_systemio_realize; 293 dc->vmsd = &vmstate_prep_systemio; 294 device_class_set_props(dc, prep_systemio_properties); 295 } 296 297 static TypeInfo prep_systemio800_info = { 298 .name = TYPE_PREP_SYSTEMIO, 299 .parent = TYPE_ISA_DEVICE, 300 .instance_size = sizeof(PrepSystemIoState), 301 .class_init = prep_systemio_class_initfn, 302 }; 303 304 static void prep_systemio_register_types(void) 305 { 306 type_register_static(&prep_systemio800_info); 307 } 308 309 type_init(prep_systemio_register_types) 310