1 /* 2 * QEMU PReP System I/O emulation 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/isa/isa.h" 27 #include "exec/address-spaces.h" 28 #include "qemu/error-report.h" /* for error_report() */ 29 #include "qemu/module.h" 30 #include "sysemu/sysemu.h" /* for vm_stop() */ 31 #include "cpu.h" 32 #include "trace.h" 33 34 #define TYPE_PREP_SYSTEMIO "prep-systemio" 35 #define PREP_SYSTEMIO(obj) \ 36 OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO) 37 38 /* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */ 39 #define PREP_BIT(n) (1 << (7 - (n))) 40 41 typedef struct PrepSystemIoState { 42 ISADevice parent_obj; 43 MemoryRegion ppc_parity_mem; 44 45 qemu_irq non_contiguous_io_map_irq; 46 uint8_t sreset; /* 0x0092 */ 47 uint8_t equipment; /* 0x080c */ 48 uint8_t system_control; /* 0x081c */ 49 uint8_t iomap_type; /* 0x0850 */ 50 uint8_t ibm_planar_id; /* 0x0852 */ 51 qemu_irq softreset_irq; 52 PortioList portio; 53 } PrepSystemIoState; 54 55 /* PORT 0092 -- Special Port 92 (Read/Write) */ 56 57 enum { 58 PORT0092_SOFTRESET = PREP_BIT(7), 59 PORT0092_LE_MODE = PREP_BIT(6), 60 }; 61 62 static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val) 63 { 64 PrepSystemIoState *s = opaque; 65 66 trace_prep_systemio_write(addr, val); 67 68 s->sreset = val & PORT0092_SOFTRESET; 69 qemu_set_irq(s->softreset_irq, s->sreset); 70 71 if ((val & PORT0092_LE_MODE) != 0) { 72 /* XXX Not supported yet */ 73 error_report("little-endian mode not supported"); 74 vm_stop(RUN_STATE_PAUSED); 75 } else { 76 /* Nothing to do */ 77 } 78 } 79 80 static uint32_t prep_port0092_read(void *opaque, uint32_t addr) 81 { 82 PrepSystemIoState *s = opaque; 83 trace_prep_systemio_read(addr, s->sreset); 84 return s->sreset; 85 } 86 87 /* PORT 0808 -- Hardfile Light Register (Write Only) */ 88 89 enum { 90 PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7), 91 }; 92 93 static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val) 94 { 95 trace_prep_systemio_write(addr, val); 96 } 97 98 /* PORT 0810 -- Password Protect 1 Register (Write Only) */ 99 100 /* reset by port 0x4D in the SIO */ 101 static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val) 102 { 103 trace_prep_systemio_write(addr, val); 104 } 105 106 /* PORT 0812 -- Password Protect 2 Register (Write Only) */ 107 108 /* reset by port 0x4D in the SIO */ 109 static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val) 110 { 111 trace_prep_systemio_write(addr, val); 112 } 113 114 /* PORT 0814 -- L2 Invalidate Register (Write Only) */ 115 116 static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val) 117 { 118 trace_prep_systemio_write(addr, val); 119 } 120 121 /* PORT 0818 -- Reserved for Keylock (Read Only) */ 122 123 enum { 124 PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7), 125 }; 126 127 static uint32_t prep_port0818_read(void *opaque, uint32_t addr) 128 { 129 uint32_t val = 0; 130 trace_prep_systemio_read(addr, val); 131 return val; 132 } 133 134 /* PORT 080C -- Equipment */ 135 136 enum { 137 PORT080C_SCSIFUSE = PREP_BIT(1), 138 PORT080C_L2_COPYBACK = PREP_BIT(4), 139 PORT080C_L2_256 = PREP_BIT(5), 140 PORT080C_UPGRADE_CPU = PREP_BIT(6), 141 PORT080C_L2 = PREP_BIT(7), 142 }; 143 144 static uint32_t prep_port080c_read(void *opaque, uint32_t addr) 145 { 146 PrepSystemIoState *s = opaque; 147 trace_prep_systemio_read(addr, s->equipment); 148 return s->equipment; 149 } 150 151 /* PORT 081C -- System Control Register (Read/Write) */ 152 153 enum { 154 PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3), 155 PORT081C_MASK_TEA = PREP_BIT(2), 156 PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1), 157 PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0), 158 }; 159 160 static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val) 161 { 162 static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT | 163 PORT081C_MASK_TEA | 164 PORT081C_L2_UPDATE_INHIBIT | 165 PORT081C_L2_CACHEMISS_INHIBIT; 166 PrepSystemIoState *s = opaque; 167 trace_prep_systemio_write(addr, val); 168 s->system_control = val & mask; 169 } 170 171 static uint32_t prep_port081c_read(void *opaque, uint32_t addr) 172 { 173 PrepSystemIoState *s = opaque; 174 trace_prep_systemio_read(addr, s->system_control); 175 return s->system_control; 176 } 177 178 /* System Board Identification */ 179 180 static uint32_t prep_port0852_read(void *opaque, uint32_t addr) 181 { 182 PrepSystemIoState *s = opaque; 183 trace_prep_systemio_read(addr, s->ibm_planar_id); 184 return s->ibm_planar_id; 185 } 186 187 /* PORT 0850 -- I/O Map Type Register (Read/Write) */ 188 189 enum { 190 PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7), 191 }; 192 193 static uint32_t prep_port0850_read(void *opaque, uint32_t addr) 194 { 195 PrepSystemIoState *s = opaque; 196 trace_prep_systemio_read(addr, s->iomap_type); 197 return s->iomap_type; 198 } 199 200 static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val) 201 { 202 PrepSystemIoState *s = opaque; 203 204 trace_prep_systemio_write(addr, val); 205 qemu_set_irq(s->non_contiguous_io_map_irq, 206 val & PORT0850_IOMAP_NONCONTIGUOUS); 207 s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS; 208 } 209 210 static const MemoryRegionPortio ppc_io800_port_list[] = { 211 { 0x092, 1, 1, .read = prep_port0092_read, 212 .write = prep_port0092_write, }, 213 { 0x808, 1, 1, .write = prep_port0808_write, }, 214 { 0x80c, 1, 1, .read = prep_port080c_read, }, 215 { 0x810, 1, 1, .write = prep_port0810_write, }, 216 { 0x812, 1, 1, .write = prep_port0812_write, }, 217 { 0x814, 1, 1, .write = prep_port0814_write, }, 218 { 0x818, 1, 1, .read = prep_port0818_read }, 219 { 0x81c, 1, 1, .read = prep_port081c_read, 220 .write = prep_port081c_write, }, 221 { 0x850, 1, 1, .read = prep_port0850_read, 222 .write = prep_port0850_write, }, 223 { 0x852, 1, 1, .read = prep_port0852_read, }, 224 PORTIO_END_OF_LIST() 225 }; 226 227 static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr, 228 unsigned int size) 229 { 230 uint32_t val = 0; 231 trace_prep_systemio_read((unsigned int)addr, val); 232 return val; 233 } 234 235 static const MemoryRegionOps ppc_parity_error_ops = { 236 .read = ppc_parity_error_readl, 237 .valid = { 238 .min_access_size = 4, 239 .max_access_size = 4, 240 }, 241 }; 242 243 static void prep_systemio_realize(DeviceState *dev, Error **errp) 244 { 245 ISADevice *isa = ISA_DEVICE(dev); 246 PrepSystemIoState *s = PREP_SYSTEMIO(dev); 247 PowerPCCPU *cpu; 248 249 qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1); 250 s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS; 251 qemu_set_irq(s->non_contiguous_io_map_irq, 252 s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); 253 cpu = POWERPC_CPU(first_cpu); 254 s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 255 256 isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s, 257 "systemio800"); 258 259 memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev), 260 &ppc_parity_error_ops, s, "ppc-parity", 0x4); 261 memory_region_add_subregion(get_system_memory(), 0xbfffeff0, 262 &s->ppc_parity_mem); 263 } 264 265 static const VMStateDescription vmstate_prep_systemio = { 266 .name = "prep_systemio", 267 .version_id = 1, 268 .minimum_version_id = 1, 269 .fields = (VMStateField[]) { 270 VMSTATE_UINT8(sreset, PrepSystemIoState), 271 VMSTATE_UINT8(system_control, PrepSystemIoState), 272 VMSTATE_UINT8(iomap_type, PrepSystemIoState), 273 VMSTATE_END_OF_LIST() 274 }, 275 }; 276 277 static Property prep_systemio_properties[] = { 278 DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0), 279 DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0), 280 DEFINE_PROP_END_OF_LIST() 281 }; 282 283 static void prep_systemio_class_initfn(ObjectClass *klass, void *data) 284 { 285 DeviceClass *dc = DEVICE_CLASS(klass); 286 287 dc->realize = prep_systemio_realize; 288 dc->vmsd = &vmstate_prep_systemio; 289 dc->props = prep_systemio_properties; 290 } 291 292 static TypeInfo prep_systemio800_info = { 293 .name = TYPE_PREP_SYSTEMIO, 294 .parent = TYPE_ISA_DEVICE, 295 .instance_size = sizeof(PrepSystemIoState), 296 .class_init = prep_systemio_class_initfn, 297 }; 298 299 static void prep_systemio_register_types(void) 300 { 301 type_register_static(&prep_systemio800_info); 302 } 303 304 type_init(prep_systemio_register_types) 305