1 /* 2 * QEMU PReP System I/O emulation 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/isa/isa.h" 28 #include "exec/address-spaces.h" 29 #include "qemu/error-report.h" /* for error_report() */ 30 #include "qemu/module.h" 31 #include "sysemu/sysemu.h" /* for vm_stop() */ 32 #include "cpu.h" 33 #include "trace.h" 34 35 #define TYPE_PREP_SYSTEMIO "prep-systemio" 36 #define PREP_SYSTEMIO(obj) \ 37 OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO) 38 39 /* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */ 40 #define PREP_BIT(n) (1 << (7 - (n))) 41 42 typedef struct PrepSystemIoState { 43 ISADevice parent_obj; 44 MemoryRegion ppc_parity_mem; 45 46 qemu_irq non_contiguous_io_map_irq; 47 uint8_t sreset; /* 0x0092 */ 48 uint8_t equipment; /* 0x080c */ 49 uint8_t system_control; /* 0x081c */ 50 uint8_t iomap_type; /* 0x0850 */ 51 uint8_t ibm_planar_id; /* 0x0852 */ 52 qemu_irq softreset_irq; 53 PortioList portio; 54 } PrepSystemIoState; 55 56 /* PORT 0092 -- Special Port 92 (Read/Write) */ 57 58 enum { 59 PORT0092_SOFTRESET = PREP_BIT(7), 60 PORT0092_LE_MODE = PREP_BIT(6), 61 }; 62 63 static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val) 64 { 65 PrepSystemIoState *s = opaque; 66 67 trace_prep_systemio_write(addr, val); 68 69 s->sreset = val & PORT0092_SOFTRESET; 70 qemu_set_irq(s->softreset_irq, s->sreset); 71 72 if ((val & PORT0092_LE_MODE) != 0) { 73 /* XXX Not supported yet */ 74 error_report("little-endian mode not supported"); 75 vm_stop(RUN_STATE_PAUSED); 76 } else { 77 /* Nothing to do */ 78 } 79 } 80 81 static uint32_t prep_port0092_read(void *opaque, uint32_t addr) 82 { 83 PrepSystemIoState *s = opaque; 84 trace_prep_systemio_read(addr, s->sreset); 85 return s->sreset; 86 } 87 88 /* PORT 0808 -- Hardfile Light Register (Write Only) */ 89 90 enum { 91 PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7), 92 }; 93 94 static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val) 95 { 96 trace_prep_systemio_write(addr, val); 97 } 98 99 /* PORT 0810 -- Password Protect 1 Register (Write Only) */ 100 101 /* reset by port 0x4D in the SIO */ 102 static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val) 103 { 104 trace_prep_systemio_write(addr, val); 105 } 106 107 /* PORT 0812 -- Password Protect 2 Register (Write Only) */ 108 109 /* reset by port 0x4D in the SIO */ 110 static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val) 111 { 112 trace_prep_systemio_write(addr, val); 113 } 114 115 /* PORT 0814 -- L2 Invalidate Register (Write Only) */ 116 117 static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val) 118 { 119 trace_prep_systemio_write(addr, val); 120 } 121 122 /* PORT 0818 -- Reserved for Keylock (Read Only) */ 123 124 enum { 125 PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7), 126 }; 127 128 static uint32_t prep_port0818_read(void *opaque, uint32_t addr) 129 { 130 uint32_t val = 0; 131 trace_prep_systemio_read(addr, val); 132 return val; 133 } 134 135 /* PORT 080C -- Equipment */ 136 137 enum { 138 PORT080C_SCSIFUSE = PREP_BIT(1), 139 PORT080C_L2_COPYBACK = PREP_BIT(4), 140 PORT080C_L2_256 = PREP_BIT(5), 141 PORT080C_UPGRADE_CPU = PREP_BIT(6), 142 PORT080C_L2 = PREP_BIT(7), 143 }; 144 145 static uint32_t prep_port080c_read(void *opaque, uint32_t addr) 146 { 147 PrepSystemIoState *s = opaque; 148 trace_prep_systemio_read(addr, s->equipment); 149 return s->equipment; 150 } 151 152 /* PORT 081C -- System Control Register (Read/Write) */ 153 154 enum { 155 PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3), 156 PORT081C_MASK_TEA = PREP_BIT(2), 157 PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1), 158 PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0), 159 }; 160 161 static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val) 162 { 163 static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT | 164 PORT081C_MASK_TEA | 165 PORT081C_L2_UPDATE_INHIBIT | 166 PORT081C_L2_CACHEMISS_INHIBIT; 167 PrepSystemIoState *s = opaque; 168 trace_prep_systemio_write(addr, val); 169 s->system_control = val & mask; 170 } 171 172 static uint32_t prep_port081c_read(void *opaque, uint32_t addr) 173 { 174 PrepSystemIoState *s = opaque; 175 trace_prep_systemio_read(addr, s->system_control); 176 return s->system_control; 177 } 178 179 /* System Board Identification */ 180 181 static uint32_t prep_port0852_read(void *opaque, uint32_t addr) 182 { 183 PrepSystemIoState *s = opaque; 184 trace_prep_systemio_read(addr, s->ibm_planar_id); 185 return s->ibm_planar_id; 186 } 187 188 /* PORT 0850 -- I/O Map Type Register (Read/Write) */ 189 190 enum { 191 PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7), 192 }; 193 194 static uint32_t prep_port0850_read(void *opaque, uint32_t addr) 195 { 196 PrepSystemIoState *s = opaque; 197 trace_prep_systemio_read(addr, s->iomap_type); 198 return s->iomap_type; 199 } 200 201 static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val) 202 { 203 PrepSystemIoState *s = opaque; 204 205 trace_prep_systemio_write(addr, val); 206 qemu_set_irq(s->non_contiguous_io_map_irq, 207 val & PORT0850_IOMAP_NONCONTIGUOUS); 208 s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS; 209 } 210 211 static const MemoryRegionPortio ppc_io800_port_list[] = { 212 { 0x092, 1, 1, .read = prep_port0092_read, 213 .write = prep_port0092_write, }, 214 { 0x808, 1, 1, .write = prep_port0808_write, }, 215 { 0x80c, 1, 1, .read = prep_port080c_read, }, 216 { 0x810, 1, 1, .write = prep_port0810_write, }, 217 { 0x812, 1, 1, .write = prep_port0812_write, }, 218 { 0x814, 1, 1, .write = prep_port0814_write, }, 219 { 0x818, 1, 1, .read = prep_port0818_read }, 220 { 0x81c, 1, 1, .read = prep_port081c_read, 221 .write = prep_port081c_write, }, 222 { 0x850, 1, 1, .read = prep_port0850_read, 223 .write = prep_port0850_write, }, 224 { 0x852, 1, 1, .read = prep_port0852_read, }, 225 PORTIO_END_OF_LIST() 226 }; 227 228 static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr, 229 unsigned int size) 230 { 231 uint32_t val = 0; 232 trace_prep_systemio_read((unsigned int)addr, val); 233 return val; 234 } 235 236 static const MemoryRegionOps ppc_parity_error_ops = { 237 .read = ppc_parity_error_readl, 238 .valid = { 239 .min_access_size = 4, 240 .max_access_size = 4, 241 }, 242 }; 243 244 static void prep_systemio_realize(DeviceState *dev, Error **errp) 245 { 246 ISADevice *isa = ISA_DEVICE(dev); 247 PrepSystemIoState *s = PREP_SYSTEMIO(dev); 248 PowerPCCPU *cpu; 249 250 qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1); 251 s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS; 252 qemu_set_irq(s->non_contiguous_io_map_irq, 253 s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS); 254 cpu = POWERPC_CPU(first_cpu); 255 s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 256 257 isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s, 258 "systemio800"); 259 260 memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev), 261 &ppc_parity_error_ops, s, "ppc-parity", 0x4); 262 memory_region_add_subregion(get_system_memory(), 0xbfffeff0, 263 &s->ppc_parity_mem); 264 } 265 266 static const VMStateDescription vmstate_prep_systemio = { 267 .name = "prep_systemio", 268 .version_id = 1, 269 .minimum_version_id = 1, 270 .fields = (VMStateField[]) { 271 VMSTATE_UINT8(sreset, PrepSystemIoState), 272 VMSTATE_UINT8(system_control, PrepSystemIoState), 273 VMSTATE_UINT8(iomap_type, PrepSystemIoState), 274 VMSTATE_END_OF_LIST() 275 }, 276 }; 277 278 static Property prep_systemio_properties[] = { 279 DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0), 280 DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0), 281 DEFINE_PROP_END_OF_LIST() 282 }; 283 284 static void prep_systemio_class_initfn(ObjectClass *klass, void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(klass); 287 288 dc->realize = prep_systemio_realize; 289 dc->vmsd = &vmstate_prep_systemio; 290 dc->props = prep_systemio_properties; 291 } 292 293 static TypeInfo prep_systemio800_info = { 294 .name = TYPE_PREP_SYSTEMIO, 295 .parent = TYPE_ISA_DEVICE, 296 .instance_size = sizeof(PrepSystemIoState), 297 .class_init = prep_systemio_class_initfn, 298 }; 299 300 static void prep_systemio_register_types(void) 301 { 302 type_register_static(&prep_systemio800_info); 303 } 304 305 type_init(prep_systemio_register_types) 306