1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/rtc/m48t59.h" 28 #include "hw/char/serial.h" 29 #include "hw/block/fdc.h" 30 #include "net/net.h" 31 #include "hw/isa/isa.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/boards.h" 36 #include "qapi/error.h" 37 #include "qemu/error-report.h" 38 #include "qemu/log.h" 39 #include "hw/loader.h" 40 #include "hw/rtc/mc146818rtc.h" 41 #include "hw/isa/pc87312.h" 42 #include "hw/qdev-properties.h" 43 #include "sysemu/arch_init.h" 44 #include "sysemu/kvm.h" 45 #include "sysemu/reset.h" 46 #include "trace.h" 47 #include "elf.h" 48 #include "qemu/units.h" 49 #include "kvm_ppc.h" 50 51 /* SMP is not enabled, for now */ 52 #define MAX_CPUS 1 53 54 #define MAX_IDE_BUS 2 55 56 #define CFG_ADDR 0xf0000510 57 58 #define KERNEL_LOAD_ADDR 0x01000000 59 #define INITRD_LOAD_ADDR 0x01800000 60 61 #define NVRAM_SIZE 0x2000 62 63 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 64 Error **errp) 65 { 66 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 67 } 68 69 static void ppc_prep_reset(void *opaque) 70 { 71 PowerPCCPU *cpu = opaque; 72 73 cpu_reset(CPU(cpu)); 74 } 75 76 77 /*****************************************************************************/ 78 /* NVRAM helpers */ 79 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 80 { 81 NvramClass *k = NVRAM_GET_CLASS(nvram); 82 return (k->read)(nvram, addr); 83 } 84 85 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 86 { 87 NvramClass *k = NVRAM_GET_CLASS(nvram); 88 (k->write)(nvram, addr, val); 89 } 90 91 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 92 { 93 nvram_write(nvram, addr, value); 94 } 95 96 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 97 { 98 return nvram_read(nvram, addr); 99 } 100 101 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 102 { 103 nvram_write(nvram, addr, value >> 8); 104 nvram_write(nvram, addr + 1, value & 0xFF); 105 } 106 107 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 108 { 109 uint16_t tmp; 110 111 tmp = nvram_read(nvram, addr) << 8; 112 tmp |= nvram_read(nvram, addr + 1); 113 114 return tmp; 115 } 116 117 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 118 { 119 nvram_write(nvram, addr, value >> 24); 120 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 121 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 122 nvram_write(nvram, addr + 3, value & 0xFF); 123 } 124 125 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 126 uint32_t max) 127 { 128 int i; 129 130 for (i = 0; i < max && str[i] != '\0'; i++) { 131 nvram_write(nvram, addr + i, str[i]); 132 } 133 nvram_write(nvram, addr + i, str[i]); 134 nvram_write(nvram, addr + max - 1, '\0'); 135 } 136 137 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 138 { 139 uint16_t tmp; 140 uint16_t pd, pd1, pd2; 141 142 tmp = prev >> 8; 143 pd = prev ^ value; 144 pd1 = pd & 0x000F; 145 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 146 tmp ^= (pd1 << 3) | (pd1 << 8); 147 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 148 149 return tmp; 150 } 151 152 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 153 { 154 uint32_t i; 155 uint16_t crc = 0xFFFF; 156 int odd; 157 158 odd = count & 1; 159 count &= ~1; 160 for (i = 0; i != count; i++) { 161 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 162 } 163 if (odd) { 164 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 165 } 166 167 return crc; 168 } 169 170 #define CMDLINE_ADDR 0x017ff000 171 172 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 173 const char *arch, 174 uint32_t RAM_size, int boot_device, 175 uint32_t kernel_image, uint32_t kernel_size, 176 const char *cmdline, 177 uint32_t initrd_image, uint32_t initrd_size, 178 uint32_t NVRAM_image, 179 int width, int height, int depth) 180 { 181 uint16_t crc; 182 183 /* Set parameters for Open Hack'Ware BIOS */ 184 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 185 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 186 NVRAM_set_word(nvram, 0x14, NVRAM_size); 187 NVRAM_set_string(nvram, 0x20, arch, 16); 188 NVRAM_set_lword(nvram, 0x30, RAM_size); 189 NVRAM_set_byte(nvram, 0x34, boot_device); 190 NVRAM_set_lword(nvram, 0x38, kernel_image); 191 NVRAM_set_lword(nvram, 0x3C, kernel_size); 192 if (cmdline) { 193 /* XXX: put the cmdline in NVRAM too ? */ 194 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 195 cmdline); 196 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 197 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 198 } else { 199 NVRAM_set_lword(nvram, 0x40, 0); 200 NVRAM_set_lword(nvram, 0x44, 0); 201 } 202 NVRAM_set_lword(nvram, 0x48, initrd_image); 203 NVRAM_set_lword(nvram, 0x4C, initrd_size); 204 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 205 206 NVRAM_set_word(nvram, 0x54, width); 207 NVRAM_set_word(nvram, 0x56, height); 208 NVRAM_set_word(nvram, 0x58, depth); 209 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 210 NVRAM_set_word(nvram, 0xFC, crc); 211 212 return 0; 213 } 214 215 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 216 { 217 uint16_t checksum = *(uint16_t *)opaque; 218 ISADevice *rtc; 219 220 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 221 rtc = ISA_DEVICE(dev); 222 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 223 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 224 rtc_set_memory(rtc, 0x2f, checksum >> 8); 225 rtc_set_memory(rtc, 0x3f, checksum >> 8); 226 227 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), 228 "date"); 229 } 230 return 0; 231 } 232 233 static void ibm_40p_init(MachineState *machine) 234 { 235 const char *bios_name = machine->firmware ?: "openbios-ppc"; 236 CPUPPCState *env = NULL; 237 uint16_t cmos_checksum; 238 PowerPCCPU *cpu; 239 DeviceState *dev, *i82378_dev; 240 SysBusDevice *pcihost, *s; 241 Nvram *m48t59 = NULL; 242 PCIBus *pci_bus; 243 ISADevice *isa_dev; 244 ISABus *isa_bus; 245 void *fw_cfg; 246 int i; 247 uint32_t kernel_base = 0, initrd_base = 0; 248 long kernel_size = 0, initrd_size = 0; 249 char boot_device; 250 251 /* init CPU */ 252 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 253 env = &cpu->env; 254 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 255 error_report("only 6xx bus is supported on this machine"); 256 exit(1); 257 } 258 259 if (env->flags & POWERPC_FLAG_RTC_CLK) { 260 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 261 cpu_ppc_tb_init(env, 7812500UL); 262 } else { 263 /* Set time-base frequency to 100 Mhz */ 264 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 265 } 266 qemu_register_reset(ppc_prep_reset, cpu); 267 268 /* PCI host */ 269 dev = qdev_new("raven-pcihost"); 270 qdev_prop_set_string(dev, "bios-name", bios_name); 271 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 272 pcihost = SYS_BUS_DEVICE(dev); 273 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); 274 sysbus_realize_and_unref(pcihost, &error_fatal); 275 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 276 if (!pci_bus) { 277 error_report("could not create PCI host controller"); 278 exit(1); 279 } 280 281 /* PCI -> ISA bridge */ 282 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 283 qdev_connect_gpio_out(i82378_dev, 0, 284 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 285 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); 286 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); 287 288 /* Memory controller */ 289 isa_dev = isa_new("rs6000-mc"); 290 dev = DEVICE(isa_dev); 291 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 292 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 293 294 /* RTC */ 295 isa_dev = isa_new(TYPE_MC146818_RTC); 296 dev = DEVICE(isa_dev); 297 qdev_prop_set_int32(dev, "base_year", 1900); 298 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 299 300 /* initialize CMOS checksums */ 301 cmos_checksum = 0x6aa9; 302 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 303 &cmos_checksum); 304 305 /* add some more devices */ 306 if (defaults_enabled()) { 307 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 308 309 isa_dev = isa_new("cs4231a"); 310 dev = DEVICE(isa_dev); 311 qdev_prop_set_uint32(dev, "iobase", 0x830); 312 qdev_prop_set_uint32(dev, "irq", 10); 313 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 314 315 isa_dev = isa_new("pc87312"); 316 dev = DEVICE(isa_dev); 317 qdev_prop_set_uint32(dev, "config", 12); 318 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 319 320 isa_dev = isa_new("prep-systemio"); 321 dev = DEVICE(isa_dev); 322 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 323 qdev_prop_set_uint32(dev, "equipment", 0xc0); 324 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 325 326 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), 327 "lsi53c810")); 328 lsi53c8xx_handle_legacy_cmdline(dev); 329 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); 330 331 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 332 pci_vga_init(pci_bus); 333 334 for (i = 0; i < nb_nics; i++) { 335 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 336 i == 0 ? "3" : NULL); 337 } 338 } 339 340 /* Prepare firmware configuration for OpenBIOS */ 341 dev = qdev_new(TYPE_FW_CFG_MEM); 342 fw_cfg = FW_CFG(dev); 343 qdev_prop_set_uint32(dev, "data_width", 1); 344 qdev_prop_set_bit(dev, "dma_enabled", false); 345 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 346 OBJECT(fw_cfg)); 347 s = SYS_BUS_DEVICE(dev); 348 sysbus_realize_and_unref(s, &error_fatal); 349 sysbus_mmio_map(s, 0, CFG_ADDR); 350 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 351 352 if (machine->kernel_filename) { 353 /* load kernel */ 354 kernel_base = KERNEL_LOAD_ADDR; 355 kernel_size = load_image_targphys(machine->kernel_filename, 356 kernel_base, 357 machine->ram_size - kernel_base); 358 if (kernel_size < 0) { 359 error_report("could not load kernel '%s'", 360 machine->kernel_filename); 361 exit(1); 362 } 363 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 364 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 365 /* load initrd */ 366 if (machine->initrd_filename) { 367 initrd_base = INITRD_LOAD_ADDR; 368 initrd_size = load_image_targphys(machine->initrd_filename, 369 initrd_base, 370 machine->ram_size - initrd_base); 371 if (initrd_size < 0) { 372 error_report("could not load initial ram disk '%s'", 373 machine->initrd_filename); 374 exit(1); 375 } 376 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 377 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 378 } 379 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 380 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 381 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 382 machine->kernel_cmdline); 383 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 384 machine->kernel_cmdline); 385 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 386 strlen(machine->kernel_cmdline) + 1); 387 } 388 boot_device = 'm'; 389 } else { 390 boot_device = machine->boot_order[0]; 391 } 392 393 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 394 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 395 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 396 397 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 398 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 399 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 400 401 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 402 if (kvm_enabled()) { 403 uint8_t *hypercall; 404 405 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 406 hypercall = g_malloc(16); 407 kvmppc_get_hypercall(env, hypercall, 16); 408 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 409 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 410 } else { 411 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 412 } 413 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 414 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 415 416 /* Prepare firmware configuration for Open Hack'Ware */ 417 if (m48t59) { 418 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size, 419 boot_device, 420 kernel_base, kernel_size, 421 machine->kernel_cmdline, 422 initrd_base, initrd_size, 423 /* XXX: need an option to load a NVRAM image */ 424 0, 425 graphic_width, graphic_height, graphic_depth); 426 } 427 } 428 429 static void ibm_40p_machine_init(MachineClass *mc) 430 { 431 mc->desc = "IBM RS/6000 7020 (40p)", 432 mc->init = ibm_40p_init; 433 mc->max_cpus = 1; 434 mc->default_ram_size = 128 * MiB; 435 mc->block_default_type = IF_SCSI; 436 mc->default_boot_order = "c"; 437 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); 438 mc->default_display = "std"; 439 } 440 441 DEFINE_MACHINE("40p", ibm_40p_machine_init) 442