1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "hw/hw.h" 28 #include "hw/timer/m48t59.h" 29 #include "hw/char/serial.h" 30 #include "hw/block/fdc.h" 31 #include "net/net.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/isa/isa.h" 34 #include "hw/pci/pci.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/boards.h" 38 #include "qemu/error-report.h" 39 #include "qemu/log.h" 40 #include "hw/ide.h" 41 #include "hw/loader.h" 42 #include "hw/timer/mc146818rtc.h" 43 #include "hw/isa/pc87312.h" 44 #include "hw/net/ne2000-isa.h" 45 #include "sysemu/arch_init.h" 46 #include "sysemu/kvm.h" 47 #include "sysemu/qtest.h" 48 #include "exec/address-spaces.h" 49 #include "trace.h" 50 #include "elf.h" 51 #include "qemu/units.h" 52 #include "kvm_ppc.h" 53 54 /* SMP is not enabled, for now */ 55 #define MAX_CPUS 1 56 57 #define MAX_IDE_BUS 2 58 59 #define CFG_ADDR 0xf0000510 60 61 #define BIOS_SIZE (1 * MiB) 62 #define BIOS_FILENAME "ppc_rom.bin" 63 #define KERNEL_LOAD_ADDR 0x01000000 64 #define INITRD_LOAD_ADDR 0x01800000 65 66 /* Constants for devices init */ 67 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 68 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 69 static const int ide_irq[2] = { 13, 13 }; 70 71 #define NE2000_NB_MAX 6 72 73 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 74 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 75 76 /* ISA IO ports bridge */ 77 #define PPC_IO_BASE 0x80000000 78 79 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 80 typedef struct sysctrl_t { 81 qemu_irq reset_irq; 82 Nvram *nvram; 83 uint8_t state; 84 uint8_t syscontrol; 85 int contiguous_map; 86 qemu_irq contiguous_map_irq; 87 int endian; 88 } sysctrl_t; 89 90 enum { 91 STATE_HARDFILE = 0x01, 92 }; 93 94 static sysctrl_t *sysctrl; 95 96 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 97 { 98 sysctrl_t *sysctrl = opaque; 99 100 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 101 switch (addr) { 102 case 0x0092: 103 /* Special port 92 */ 104 /* Check soft reset asked */ 105 if (val & 0x01) { 106 qemu_irq_raise(sysctrl->reset_irq); 107 } else { 108 qemu_irq_lower(sysctrl->reset_irq); 109 } 110 /* Check LE mode */ 111 if (val & 0x02) { 112 sysctrl->endian = 1; 113 } else { 114 sysctrl->endian = 0; 115 } 116 break; 117 case 0x0800: 118 /* Motorola CPU configuration register : read-only */ 119 break; 120 case 0x0802: 121 /* Motorola base module feature register : read-only */ 122 break; 123 case 0x0803: 124 /* Motorola base module status register : read-only */ 125 break; 126 case 0x0808: 127 /* Hardfile light register */ 128 if (val & 1) 129 sysctrl->state |= STATE_HARDFILE; 130 else 131 sysctrl->state &= ~STATE_HARDFILE; 132 break; 133 case 0x0810: 134 /* Password protect 1 register */ 135 if (sysctrl->nvram != NULL) { 136 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 137 (k->toggle_lock)(sysctrl->nvram, 1); 138 } 139 break; 140 case 0x0812: 141 /* Password protect 2 register */ 142 if (sysctrl->nvram != NULL) { 143 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 144 (k->toggle_lock)(sysctrl->nvram, 2); 145 } 146 break; 147 case 0x0814: 148 /* L2 invalidate register */ 149 // tlb_flush(first_cpu, 1); 150 break; 151 case 0x081C: 152 /* system control register */ 153 sysctrl->syscontrol = val & 0x0F; 154 break; 155 case 0x0850: 156 /* I/O map type register */ 157 sysctrl->contiguous_map = val & 0x01; 158 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 159 break; 160 default: 161 printf("ERROR: unaffected IO port write: %04" PRIx32 162 " => %02" PRIx32"\n", addr, val); 163 break; 164 } 165 } 166 167 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 168 { 169 sysctrl_t *sysctrl = opaque; 170 uint32_t retval = 0xFF; 171 172 switch (addr) { 173 case 0x0092: 174 /* Special port 92 */ 175 retval = sysctrl->endian << 1; 176 break; 177 case 0x0800: 178 /* Motorola CPU configuration register */ 179 retval = 0xEF; /* MPC750 */ 180 break; 181 case 0x0802: 182 /* Motorola Base module feature register */ 183 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 184 break; 185 case 0x0803: 186 /* Motorola base module status register */ 187 retval = 0xE0; /* Standard MPC750 */ 188 break; 189 case 0x080C: 190 /* Equipment present register: 191 * no L2 cache 192 * no upgrade processor 193 * no cards in PCI slots 194 * SCSI fuse is bad 195 */ 196 retval = 0x3C; 197 break; 198 case 0x0810: 199 /* Motorola base module extended feature register */ 200 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 201 break; 202 case 0x0814: 203 /* L2 invalidate: don't care */ 204 break; 205 case 0x0818: 206 /* Keylock */ 207 retval = 0x00; 208 break; 209 case 0x081C: 210 /* system control register 211 * 7 - 6 / 1 - 0: L2 cache enable 212 */ 213 retval = sysctrl->syscontrol; 214 break; 215 case 0x0823: 216 /* */ 217 retval = 0x03; /* no L2 cache */ 218 break; 219 case 0x0850: 220 /* I/O map type register */ 221 retval = sysctrl->contiguous_map; 222 break; 223 default: 224 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 225 break; 226 } 227 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 228 229 return retval; 230 } 231 232 233 #define NVRAM_SIZE 0x2000 234 235 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 236 Error **errp) 237 { 238 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 239 } 240 241 static void ppc_prep_reset(void *opaque) 242 { 243 PowerPCCPU *cpu = opaque; 244 245 cpu_reset(CPU(cpu)); 246 } 247 248 static const MemoryRegionPortio prep_portio_list[] = { 249 /* System control ports */ 250 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 251 { 0x0800, 0x52, 1, 252 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 253 /* Special port to get debug messages from Open-Firmware */ 254 { 0x0F00, 4, 1, .write = PPC_debug_write, }, 255 PORTIO_END_OF_LIST(), 256 }; 257 258 static PortioList prep_port_list; 259 260 /*****************************************************************************/ 261 /* NVRAM helpers */ 262 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 263 { 264 NvramClass *k = NVRAM_GET_CLASS(nvram); 265 return (k->read)(nvram, addr); 266 } 267 268 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 269 { 270 NvramClass *k = NVRAM_GET_CLASS(nvram); 271 (k->write)(nvram, addr, val); 272 } 273 274 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 275 { 276 nvram_write(nvram, addr, value); 277 } 278 279 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 280 { 281 return nvram_read(nvram, addr); 282 } 283 284 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 285 { 286 nvram_write(nvram, addr, value >> 8); 287 nvram_write(nvram, addr + 1, value & 0xFF); 288 } 289 290 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 291 { 292 uint16_t tmp; 293 294 tmp = nvram_read(nvram, addr) << 8; 295 tmp |= nvram_read(nvram, addr + 1); 296 297 return tmp; 298 } 299 300 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 301 { 302 nvram_write(nvram, addr, value >> 24); 303 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 304 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 305 nvram_write(nvram, addr + 3, value & 0xFF); 306 } 307 308 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 309 uint32_t max) 310 { 311 int i; 312 313 for (i = 0; i < max && str[i] != '\0'; i++) { 314 nvram_write(nvram, addr + i, str[i]); 315 } 316 nvram_write(nvram, addr + i, str[i]); 317 nvram_write(nvram, addr + max - 1, '\0'); 318 } 319 320 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 321 { 322 uint16_t tmp; 323 uint16_t pd, pd1, pd2; 324 325 tmp = prev >> 8; 326 pd = prev ^ value; 327 pd1 = pd & 0x000F; 328 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 329 tmp ^= (pd1 << 3) | (pd1 << 8); 330 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 331 332 return tmp; 333 } 334 335 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 336 { 337 uint32_t i; 338 uint16_t crc = 0xFFFF; 339 int odd; 340 341 odd = count & 1; 342 count &= ~1; 343 for (i = 0; i != count; i++) { 344 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 345 } 346 if (odd) { 347 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 348 } 349 350 return crc; 351 } 352 353 #define CMDLINE_ADDR 0x017ff000 354 355 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 356 const char *arch, 357 uint32_t RAM_size, int boot_device, 358 uint32_t kernel_image, uint32_t kernel_size, 359 const char *cmdline, 360 uint32_t initrd_image, uint32_t initrd_size, 361 uint32_t NVRAM_image, 362 int width, int height, int depth) 363 { 364 uint16_t crc; 365 366 /* Set parameters for Open Hack'Ware BIOS */ 367 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 368 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 369 NVRAM_set_word(nvram, 0x14, NVRAM_size); 370 NVRAM_set_string(nvram, 0x20, arch, 16); 371 NVRAM_set_lword(nvram, 0x30, RAM_size); 372 NVRAM_set_byte(nvram, 0x34, boot_device); 373 NVRAM_set_lword(nvram, 0x38, kernel_image); 374 NVRAM_set_lword(nvram, 0x3C, kernel_size); 375 if (cmdline) { 376 /* XXX: put the cmdline in NVRAM too ? */ 377 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 378 cmdline); 379 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 380 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 381 } else { 382 NVRAM_set_lword(nvram, 0x40, 0); 383 NVRAM_set_lword(nvram, 0x44, 0); 384 } 385 NVRAM_set_lword(nvram, 0x48, initrd_image); 386 NVRAM_set_lword(nvram, 0x4C, initrd_size); 387 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 388 389 NVRAM_set_word(nvram, 0x54, width); 390 NVRAM_set_word(nvram, 0x56, height); 391 NVRAM_set_word(nvram, 0x58, depth); 392 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 393 NVRAM_set_word(nvram, 0xFC, crc); 394 395 return 0; 396 } 397 398 /* PowerPC PREP hardware initialisation */ 399 static void ppc_prep_init(MachineState *machine) 400 { 401 ram_addr_t ram_size = machine->ram_size; 402 const char *kernel_filename = machine->kernel_filename; 403 const char *kernel_cmdline = machine->kernel_cmdline; 404 const char *initrd_filename = machine->initrd_filename; 405 const char *boot_device = machine->boot_order; 406 MemoryRegion *sysmem = get_system_memory(); 407 PowerPCCPU *cpu = NULL; 408 CPUPPCState *env = NULL; 409 Nvram *m48t59; 410 #if 0 411 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 412 #endif 413 int linux_boot, i, nb_nics1; 414 MemoryRegion *ram = g_new(MemoryRegion, 1); 415 uint32_t kernel_base, initrd_base; 416 long kernel_size, initrd_size; 417 DeviceState *dev; 418 PCIHostState *pcihost; 419 PCIBus *pci_bus; 420 PCIDevice *pci; 421 ISABus *isa_bus; 422 ISADevice *isa; 423 int ppc_boot_device; 424 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 425 426 sysctrl = g_malloc0(sizeof(sysctrl_t)); 427 428 linux_boot = (kernel_filename != NULL); 429 430 /* init CPUs */ 431 for (i = 0; i < smp_cpus; i++) { 432 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 433 env = &cpu->env; 434 435 if (env->flags & POWERPC_FLAG_RTC_CLK) { 436 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 437 cpu_ppc_tb_init(env, 7812500UL); 438 } else { 439 /* Set time-base frequency to 100 Mhz */ 440 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 441 } 442 qemu_register_reset(ppc_prep_reset, cpu); 443 } 444 445 /* allocate RAM */ 446 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 447 memory_region_add_subregion(sysmem, 0, ram); 448 449 if (linux_boot) { 450 kernel_base = KERNEL_LOAD_ADDR; 451 /* now we can load the kernel */ 452 kernel_size = load_image_targphys(kernel_filename, kernel_base, 453 ram_size - kernel_base); 454 if (kernel_size < 0) { 455 error_report("could not load kernel '%s'", kernel_filename); 456 exit(1); 457 } 458 /* load initrd */ 459 if (initrd_filename) { 460 initrd_base = INITRD_LOAD_ADDR; 461 initrd_size = load_image_targphys(initrd_filename, initrd_base, 462 ram_size - initrd_base); 463 if (initrd_size < 0) { 464 error_report("could not load initial ram disk '%s'", 465 initrd_filename); 466 exit(1); 467 } 468 } else { 469 initrd_base = 0; 470 initrd_size = 0; 471 } 472 ppc_boot_device = 'm'; 473 } else { 474 kernel_base = 0; 475 kernel_size = 0; 476 initrd_base = 0; 477 initrd_size = 0; 478 ppc_boot_device = '\0'; 479 /* For now, OHW cannot boot from the network. */ 480 for (i = 0; boot_device[i] != '\0'; i++) { 481 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 482 ppc_boot_device = boot_device[i]; 483 break; 484 } 485 } 486 if (ppc_boot_device == '\0') { 487 error_report("No valid boot device for Mac99 machine"); 488 exit(1); 489 } 490 } 491 492 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 493 error_report("Only 6xx bus is supported on PREP machine"); 494 exit(1); 495 } 496 497 dev = qdev_create(NULL, "raven-pcihost"); 498 if (bios_name == NULL) { 499 bios_name = BIOS_FILENAME; 500 } 501 qdev_prop_set_string(dev, "bios-name", bios_name); 502 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 503 qdev_prop_set_bit(dev, "is-legacy-prep", true); 504 pcihost = PCI_HOST_BRIDGE(dev); 505 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 506 qdev_init_nofail(dev); 507 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 508 if (pci_bus == NULL) { 509 error_report("Couldn't create PCI host controller"); 510 exit(1); 511 } 512 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 513 514 /* PCI -> ISA bridge */ 515 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 516 cpu = POWERPC_CPU(first_cpu); 517 qdev_connect_gpio_out(&pci->qdev, 0, 518 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 519 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 520 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 521 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 522 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 523 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 524 525 /* Super I/O (parallel + serial ports) */ 526 isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO); 527 dev = DEVICE(isa); 528 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 529 qdev_init_nofail(dev); 530 531 /* init basic PC hardware */ 532 pci_vga_init(pci_bus); 533 534 nb_nics1 = nb_nics; 535 if (nb_nics1 > NE2000_NB_MAX) 536 nb_nics1 = NE2000_NB_MAX; 537 for(i = 0; i < nb_nics1; i++) { 538 if (nd_table[i].model == NULL) { 539 nd_table[i].model = g_strdup("ne2k_isa"); 540 } 541 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 542 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 543 &nd_table[i]); 544 } else { 545 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 546 } 547 } 548 549 ide_drive_get(hd, ARRAY_SIZE(hd)); 550 for(i = 0; i < MAX_IDE_BUS; i++) { 551 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 552 hd[2 * i], 553 hd[2 * i + 1]); 554 } 555 556 cpu = POWERPC_CPU(first_cpu); 557 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 558 559 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 560 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 561 562 /* 563 * PowerPC control and status register group: unimplemented, 564 * would be at address 0xFEFF0000. 565 */ 566 567 if (machine_usb(machine)) { 568 pci_create_simple(pci_bus, -1, "pci-ohci"); 569 } 570 571 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 572 if (m48t59 == NULL) 573 return; 574 sysctrl->nvram = m48t59; 575 576 /* Initialise NVRAM */ 577 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 578 ppc_boot_device, 579 kernel_base, kernel_size, 580 kernel_cmdline, 581 initrd_base, initrd_size, 582 /* XXX: need an option to load a NVRAM image */ 583 0, 584 graphic_width, graphic_height, graphic_depth); 585 } 586 587 static void prep_machine_init(MachineClass *mc) 588 { 589 mc->deprecation_reason = "use 40p machine type instead"; 590 mc->desc = "PowerPC PREP platform"; 591 mc->init = ppc_prep_init; 592 mc->block_default_type = IF_IDE; 593 mc->max_cpus = MAX_CPUS; 594 mc->default_boot_order = "cad"; 595 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602"); 596 mc->default_display = "std"; 597 } 598 599 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 600 { 601 uint16_t checksum = *(uint16_t *)opaque; 602 ISADevice *rtc; 603 604 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 605 rtc = ISA_DEVICE(dev); 606 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 607 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 608 rtc_set_memory(rtc, 0x2f, checksum >> 8); 609 rtc_set_memory(rtc, 0x3f, checksum >> 8); 610 611 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), 612 "date", NULL); 613 } 614 return 0; 615 } 616 617 static void ibm_40p_init(MachineState *machine) 618 { 619 CPUPPCState *env = NULL; 620 uint16_t cmos_checksum; 621 PowerPCCPU *cpu; 622 DeviceState *dev, *i82378_dev; 623 SysBusDevice *pcihost, *s; 624 Nvram *m48t59 = NULL; 625 PCIBus *pci_bus; 626 ISABus *isa_bus; 627 void *fw_cfg; 628 int i; 629 uint32_t kernel_base = 0, initrd_base = 0; 630 long kernel_size = 0, initrd_size = 0; 631 char boot_device; 632 633 /* init CPU */ 634 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 635 env = &cpu->env; 636 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 637 error_report("only 6xx bus is supported on this machine"); 638 exit(1); 639 } 640 641 if (env->flags & POWERPC_FLAG_RTC_CLK) { 642 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 643 cpu_ppc_tb_init(env, 7812500UL); 644 } else { 645 /* Set time-base frequency to 100 Mhz */ 646 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 647 } 648 qemu_register_reset(ppc_prep_reset, cpu); 649 650 /* PCI host */ 651 dev = qdev_create(NULL, "raven-pcihost"); 652 if (!bios_name) { 653 bios_name = "openbios-ppc"; 654 } 655 qdev_prop_set_string(dev, "bios-name", bios_name); 656 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 657 pcihost = SYS_BUS_DEVICE(dev); 658 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 659 qdev_init_nofail(dev); 660 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 661 if (!pci_bus) { 662 error_report("could not create PCI host controller"); 663 exit(1); 664 } 665 666 /* PCI -> ISA bridge */ 667 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 668 qdev_connect_gpio_out(i82378_dev, 0, 669 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 670 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); 671 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); 672 673 /* Memory controller */ 674 dev = DEVICE(isa_create(isa_bus, "rs6000-mc")); 675 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 676 qdev_init_nofail(dev); 677 678 /* RTC */ 679 dev = DEVICE(isa_create(isa_bus, TYPE_MC146818_RTC)); 680 qdev_prop_set_int32(dev, "base_year", 1900); 681 qdev_init_nofail(dev); 682 683 /* initialize CMOS checksums */ 684 cmos_checksum = 0x6aa9; 685 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 686 &cmos_checksum); 687 688 /* add some more devices */ 689 if (defaults_enabled()) { 690 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 691 692 dev = DEVICE(isa_create(isa_bus, "cs4231a")); 693 qdev_prop_set_uint32(dev, "iobase", 0x830); 694 qdev_prop_set_uint32(dev, "irq", 10); 695 qdev_init_nofail(dev); 696 697 dev = DEVICE(isa_create(isa_bus, "pc87312")); 698 qdev_prop_set_uint32(dev, "config", 12); 699 qdev_init_nofail(dev); 700 701 dev = DEVICE(isa_create(isa_bus, "prep-systemio")); 702 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 703 qdev_prop_set_uint32(dev, "equipment", 0xc0); 704 qdev_init_nofail(dev); 705 706 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), 707 "lsi53c810")); 708 lsi53c8xx_handle_legacy_cmdline(dev); 709 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); 710 711 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 712 pci_vga_init(pci_bus); 713 714 for (i = 0; i < nb_nics; i++) { 715 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 716 i == 0 ? "3" : NULL); 717 } 718 } 719 720 /* Prepare firmware configuration for OpenBIOS */ 721 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 722 fw_cfg = FW_CFG(dev); 723 qdev_prop_set_uint32(dev, "data_width", 1); 724 qdev_prop_set_bit(dev, "dma_enabled", false); 725 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 726 OBJECT(fw_cfg), NULL); 727 qdev_init_nofail(dev); 728 s = SYS_BUS_DEVICE(dev); 729 sysbus_mmio_map(s, 0, CFG_ADDR); 730 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 731 732 if (machine->kernel_filename) { 733 /* load kernel */ 734 kernel_base = KERNEL_LOAD_ADDR; 735 kernel_size = load_image_targphys(machine->kernel_filename, 736 kernel_base, 737 machine->ram_size - kernel_base); 738 if (kernel_size < 0) { 739 error_report("could not load kernel '%s'", 740 machine->kernel_filename); 741 exit(1); 742 } 743 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 744 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 745 /* load initrd */ 746 if (machine->initrd_filename) { 747 initrd_base = INITRD_LOAD_ADDR; 748 initrd_size = load_image_targphys(machine->initrd_filename, 749 initrd_base, 750 machine->ram_size - initrd_base); 751 if (initrd_size < 0) { 752 error_report("could not load initial ram disk '%s'", 753 machine->initrd_filename); 754 exit(1); 755 } 756 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 757 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 758 } 759 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 760 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 761 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 762 machine->kernel_cmdline); 763 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 764 machine->kernel_cmdline); 765 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 766 strlen(machine->kernel_cmdline) + 1); 767 } 768 boot_device = 'm'; 769 } else { 770 boot_device = machine->boot_order[0]; 771 } 772 773 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 774 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 775 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 776 777 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 778 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 779 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 780 781 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 782 if (kvm_enabled()) { 783 #ifdef CONFIG_KVM 784 uint8_t *hypercall; 785 786 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 787 hypercall = g_malloc(16); 788 kvmppc_get_hypercall(env, hypercall, 16); 789 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 790 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 791 #endif 792 } else { 793 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 794 } 795 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 796 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 797 798 /* Prepare firmware configuration for Open Hack'Ware */ 799 if (m48t59) { 800 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 801 boot_device, 802 kernel_base, kernel_size, 803 machine->kernel_cmdline, 804 initrd_base, initrd_size, 805 /* XXX: need an option to load a NVRAM image */ 806 0, 807 graphic_width, graphic_height, graphic_depth); 808 } 809 } 810 811 static void ibm_40p_machine_init(MachineClass *mc) 812 { 813 mc->desc = "IBM RS/6000 7020 (40p)", 814 mc->init = ibm_40p_init; 815 mc->max_cpus = 1; 816 mc->default_ram_size = 128 * MiB; 817 mc->block_default_type = IF_SCSI; 818 mc->default_boot_order = "c"; 819 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); 820 mc->default_display = "std"; 821 } 822 823 DEFINE_MACHINE("40p", ibm_40p_machine_init) 824 DEFINE_MACHINE("prep", prep_machine_init) 825