xref: /openbmc/qemu/hw/ppc/prep.c (revision ad66b5cb)
1 /*
2  * QEMU PPC PREP hardware System Emulator
3  *
4  * Copyright (c) 2003-2007 Jocelyn Mayer
5  * Copyright (c) 2017 Hervé Poussineau
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 #include "qemu/osdep.h"
27 #include "hw/rtc/m48t59.h"
28 #include "hw/char/serial.h"
29 #include "hw/block/fdc.h"
30 #include "net/net.h"
31 #include "hw/isa/isa.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/ppc/ppc.h"
35 #include "hw/boards.h"
36 #include "qapi/error.h"
37 #include "qemu/error-report.h"
38 #include "qemu/log.h"
39 #include "hw/loader.h"
40 #include "hw/rtc/mc146818rtc.h"
41 #include "hw/isa/pc87312.h"
42 #include "hw/qdev-properties.h"
43 #include "sysemu/kvm.h"
44 #include "sysemu/reset.h"
45 #include "trace.h"
46 #include "elf.h"
47 #include "qemu/units.h"
48 #include "kvm_ppc.h"
49 
50 /* SMP is not enabled, for now */
51 #define MAX_CPUS 1
52 
53 #define CFG_ADDR 0xf0000510
54 
55 #define KERNEL_LOAD_ADDR 0x01000000
56 #define INITRD_LOAD_ADDR 0x01800000
57 
58 #define NVRAM_SIZE        0x2000
59 
60 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
61                             Error **errp)
62 {
63     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
64 }
65 
66 static void ppc_prep_reset(void *opaque)
67 {
68     PowerPCCPU *cpu = opaque;
69 
70     cpu_reset(CPU(cpu));
71 }
72 
73 
74 /*****************************************************************************/
75 /* NVRAM helpers */
76 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
77 {
78     NvramClass *k = NVRAM_GET_CLASS(nvram);
79     return (k->read)(nvram, addr);
80 }
81 
82 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
83 {
84     NvramClass *k = NVRAM_GET_CLASS(nvram);
85     (k->write)(nvram, addr, val);
86 }
87 
88 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
89 {
90     nvram_write(nvram, addr, value);
91 }
92 
93 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
94 {
95     return nvram_read(nvram, addr);
96 }
97 
98 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
99 {
100     nvram_write(nvram, addr, value >> 8);
101     nvram_write(nvram, addr + 1, value & 0xFF);
102 }
103 
104 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
105 {
106     uint16_t tmp;
107 
108     tmp = nvram_read(nvram, addr) << 8;
109     tmp |= nvram_read(nvram, addr + 1);
110 
111     return tmp;
112 }
113 
114 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
115 {
116     nvram_write(nvram, addr, value >> 24);
117     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
118     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
119     nvram_write(nvram, addr + 3, value & 0xFF);
120 }
121 
122 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
123                              uint32_t max)
124 {
125     int i;
126 
127     for (i = 0; i < max && str[i] != '\0'; i++) {
128         nvram_write(nvram, addr + i, str[i]);
129     }
130     nvram_write(nvram, addr + i, str[i]);
131     nvram_write(nvram, addr + max - 1, '\0');
132 }
133 
134 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
135 {
136     uint16_t tmp;
137     uint16_t pd, pd1, pd2;
138 
139     tmp = prev >> 8;
140     pd = prev ^ value;
141     pd1 = pd & 0x000F;
142     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
143     tmp ^= (pd1 << 3) | (pd1 << 8);
144     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
145 
146     return tmp;
147 }
148 
149 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
150 {
151     uint32_t i;
152     uint16_t crc = 0xFFFF;
153     int odd;
154 
155     odd = count & 1;
156     count &= ~1;
157     for (i = 0; i != count; i++) {
158         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
159     }
160     if (odd) {
161         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
162     }
163 
164     return crc;
165 }
166 
167 #define CMDLINE_ADDR 0x017ff000
168 
169 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
170                           const char *arch,
171                           uint32_t RAM_size, int boot_device,
172                           uint32_t kernel_image, uint32_t kernel_size,
173                           const char *cmdline,
174                           uint32_t initrd_image, uint32_t initrd_size,
175                           uint32_t NVRAM_image,
176                           int width, int height, int depth)
177 {
178     uint16_t crc;
179 
180     /* Set parameters for Open Hack'Ware BIOS */
181     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
182     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
183     NVRAM_set_word(nvram,   0x14, NVRAM_size);
184     NVRAM_set_string(nvram, 0x20, arch, 16);
185     NVRAM_set_lword(nvram,  0x30, RAM_size);
186     NVRAM_set_byte(nvram,   0x34, boot_device);
187     NVRAM_set_lword(nvram,  0x38, kernel_image);
188     NVRAM_set_lword(nvram,  0x3C, kernel_size);
189     if (cmdline) {
190         /* XXX: put the cmdline in NVRAM too ? */
191         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
192                          cmdline);
193         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
194         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
195     } else {
196         NVRAM_set_lword(nvram,  0x40, 0);
197         NVRAM_set_lword(nvram,  0x44, 0);
198     }
199     NVRAM_set_lword(nvram,  0x48, initrd_image);
200     NVRAM_set_lword(nvram,  0x4C, initrd_size);
201     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
202 
203     NVRAM_set_word(nvram,   0x54, width);
204     NVRAM_set_word(nvram,   0x56, height);
205     NVRAM_set_word(nvram,   0x58, depth);
206     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
207     NVRAM_set_word(nvram,   0xFC, crc);
208 
209     return 0;
210 }
211 
212 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
213 {
214     uint16_t checksum = *(uint16_t *)opaque;
215 
216     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
217         MC146818RtcState *rtc = MC146818_RTC(dev);
218         mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff);
219         mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff);
220         mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8);
221         mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8);
222 
223         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
224                                   "date");
225     }
226     return 0;
227 }
228 
229 static void ibm_40p_init(MachineState *machine)
230 {
231     const char *bios_name = machine->firmware ?: "openbios-ppc";
232     CPUPPCState *env = NULL;
233     uint16_t cmos_checksum;
234     PowerPCCPU *cpu;
235     DeviceState *dev, *i82378_dev;
236     SysBusDevice *pcihost, *s;
237     Nvram *m48t59 = NULL;
238     PCIBus *pci_bus;
239     ISADevice *isa_dev;
240     ISABus *isa_bus;
241     void *fw_cfg;
242     int i;
243     uint32_t kernel_base = 0, initrd_base = 0;
244     long kernel_size = 0, initrd_size = 0;
245     char boot_device;
246 
247     /* init CPU */
248     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
249     env = &cpu->env;
250     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
251         error_report("only 6xx bus is supported on this machine");
252         exit(1);
253     }
254 
255     /* Set time-base frequency to 100 Mhz */
256     cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
257     qemu_register_reset(ppc_prep_reset, cpu);
258 
259     /* PCI host */
260     dev = qdev_new("raven-pcihost");
261     qdev_prop_set_string(dev, "bios-name", bios_name);
262     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
263     pcihost = SYS_BUS_DEVICE(dev);
264     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
265     sysbus_realize_and_unref(pcihost, &error_fatal);
266     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
267     if (!pci_bus) {
268         error_report("could not create PCI host controller");
269         exit(1);
270     }
271 
272     /* PCI -> ISA bridge */
273     i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
274     qdev_connect_gpio_out(i82378_dev, 0,
275                           qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
276     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
277     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
278 
279     /* Memory controller */
280     isa_dev = isa_new("rs6000-mc");
281     dev = DEVICE(isa_dev);
282     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
283     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
284 
285     /* RTC */
286     isa_dev = isa_new(TYPE_MC146818_RTC);
287     dev = DEVICE(isa_dev);
288     qdev_prop_set_int32(dev, "base_year", 1900);
289     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
290 
291     /* initialize CMOS checksums */
292     cmos_checksum = 0x6aa9;
293     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
294                        &cmos_checksum);
295 
296     /* add some more devices */
297     if (defaults_enabled()) {
298         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
299 
300         isa_dev = isa_new("cs4231a");
301         dev = DEVICE(isa_dev);
302         qdev_prop_set_uint32(dev, "iobase", 0x830);
303         qdev_prop_set_uint32(dev, "irq", 10);
304         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
305 
306         isa_dev = isa_new("pc87312");
307         dev = DEVICE(isa_dev);
308         qdev_prop_set_uint32(dev, "config", 12);
309         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
310 
311         isa_dev = isa_new("prep-systemio");
312         dev = DEVICE(isa_dev);
313         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
314         qdev_prop_set_uint32(dev, "equipment", 0xc0);
315         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
316 
317         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
318                                        "lsi53c810"));
319         lsi53c8xx_handle_legacy_cmdline(dev);
320         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
321 
322         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
323         pci_vga_init(pci_bus);
324 
325         for (i = 0; i < nb_nics; i++) {
326             pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
327                                 i == 0 ? "3" : NULL);
328         }
329     }
330 
331     /* Prepare firmware configuration for OpenBIOS */
332     dev = qdev_new(TYPE_FW_CFG_MEM);
333     fw_cfg = FW_CFG(dev);
334     qdev_prop_set_uint32(dev, "data_width", 1);
335     qdev_prop_set_bit(dev, "dma_enabled", false);
336     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
337                               OBJECT(fw_cfg));
338     s = SYS_BUS_DEVICE(dev);
339     sysbus_realize_and_unref(s, &error_fatal);
340     sysbus_mmio_map(s, 0, CFG_ADDR);
341     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
342 
343     if (machine->kernel_filename) {
344         /* load kernel */
345         kernel_base = KERNEL_LOAD_ADDR;
346         kernel_size = load_image_targphys(machine->kernel_filename,
347                                           kernel_base,
348                                           machine->ram_size - kernel_base);
349         if (kernel_size < 0) {
350             error_report("could not load kernel '%s'",
351                          machine->kernel_filename);
352             exit(1);
353         }
354         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
355         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
356         /* load initrd */
357         if (machine->initrd_filename) {
358             initrd_base = INITRD_LOAD_ADDR;
359             initrd_size = load_image_targphys(machine->initrd_filename,
360                                               initrd_base,
361                                               machine->ram_size - initrd_base);
362             if (initrd_size < 0) {
363                 error_report("could not load initial ram disk '%s'",
364                              machine->initrd_filename);
365                 exit(1);
366             }
367             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
368             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
369         }
370         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
371             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
372             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
373                              machine->kernel_cmdline);
374             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
375                               machine->kernel_cmdline);
376             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
377                            strlen(machine->kernel_cmdline) + 1);
378         }
379         boot_device = 'm';
380     } else {
381         boot_device = machine->boot_config.order[0];
382     }
383 
384     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
385     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
386     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
387 
388     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
389     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
390     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
391 
392     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
393     if (kvm_enabled()) {
394         uint8_t *hypercall;
395 
396         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
397         hypercall = g_malloc(16);
398         kvmppc_get_hypercall(env, hypercall, 16);
399         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
400         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
401     } else {
402         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
403     }
404     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
405     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
406 
407     /* Prepare firmware configuration for Open Hack'Ware */
408     if (m48t59) {
409         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
410                              boot_device,
411                              kernel_base, kernel_size,
412                              machine->kernel_cmdline,
413                              initrd_base, initrd_size,
414                              /* XXX: need an option to load a NVRAM image */
415                              0,
416                              graphic_width, graphic_height, graphic_depth);
417     }
418 }
419 
420 static void ibm_40p_machine_init(MachineClass *mc)
421 {
422     mc->desc = "IBM RS/6000 7020 (40p)",
423     mc->init = ibm_40p_init;
424     mc->max_cpus = 1;
425     mc->default_ram_size = 128 * MiB;
426     mc->block_default_type = IF_SCSI;
427     mc->default_boot_order = "c";
428     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
429     mc->default_display = "std";
430 }
431 
432 DEFINE_MACHINE("40p", ibm_40p_machine_init)
433