1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "hw/hw.h" 28 #include "hw/timer/m48t59.h" 29 #include "hw/i386/pc.h" 30 #include "hw/char/serial.h" 31 #include "hw/block/fdc.h" 32 #include "net/net.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/isa/isa.h" 35 #include "hw/pci/pci.h" 36 #include "hw/pci/pci_host.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/boards.h" 39 #include "qemu/error-report.h" 40 #include "qemu/log.h" 41 #include "hw/ide.h" 42 #include "hw/loader.h" 43 #include "hw/timer/mc146818rtc.h" 44 #include "hw/isa/pc87312.h" 45 #include "sysemu/block-backend.h" 46 #include "sysemu/arch_init.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "exec/address-spaces.h" 50 #include "trace.h" 51 #include "elf.h" 52 #include "qemu/cutils.h" 53 #include "kvm_ppc.h" 54 55 /* SMP is not enabled, for now */ 56 #define MAX_CPUS 1 57 58 #define MAX_IDE_BUS 2 59 60 #define CFG_ADDR 0xf0000510 61 62 #define BIOS_SIZE (1024 * 1024) 63 #define BIOS_FILENAME "ppc_rom.bin" 64 #define KERNEL_LOAD_ADDR 0x01000000 65 #define INITRD_LOAD_ADDR 0x01800000 66 67 /* Constants for devices init */ 68 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 69 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 70 static const int ide_irq[2] = { 13, 13 }; 71 72 #define NE2000_NB_MAX 6 73 74 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 75 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 76 77 /* ISA IO ports bridge */ 78 #define PPC_IO_BASE 0x80000000 79 80 /* PowerPC control and status registers */ 81 #if 0 // Not used 82 static struct { 83 /* IDs */ 84 uint32_t veni_devi; 85 uint32_t revi; 86 /* Control and status */ 87 uint32_t gcsr; 88 uint32_t xcfr; 89 uint32_t ct32; 90 uint32_t mcsr; 91 /* General purpose registers */ 92 uint32_t gprg[6]; 93 /* Exceptions */ 94 uint32_t feen; 95 uint32_t fest; 96 uint32_t fema; 97 uint32_t fecl; 98 uint32_t eeen; 99 uint32_t eest; 100 uint32_t eecl; 101 uint32_t eeint; 102 uint32_t eemck0; 103 uint32_t eemck1; 104 /* Error diagnostic */ 105 } XCSR; 106 107 static void PPC_XCSR_writeb (void *opaque, 108 hwaddr addr, uint32_t value) 109 { 110 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 111 value); 112 } 113 114 static void PPC_XCSR_writew (void *opaque, 115 hwaddr addr, uint32_t value) 116 { 117 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 118 value); 119 } 120 121 static void PPC_XCSR_writel (void *opaque, 122 hwaddr addr, uint32_t value) 123 { 124 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 125 value); 126 } 127 128 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) 129 { 130 uint32_t retval = 0; 131 132 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 133 retval); 134 135 return retval; 136 } 137 138 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) 139 { 140 uint32_t retval = 0; 141 142 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 143 retval); 144 145 return retval; 146 } 147 148 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) 149 { 150 uint32_t retval = 0; 151 152 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 153 retval); 154 155 return retval; 156 } 157 158 static const MemoryRegionOps PPC_XCSR_ops = { 159 .old_mmio = { 160 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, 161 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, 162 }, 163 .endianness = DEVICE_LITTLE_ENDIAN, 164 }; 165 166 #endif 167 168 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 169 typedef struct sysctrl_t { 170 qemu_irq reset_irq; 171 Nvram *nvram; 172 uint8_t state; 173 uint8_t syscontrol; 174 int contiguous_map; 175 qemu_irq contiguous_map_irq; 176 int endian; 177 } sysctrl_t; 178 179 enum { 180 STATE_HARDFILE = 0x01, 181 }; 182 183 static sysctrl_t *sysctrl; 184 185 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 186 { 187 sysctrl_t *sysctrl = opaque; 188 189 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 190 switch (addr) { 191 case 0x0092: 192 /* Special port 92 */ 193 /* Check soft reset asked */ 194 if (val & 0x01) { 195 qemu_irq_raise(sysctrl->reset_irq); 196 } else { 197 qemu_irq_lower(sysctrl->reset_irq); 198 } 199 /* Check LE mode */ 200 if (val & 0x02) { 201 sysctrl->endian = 1; 202 } else { 203 sysctrl->endian = 0; 204 } 205 break; 206 case 0x0800: 207 /* Motorola CPU configuration register : read-only */ 208 break; 209 case 0x0802: 210 /* Motorola base module feature register : read-only */ 211 break; 212 case 0x0803: 213 /* Motorola base module status register : read-only */ 214 break; 215 case 0x0808: 216 /* Hardfile light register */ 217 if (val & 1) 218 sysctrl->state |= STATE_HARDFILE; 219 else 220 sysctrl->state &= ~STATE_HARDFILE; 221 break; 222 case 0x0810: 223 /* Password protect 1 register */ 224 if (sysctrl->nvram != NULL) { 225 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 226 (k->toggle_lock)(sysctrl->nvram, 1); 227 } 228 break; 229 case 0x0812: 230 /* Password protect 2 register */ 231 if (sysctrl->nvram != NULL) { 232 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 233 (k->toggle_lock)(sysctrl->nvram, 2); 234 } 235 break; 236 case 0x0814: 237 /* L2 invalidate register */ 238 // tlb_flush(first_cpu, 1); 239 break; 240 case 0x081C: 241 /* system control register */ 242 sysctrl->syscontrol = val & 0x0F; 243 break; 244 case 0x0850: 245 /* I/O map type register */ 246 sysctrl->contiguous_map = val & 0x01; 247 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 248 break; 249 default: 250 printf("ERROR: unaffected IO port write: %04" PRIx32 251 " => %02" PRIx32"\n", addr, val); 252 break; 253 } 254 } 255 256 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 257 { 258 sysctrl_t *sysctrl = opaque; 259 uint32_t retval = 0xFF; 260 261 switch (addr) { 262 case 0x0092: 263 /* Special port 92 */ 264 retval = sysctrl->endian << 1; 265 break; 266 case 0x0800: 267 /* Motorola CPU configuration register */ 268 retval = 0xEF; /* MPC750 */ 269 break; 270 case 0x0802: 271 /* Motorola Base module feature register */ 272 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 273 break; 274 case 0x0803: 275 /* Motorola base module status register */ 276 retval = 0xE0; /* Standard MPC750 */ 277 break; 278 case 0x080C: 279 /* Equipment present register: 280 * no L2 cache 281 * no upgrade processor 282 * no cards in PCI slots 283 * SCSI fuse is bad 284 */ 285 retval = 0x3C; 286 break; 287 case 0x0810: 288 /* Motorola base module extended feature register */ 289 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 290 break; 291 case 0x0814: 292 /* L2 invalidate: don't care */ 293 break; 294 case 0x0818: 295 /* Keylock */ 296 retval = 0x00; 297 break; 298 case 0x081C: 299 /* system control register 300 * 7 - 6 / 1 - 0: L2 cache enable 301 */ 302 retval = sysctrl->syscontrol; 303 break; 304 case 0x0823: 305 /* */ 306 retval = 0x03; /* no L2 cache */ 307 break; 308 case 0x0850: 309 /* I/O map type register */ 310 retval = sysctrl->contiguous_map; 311 break; 312 default: 313 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 314 break; 315 } 316 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 317 318 return retval; 319 } 320 321 322 #define NVRAM_SIZE 0x2000 323 324 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 325 Error **errp) 326 { 327 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 328 } 329 330 static void ppc_prep_reset(void *opaque) 331 { 332 PowerPCCPU *cpu = opaque; 333 334 cpu_reset(CPU(cpu)); 335 } 336 337 static const MemoryRegionPortio prep_portio_list[] = { 338 /* System control ports */ 339 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 340 { 0x0800, 0x52, 1, 341 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 342 /* Special port to get debug messages from Open-Firmware */ 343 { 0x0F00, 4, 1, .write = PPC_debug_write, }, 344 PORTIO_END_OF_LIST(), 345 }; 346 347 static PortioList prep_port_list; 348 349 /*****************************************************************************/ 350 /* NVRAM helpers */ 351 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 352 { 353 NvramClass *k = NVRAM_GET_CLASS(nvram); 354 return (k->read)(nvram, addr); 355 } 356 357 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 358 { 359 NvramClass *k = NVRAM_GET_CLASS(nvram); 360 (k->write)(nvram, addr, val); 361 } 362 363 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 364 { 365 nvram_write(nvram, addr, value); 366 } 367 368 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 369 { 370 return nvram_read(nvram, addr); 371 } 372 373 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 374 { 375 nvram_write(nvram, addr, value >> 8); 376 nvram_write(nvram, addr + 1, value & 0xFF); 377 } 378 379 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 380 { 381 uint16_t tmp; 382 383 tmp = nvram_read(nvram, addr) << 8; 384 tmp |= nvram_read(nvram, addr + 1); 385 386 return tmp; 387 } 388 389 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 390 { 391 nvram_write(nvram, addr, value >> 24); 392 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 393 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 394 nvram_write(nvram, addr + 3, value & 0xFF); 395 } 396 397 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 398 uint32_t max) 399 { 400 int i; 401 402 for (i = 0; i < max && str[i] != '\0'; i++) { 403 nvram_write(nvram, addr + i, str[i]); 404 } 405 nvram_write(nvram, addr + i, str[i]); 406 nvram_write(nvram, addr + max - 1, '\0'); 407 } 408 409 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 410 { 411 uint16_t tmp; 412 uint16_t pd, pd1, pd2; 413 414 tmp = prev >> 8; 415 pd = prev ^ value; 416 pd1 = pd & 0x000F; 417 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 418 tmp ^= (pd1 << 3) | (pd1 << 8); 419 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 420 421 return tmp; 422 } 423 424 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 425 { 426 uint32_t i; 427 uint16_t crc = 0xFFFF; 428 int odd; 429 430 odd = count & 1; 431 count &= ~1; 432 for (i = 0; i != count; i++) { 433 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 434 } 435 if (odd) { 436 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 437 } 438 439 return crc; 440 } 441 442 #define CMDLINE_ADDR 0x017ff000 443 444 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 445 const char *arch, 446 uint32_t RAM_size, int boot_device, 447 uint32_t kernel_image, uint32_t kernel_size, 448 const char *cmdline, 449 uint32_t initrd_image, uint32_t initrd_size, 450 uint32_t NVRAM_image, 451 int width, int height, int depth) 452 { 453 uint16_t crc; 454 455 /* Set parameters for Open Hack'Ware BIOS */ 456 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 457 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 458 NVRAM_set_word(nvram, 0x14, NVRAM_size); 459 NVRAM_set_string(nvram, 0x20, arch, 16); 460 NVRAM_set_lword(nvram, 0x30, RAM_size); 461 NVRAM_set_byte(nvram, 0x34, boot_device); 462 NVRAM_set_lword(nvram, 0x38, kernel_image); 463 NVRAM_set_lword(nvram, 0x3C, kernel_size); 464 if (cmdline) { 465 /* XXX: put the cmdline in NVRAM too ? */ 466 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 467 cmdline); 468 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 469 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 470 } else { 471 NVRAM_set_lword(nvram, 0x40, 0); 472 NVRAM_set_lword(nvram, 0x44, 0); 473 } 474 NVRAM_set_lword(nvram, 0x48, initrd_image); 475 NVRAM_set_lword(nvram, 0x4C, initrd_size); 476 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 477 478 NVRAM_set_word(nvram, 0x54, width); 479 NVRAM_set_word(nvram, 0x56, height); 480 NVRAM_set_word(nvram, 0x58, depth); 481 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 482 NVRAM_set_word(nvram, 0xFC, crc); 483 484 return 0; 485 } 486 487 /* PowerPC PREP hardware initialisation */ 488 static void ppc_prep_init(MachineState *machine) 489 { 490 ram_addr_t ram_size = machine->ram_size; 491 const char *kernel_filename = machine->kernel_filename; 492 const char *kernel_cmdline = machine->kernel_cmdline; 493 const char *initrd_filename = machine->initrd_filename; 494 const char *boot_device = machine->boot_order; 495 MemoryRegion *sysmem = get_system_memory(); 496 PowerPCCPU *cpu = NULL; 497 CPUPPCState *env = NULL; 498 Nvram *m48t59; 499 #if 0 500 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 501 #endif 502 int linux_boot, i, nb_nics1; 503 MemoryRegion *ram = g_new(MemoryRegion, 1); 504 uint32_t kernel_base, initrd_base; 505 long kernel_size, initrd_size; 506 DeviceState *dev; 507 PCIHostState *pcihost; 508 PCIBus *pci_bus; 509 PCIDevice *pci; 510 ISABus *isa_bus; 511 ISADevice *isa; 512 int ppc_boot_device; 513 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 514 515 sysctrl = g_malloc0(sizeof(sysctrl_t)); 516 517 linux_boot = (kernel_filename != NULL); 518 519 /* init CPUs */ 520 if (machine->cpu_model == NULL) 521 machine->cpu_model = "602"; 522 for (i = 0; i < smp_cpus; i++) { 523 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 524 machine->cpu_model)); 525 if (cpu == NULL) { 526 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 527 exit(1); 528 } 529 env = &cpu->env; 530 531 if (env->flags & POWERPC_FLAG_RTC_CLK) { 532 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 533 cpu_ppc_tb_init(env, 7812500UL); 534 } else { 535 /* Set time-base frequency to 100 Mhz */ 536 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 537 } 538 qemu_register_reset(ppc_prep_reset, cpu); 539 } 540 541 /* allocate RAM */ 542 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 543 memory_region_add_subregion(sysmem, 0, ram); 544 545 if (linux_boot) { 546 kernel_base = KERNEL_LOAD_ADDR; 547 /* now we can load the kernel */ 548 kernel_size = load_image_targphys(kernel_filename, kernel_base, 549 ram_size - kernel_base); 550 if (kernel_size < 0) { 551 error_report("could not load kernel '%s'", kernel_filename); 552 exit(1); 553 } 554 /* load initrd */ 555 if (initrd_filename) { 556 initrd_base = INITRD_LOAD_ADDR; 557 initrd_size = load_image_targphys(initrd_filename, initrd_base, 558 ram_size - initrd_base); 559 if (initrd_size < 0) { 560 error_report("could not load initial ram disk '%s'", 561 initrd_filename); 562 exit(1); 563 } 564 } else { 565 initrd_base = 0; 566 initrd_size = 0; 567 } 568 ppc_boot_device = 'm'; 569 } else { 570 kernel_base = 0; 571 kernel_size = 0; 572 initrd_base = 0; 573 initrd_size = 0; 574 ppc_boot_device = '\0'; 575 /* For now, OHW cannot boot from the network. */ 576 for (i = 0; boot_device[i] != '\0'; i++) { 577 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 578 ppc_boot_device = boot_device[i]; 579 break; 580 } 581 } 582 if (ppc_boot_device == '\0') { 583 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 584 exit(1); 585 } 586 } 587 588 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 589 error_report("Only 6xx bus is supported on PREP machine"); 590 exit(1); 591 } 592 593 dev = qdev_create(NULL, "raven-pcihost"); 594 if (bios_name == NULL) { 595 bios_name = BIOS_FILENAME; 596 } 597 qdev_prop_set_string(dev, "bios-name", bios_name); 598 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 599 pcihost = PCI_HOST_BRIDGE(dev); 600 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 601 qdev_init_nofail(dev); 602 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 603 if (pci_bus == NULL) { 604 fprintf(stderr, "Couldn't create PCI host controller.\n"); 605 exit(1); 606 } 607 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 608 609 /* PCI -> ISA bridge */ 610 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 611 cpu = POWERPC_CPU(first_cpu); 612 qdev_connect_gpio_out(&pci->qdev, 0, 613 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 614 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 615 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 616 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 617 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 618 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 619 620 /* Super I/O (parallel + serial ports) */ 621 isa = isa_create(isa_bus, TYPE_PC87312); 622 dev = DEVICE(isa); 623 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 624 qdev_init_nofail(dev); 625 626 /* init basic PC hardware */ 627 pci_vga_init(pci_bus); 628 629 nb_nics1 = nb_nics; 630 if (nb_nics1 > NE2000_NB_MAX) 631 nb_nics1 = NE2000_NB_MAX; 632 for(i = 0; i < nb_nics1; i++) { 633 if (nd_table[i].model == NULL) { 634 nd_table[i].model = g_strdup("ne2k_isa"); 635 } 636 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 637 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 638 &nd_table[i]); 639 } else { 640 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 641 } 642 } 643 644 ide_drive_get(hd, ARRAY_SIZE(hd)); 645 for(i = 0; i < MAX_IDE_BUS; i++) { 646 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 647 hd[2 * i], 648 hd[2 * i + 1]); 649 } 650 isa_create_simple(isa_bus, "i8042"); 651 652 cpu = POWERPC_CPU(first_cpu); 653 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 654 655 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 656 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 657 658 /* PowerPC control and status register group */ 659 #if 0 660 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); 661 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); 662 #endif 663 664 if (machine_usb(machine)) { 665 pci_create_simple(pci_bus, -1, "pci-ohci"); 666 } 667 668 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 669 if (m48t59 == NULL) 670 return; 671 sysctrl->nvram = m48t59; 672 673 /* Initialise NVRAM */ 674 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 675 ppc_boot_device, 676 kernel_base, kernel_size, 677 kernel_cmdline, 678 initrd_base, initrd_size, 679 /* XXX: need an option to load a NVRAM image */ 680 0, 681 graphic_width, graphic_height, graphic_depth); 682 } 683 684 static void prep_machine_init(MachineClass *mc) 685 { 686 mc->desc = "PowerPC PREP platform"; 687 mc->init = ppc_prep_init; 688 mc->block_default_type = IF_IDE; 689 mc->max_cpus = MAX_CPUS; 690 mc->default_boot_order = "cad"; 691 } 692 693 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 694 { 695 uint16_t checksum = *(uint16_t *)opaque; 696 ISADevice *rtc; 697 698 if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) { 699 rtc = ISA_DEVICE(dev); 700 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 701 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 702 rtc_set_memory(rtc, 0x2f, checksum >> 8); 703 rtc_set_memory(rtc, 0x3f, checksum >> 8); 704 } 705 return 0; 706 } 707 708 static void ibm_40p_init(MachineState *machine) 709 { 710 CPUPPCState *env = NULL; 711 uint16_t cmos_checksum; 712 PowerPCCPU *cpu; 713 DeviceState *dev; 714 SysBusDevice *pcihost; 715 Nvram *m48t59 = NULL; 716 PCIBus *pci_bus; 717 ISABus *isa_bus; 718 void *fw_cfg; 719 int i; 720 uint32_t kernel_base = 0, initrd_base = 0; 721 long kernel_size = 0, initrd_size = 0; 722 char boot_device; 723 724 /* init CPU */ 725 if (!machine->cpu_model) { 726 machine->cpu_model = "604"; 727 } 728 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); 729 if (!cpu) { 730 error_report("could not initialize CPU '%s'", 731 machine->cpu_model); 732 exit(1); 733 } 734 env = &cpu->env; 735 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 736 error_report("only 6xx bus is supported on this machine"); 737 exit(1); 738 } 739 740 if (env->flags & POWERPC_FLAG_RTC_CLK) { 741 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 742 cpu_ppc_tb_init(env, 7812500UL); 743 } else { 744 /* Set time-base frequency to 100 Mhz */ 745 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 746 } 747 qemu_register_reset(ppc_prep_reset, cpu); 748 749 /* PCI host */ 750 dev = qdev_create(NULL, "raven-pcihost"); 751 if (!bios_name) { 752 bios_name = BIOS_FILENAME; 753 } 754 qdev_prop_set_string(dev, "bios-name", bios_name); 755 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 756 pcihost = SYS_BUS_DEVICE(dev); 757 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 758 qdev_init_nofail(dev); 759 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 760 if (!pci_bus) { 761 error_report("could not create PCI host controller"); 762 exit(1); 763 } 764 765 /* PCI -> ISA bridge */ 766 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 767 qdev_connect_gpio_out(dev, 0, 768 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 769 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15)); 770 sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13)); 771 sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15)); 772 sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13)); 773 isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); 774 775 /* Memory controller */ 776 dev = DEVICE(isa_create(isa_bus, "rs6000-mc")); 777 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 778 qdev_init_nofail(dev); 779 780 /* initialize CMOS checksums */ 781 cmos_checksum = 0x6aa9; 782 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 783 &cmos_checksum); 784 785 /* add some more devices */ 786 if (defaults_enabled()) { 787 isa_create_simple(isa_bus, "i8042"); 788 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 789 790 dev = DEVICE(isa_create(isa_bus, "cs4231a")); 791 qdev_prop_set_uint32(dev, "iobase", 0x830); 792 qdev_prop_set_uint32(dev, "irq", 10); 793 qdev_init_nofail(dev); 794 795 dev = DEVICE(isa_create(isa_bus, "pc87312")); 796 qdev_prop_set_uint32(dev, "config", 12); 797 qdev_init_nofail(dev); 798 799 dev = DEVICE(isa_create(isa_bus, "prep-systemio")); 800 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 801 qdev_prop_set_uint32(dev, "equipment", 0xc0); 802 qdev_init_nofail(dev); 803 804 pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810"); 805 806 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 807 pci_vga_init(pci_bus); 808 809 for (i = 0; i < nb_nics; i++) { 810 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 811 i == 0 ? "3" : NULL); 812 } 813 } 814 815 /* Prepare firmware configuration for OpenBIOS */ 816 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 817 818 if (machine->kernel_filename) { 819 /* load kernel */ 820 kernel_base = KERNEL_LOAD_ADDR; 821 kernel_size = load_image_targphys(machine->kernel_filename, 822 kernel_base, 823 machine->ram_size - kernel_base); 824 if (kernel_size < 0) { 825 error_report("could not load kernel '%s'", 826 machine->kernel_filename); 827 exit(1); 828 } 829 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 830 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 831 /* load initrd */ 832 if (machine->initrd_filename) { 833 initrd_base = INITRD_LOAD_ADDR; 834 initrd_size = load_image_targphys(machine->initrd_filename, 835 initrd_base, 836 machine->ram_size - initrd_base); 837 if (initrd_size < 0) { 838 error_report("could not load initial ram disk '%s'", 839 machine->initrd_filename); 840 exit(1); 841 } 842 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 843 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 844 } 845 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 846 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 847 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 848 machine->kernel_cmdline); 849 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 850 machine->kernel_cmdline); 851 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 852 strlen(machine->kernel_cmdline) + 1); 853 } 854 boot_device = 'm'; 855 } else { 856 boot_device = machine->boot_order[0]; 857 } 858 859 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 860 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 861 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 862 863 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 864 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 865 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 866 867 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 868 if (kvm_enabled()) { 869 #ifdef CONFIG_KVM 870 uint8_t *hypercall; 871 872 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 873 hypercall = g_malloc(16); 874 kvmppc_get_hypercall(env, hypercall, 16); 875 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 876 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 877 #endif 878 } else { 879 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 880 } 881 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 882 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 883 884 /* Prepare firmware configuration for Open Hack'Ware */ 885 if (m48t59) { 886 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 887 boot_device, 888 kernel_base, kernel_size, 889 machine->kernel_cmdline, 890 initrd_base, initrd_size, 891 /* XXX: need an option to load a NVRAM image */ 892 0, 893 graphic_width, graphic_height, graphic_depth); 894 } 895 } 896 897 static void ibm_40p_machine_init(MachineClass *mc) 898 { 899 mc->desc = "IBM RS/6000 7020 (40p)", 900 mc->init = ibm_40p_init; 901 mc->max_cpus = 1; 902 mc->pci_allow_0_address = true; 903 mc->default_ram_size = 128 * M_BYTE; 904 mc->block_default_type = IF_SCSI; 905 mc->default_boot_order = "c"; 906 } 907 908 DEFINE_MACHINE("40p", ibm_40p_machine_init) 909 DEFINE_MACHINE("prep", prep_machine_init) 910