1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/timer/m48t59.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/block/fdc.h" 29 #include "net/net.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/isa/isa.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/boards.h" 36 #include "qemu/error-report.h" 37 #include "qemu/log.h" 38 #include "hw/ide.h" 39 #include "hw/loader.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/isa/pc87312.h" 42 #include "sysemu/block-backend.h" 43 #include "sysemu/arch_init.h" 44 #include "sysemu/qtest.h" 45 #include "exec/address-spaces.h" 46 #include "trace.h" 47 #include "elf.h" 48 49 /* SMP is not enabled, for now */ 50 #define MAX_CPUS 1 51 52 #define MAX_IDE_BUS 2 53 54 #define BIOS_SIZE (1024 * 1024) 55 #define BIOS_FILENAME "ppc_rom.bin" 56 #define KERNEL_LOAD_ADDR 0x01000000 57 #define INITRD_LOAD_ADDR 0x01800000 58 59 /* Constants for devices init */ 60 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 61 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 62 static const int ide_irq[2] = { 13, 13 }; 63 64 #define NE2000_NB_MAX 6 65 66 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 67 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 68 69 /* ISA IO ports bridge */ 70 #define PPC_IO_BASE 0x80000000 71 72 /* PowerPC control and status registers */ 73 #if 0 // Not used 74 static struct { 75 /* IDs */ 76 uint32_t veni_devi; 77 uint32_t revi; 78 /* Control and status */ 79 uint32_t gcsr; 80 uint32_t xcfr; 81 uint32_t ct32; 82 uint32_t mcsr; 83 /* General purpose registers */ 84 uint32_t gprg[6]; 85 /* Exceptions */ 86 uint32_t feen; 87 uint32_t fest; 88 uint32_t fema; 89 uint32_t fecl; 90 uint32_t eeen; 91 uint32_t eest; 92 uint32_t eecl; 93 uint32_t eeint; 94 uint32_t eemck0; 95 uint32_t eemck1; 96 /* Error diagnostic */ 97 } XCSR; 98 99 static void PPC_XCSR_writeb (void *opaque, 100 hwaddr addr, uint32_t value) 101 { 102 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 103 value); 104 } 105 106 static void PPC_XCSR_writew (void *opaque, 107 hwaddr addr, uint32_t value) 108 { 109 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 110 value); 111 } 112 113 static void PPC_XCSR_writel (void *opaque, 114 hwaddr addr, uint32_t value) 115 { 116 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 117 value); 118 } 119 120 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) 121 { 122 uint32_t retval = 0; 123 124 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 125 retval); 126 127 return retval; 128 } 129 130 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) 131 { 132 uint32_t retval = 0; 133 134 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 135 retval); 136 137 return retval; 138 } 139 140 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) 141 { 142 uint32_t retval = 0; 143 144 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 145 retval); 146 147 return retval; 148 } 149 150 static const MemoryRegionOps PPC_XCSR_ops = { 151 .old_mmio = { 152 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, 153 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, 154 }, 155 .endianness = DEVICE_LITTLE_ENDIAN, 156 }; 157 158 #endif 159 160 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 161 typedef struct sysctrl_t { 162 qemu_irq reset_irq; 163 Nvram *nvram; 164 uint8_t state; 165 uint8_t syscontrol; 166 int contiguous_map; 167 qemu_irq contiguous_map_irq; 168 int endian; 169 } sysctrl_t; 170 171 enum { 172 STATE_HARDFILE = 0x01, 173 }; 174 175 static sysctrl_t *sysctrl; 176 177 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 178 { 179 sysctrl_t *sysctrl = opaque; 180 181 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 182 switch (addr) { 183 case 0x0092: 184 /* Special port 92 */ 185 /* Check soft reset asked */ 186 if (val & 0x01) { 187 qemu_irq_raise(sysctrl->reset_irq); 188 } else { 189 qemu_irq_lower(sysctrl->reset_irq); 190 } 191 /* Check LE mode */ 192 if (val & 0x02) { 193 sysctrl->endian = 1; 194 } else { 195 sysctrl->endian = 0; 196 } 197 break; 198 case 0x0800: 199 /* Motorola CPU configuration register : read-only */ 200 break; 201 case 0x0802: 202 /* Motorola base module feature register : read-only */ 203 break; 204 case 0x0803: 205 /* Motorola base module status register : read-only */ 206 break; 207 case 0x0808: 208 /* Hardfile light register */ 209 if (val & 1) 210 sysctrl->state |= STATE_HARDFILE; 211 else 212 sysctrl->state &= ~STATE_HARDFILE; 213 break; 214 case 0x0810: 215 /* Password protect 1 register */ 216 if (sysctrl->nvram != NULL) { 217 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 218 (k->toggle_lock)(sysctrl->nvram, 1); 219 } 220 break; 221 case 0x0812: 222 /* Password protect 2 register */ 223 if (sysctrl->nvram != NULL) { 224 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 225 (k->toggle_lock)(sysctrl->nvram, 2); 226 } 227 break; 228 case 0x0814: 229 /* L2 invalidate register */ 230 // tlb_flush(first_cpu, 1); 231 break; 232 case 0x081C: 233 /* system control register */ 234 sysctrl->syscontrol = val & 0x0F; 235 break; 236 case 0x0850: 237 /* I/O map type register */ 238 sysctrl->contiguous_map = val & 0x01; 239 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 240 break; 241 default: 242 printf("ERROR: unaffected IO port write: %04" PRIx32 243 " => %02" PRIx32"\n", addr, val); 244 break; 245 } 246 } 247 248 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 249 { 250 sysctrl_t *sysctrl = opaque; 251 uint32_t retval = 0xFF; 252 253 switch (addr) { 254 case 0x0092: 255 /* Special port 92 */ 256 retval = sysctrl->endian << 1; 257 break; 258 case 0x0800: 259 /* Motorola CPU configuration register */ 260 retval = 0xEF; /* MPC750 */ 261 break; 262 case 0x0802: 263 /* Motorola Base module feature register */ 264 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 265 break; 266 case 0x0803: 267 /* Motorola base module status register */ 268 retval = 0xE0; /* Standard MPC750 */ 269 break; 270 case 0x080C: 271 /* Equipment present register: 272 * no L2 cache 273 * no upgrade processor 274 * no cards in PCI slots 275 * SCSI fuse is bad 276 */ 277 retval = 0x3C; 278 break; 279 case 0x0810: 280 /* Motorola base module extended feature register */ 281 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 282 break; 283 case 0x0814: 284 /* L2 invalidate: don't care */ 285 break; 286 case 0x0818: 287 /* Keylock */ 288 retval = 0x00; 289 break; 290 case 0x081C: 291 /* system control register 292 * 7 - 6 / 1 - 0: L2 cache enable 293 */ 294 retval = sysctrl->syscontrol; 295 break; 296 case 0x0823: 297 /* */ 298 retval = 0x03; /* no L2 cache */ 299 break; 300 case 0x0850: 301 /* I/O map type register */ 302 retval = sysctrl->contiguous_map; 303 break; 304 default: 305 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 306 break; 307 } 308 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 309 310 return retval; 311 } 312 313 314 #define NVRAM_SIZE 0x2000 315 316 static void ppc_prep_reset(void *opaque) 317 { 318 PowerPCCPU *cpu = opaque; 319 320 cpu_reset(CPU(cpu)); 321 } 322 323 static const MemoryRegionPortio prep_portio_list[] = { 324 /* System control ports */ 325 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 326 { 0x0800, 0x52, 1, 327 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 328 /* Special port to get debug messages from Open-Firmware */ 329 { 0x0F00, 4, 1, .write = PPC_debug_write, }, 330 PORTIO_END_OF_LIST(), 331 }; 332 333 static PortioList prep_port_list; 334 335 /*****************************************************************************/ 336 /* NVRAM helpers */ 337 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 338 { 339 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 340 return (k->read)(nvram, addr); 341 } 342 343 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 344 { 345 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 346 (k->write)(nvram, addr, val); 347 } 348 349 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 350 { 351 nvram_write(nvram, addr, value); 352 } 353 354 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 355 { 356 return nvram_read(nvram, addr); 357 } 358 359 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 360 { 361 nvram_write(nvram, addr, value >> 8); 362 nvram_write(nvram, addr + 1, value & 0xFF); 363 } 364 365 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 366 { 367 uint16_t tmp; 368 369 tmp = nvram_read(nvram, addr) << 8; 370 tmp |= nvram_read(nvram, addr + 1); 371 372 return tmp; 373 } 374 375 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 376 { 377 nvram_write(nvram, addr, value >> 24); 378 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 379 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 380 nvram_write(nvram, addr + 3, value & 0xFF); 381 } 382 383 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 384 uint32_t max) 385 { 386 int i; 387 388 for (i = 0; i < max && str[i] != '\0'; i++) { 389 nvram_write(nvram, addr + i, str[i]); 390 } 391 nvram_write(nvram, addr + i, str[i]); 392 nvram_write(nvram, addr + max - 1, '\0'); 393 } 394 395 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 396 { 397 uint16_t tmp; 398 uint16_t pd, pd1, pd2; 399 400 tmp = prev >> 8; 401 pd = prev ^ value; 402 pd1 = pd & 0x000F; 403 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 404 tmp ^= (pd1 << 3) | (pd1 << 8); 405 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 406 407 return tmp; 408 } 409 410 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 411 { 412 uint32_t i; 413 uint16_t crc = 0xFFFF; 414 int odd; 415 416 odd = count & 1; 417 count &= ~1; 418 for (i = 0; i != count; i++) { 419 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 420 } 421 if (odd) { 422 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 423 } 424 425 return crc; 426 } 427 428 #define CMDLINE_ADDR 0x017ff000 429 430 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 431 const char *arch, 432 uint32_t RAM_size, int boot_device, 433 uint32_t kernel_image, uint32_t kernel_size, 434 const char *cmdline, 435 uint32_t initrd_image, uint32_t initrd_size, 436 uint32_t NVRAM_image, 437 int width, int height, int depth) 438 { 439 uint16_t crc; 440 441 /* Set parameters for Open Hack'Ware BIOS */ 442 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 443 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 444 NVRAM_set_word(nvram, 0x14, NVRAM_size); 445 NVRAM_set_string(nvram, 0x20, arch, 16); 446 NVRAM_set_lword(nvram, 0x30, RAM_size); 447 NVRAM_set_byte(nvram, 0x34, boot_device); 448 NVRAM_set_lword(nvram, 0x38, kernel_image); 449 NVRAM_set_lword(nvram, 0x3C, kernel_size); 450 if (cmdline) { 451 /* XXX: put the cmdline in NVRAM too ? */ 452 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 453 cmdline); 454 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 455 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 456 } else { 457 NVRAM_set_lword(nvram, 0x40, 0); 458 NVRAM_set_lword(nvram, 0x44, 0); 459 } 460 NVRAM_set_lword(nvram, 0x48, initrd_image); 461 NVRAM_set_lword(nvram, 0x4C, initrd_size); 462 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 463 464 NVRAM_set_word(nvram, 0x54, width); 465 NVRAM_set_word(nvram, 0x56, height); 466 NVRAM_set_word(nvram, 0x58, depth); 467 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 468 NVRAM_set_word(nvram, 0xFC, crc); 469 470 return 0; 471 } 472 473 /* PowerPC PREP hardware initialisation */ 474 static void ppc_prep_init(MachineState *machine) 475 { 476 ram_addr_t ram_size = machine->ram_size; 477 const char *kernel_filename = machine->kernel_filename; 478 const char *kernel_cmdline = machine->kernel_cmdline; 479 const char *initrd_filename = machine->initrd_filename; 480 const char *boot_device = machine->boot_order; 481 MemoryRegion *sysmem = get_system_memory(); 482 PowerPCCPU *cpu = NULL; 483 CPUPPCState *env = NULL; 484 Nvram *m48t59; 485 #if 0 486 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 487 #endif 488 int linux_boot, i, nb_nics1; 489 MemoryRegion *ram = g_new(MemoryRegion, 1); 490 uint32_t kernel_base, initrd_base; 491 long kernel_size, initrd_size; 492 DeviceState *dev; 493 PCIHostState *pcihost; 494 PCIBus *pci_bus; 495 PCIDevice *pci; 496 ISABus *isa_bus; 497 ISADevice *isa; 498 int ppc_boot_device; 499 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 500 501 sysctrl = g_malloc0(sizeof(sysctrl_t)); 502 503 linux_boot = (kernel_filename != NULL); 504 505 /* init CPUs */ 506 if (machine->cpu_model == NULL) 507 machine->cpu_model = "602"; 508 for (i = 0; i < smp_cpus; i++) { 509 cpu = cpu_ppc_init(machine->cpu_model); 510 if (cpu == NULL) { 511 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 512 exit(1); 513 } 514 env = &cpu->env; 515 516 if (env->flags & POWERPC_FLAG_RTC_CLK) { 517 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 518 cpu_ppc_tb_init(env, 7812500UL); 519 } else { 520 /* Set time-base frequency to 100 Mhz */ 521 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 522 } 523 qemu_register_reset(ppc_prep_reset, cpu); 524 } 525 526 /* allocate RAM */ 527 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 528 memory_region_add_subregion(sysmem, 0, ram); 529 530 if (linux_boot) { 531 kernel_base = KERNEL_LOAD_ADDR; 532 /* now we can load the kernel */ 533 kernel_size = load_image_targphys(kernel_filename, kernel_base, 534 ram_size - kernel_base); 535 if (kernel_size < 0) { 536 error_report("could not load kernel '%s'", kernel_filename); 537 exit(1); 538 } 539 /* load initrd */ 540 if (initrd_filename) { 541 initrd_base = INITRD_LOAD_ADDR; 542 initrd_size = load_image_targphys(initrd_filename, initrd_base, 543 ram_size - initrd_base); 544 if (initrd_size < 0) { 545 error_report("could not load initial ram disk '%s'", 546 initrd_filename); 547 exit(1); 548 } 549 } else { 550 initrd_base = 0; 551 initrd_size = 0; 552 } 553 ppc_boot_device = 'm'; 554 } else { 555 kernel_base = 0; 556 kernel_size = 0; 557 initrd_base = 0; 558 initrd_size = 0; 559 ppc_boot_device = '\0'; 560 /* For now, OHW cannot boot from the network. */ 561 for (i = 0; boot_device[i] != '\0'; i++) { 562 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 563 ppc_boot_device = boot_device[i]; 564 break; 565 } 566 } 567 if (ppc_boot_device == '\0') { 568 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 569 exit(1); 570 } 571 } 572 573 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 574 error_report("Only 6xx bus is supported on PREP machine"); 575 exit(1); 576 } 577 578 dev = qdev_create(NULL, "raven-pcihost"); 579 if (bios_name == NULL) { 580 bios_name = BIOS_FILENAME; 581 } 582 qdev_prop_set_string(dev, "bios-name", bios_name); 583 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 584 pcihost = PCI_HOST_BRIDGE(dev); 585 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 586 qdev_init_nofail(dev); 587 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 588 if (pci_bus == NULL) { 589 fprintf(stderr, "Couldn't create PCI host controller.\n"); 590 exit(1); 591 } 592 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 593 594 /* PCI -> ISA bridge */ 595 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 596 cpu = POWERPC_CPU(first_cpu); 597 qdev_connect_gpio_out(&pci->qdev, 0, 598 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 599 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 600 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 601 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 602 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 603 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 604 605 /* Super I/O (parallel + serial ports) */ 606 isa = isa_create(isa_bus, TYPE_PC87312); 607 dev = DEVICE(isa); 608 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 609 qdev_init_nofail(dev); 610 611 /* init basic PC hardware */ 612 pci_vga_init(pci_bus); 613 614 nb_nics1 = nb_nics; 615 if (nb_nics1 > NE2000_NB_MAX) 616 nb_nics1 = NE2000_NB_MAX; 617 for(i = 0; i < nb_nics1; i++) { 618 if (nd_table[i].model == NULL) { 619 nd_table[i].model = g_strdup("ne2k_isa"); 620 } 621 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 622 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 623 &nd_table[i]); 624 } else { 625 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 626 } 627 } 628 629 ide_drive_get(hd, ARRAY_SIZE(hd)); 630 for(i = 0; i < MAX_IDE_BUS; i++) { 631 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 632 hd[2 * i], 633 hd[2 * i + 1]); 634 } 635 isa_create_simple(isa_bus, "i8042"); 636 637 cpu = POWERPC_CPU(first_cpu); 638 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 639 640 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 641 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 642 643 /* PowerPC control and status register group */ 644 #if 0 645 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); 646 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); 647 #endif 648 649 if (usb_enabled()) { 650 pci_create_simple(pci_bus, -1, "pci-ohci"); 651 } 652 653 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 654 if (m48t59 == NULL) 655 return; 656 sysctrl->nvram = m48t59; 657 658 /* Initialise NVRAM */ 659 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 660 ppc_boot_device, 661 kernel_base, kernel_size, 662 kernel_cmdline, 663 initrd_base, initrd_size, 664 /* XXX: need an option to load a NVRAM image */ 665 0, 666 graphic_width, graphic_height, graphic_depth); 667 } 668 669 static void prep_machine_init(MachineClass *mc) 670 { 671 mc->desc = "PowerPC PREP platform"; 672 mc->init = ppc_prep_init; 673 mc->max_cpus = MAX_CPUS; 674 mc->default_boot_order = "cad"; 675 } 676 677 DEFINE_MACHINE("prep", prep_machine_init) 678