1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/timer/m48t59.h" 30 #include "hw/char/serial.h" 31 #include "hw/block/fdc.h" 32 #include "net/net.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/isa/isa.h" 35 #include "hw/pci/pci.h" 36 #include "hw/pci/pci_host.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/boards.h" 39 #include "qemu/error-report.h" 40 #include "qemu/log.h" 41 #include "hw/ide.h" 42 #include "hw/irq.h" 43 #include "hw/loader.h" 44 #include "hw/timer/mc146818rtc.h" 45 #include "hw/isa/pc87312.h" 46 #include "hw/net/ne2000-isa.h" 47 #include "sysemu/arch_init.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "sysemu/reset.h" 51 #include "exec/address-spaces.h" 52 #include "trace.h" 53 #include "elf.h" 54 #include "qemu/units.h" 55 #include "kvm_ppc.h" 56 57 /* SMP is not enabled, for now */ 58 #define MAX_CPUS 1 59 60 #define MAX_IDE_BUS 2 61 62 #define CFG_ADDR 0xf0000510 63 64 #define BIOS_SIZE (1 * MiB) 65 #define BIOS_FILENAME "ppc_rom.bin" 66 #define KERNEL_LOAD_ADDR 0x01000000 67 #define INITRD_LOAD_ADDR 0x01800000 68 69 /* Constants for devices init */ 70 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 71 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 72 static const int ide_irq[2] = { 13, 13 }; 73 74 #define NE2000_NB_MAX 6 75 76 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 77 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 78 79 /* ISA IO ports bridge */ 80 #define PPC_IO_BASE 0x80000000 81 82 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 83 typedef struct sysctrl_t { 84 qemu_irq reset_irq; 85 Nvram *nvram; 86 uint8_t state; 87 uint8_t syscontrol; 88 int contiguous_map; 89 qemu_irq contiguous_map_irq; 90 int endian; 91 } sysctrl_t; 92 93 enum { 94 STATE_HARDFILE = 0x01, 95 }; 96 97 static sysctrl_t *sysctrl; 98 99 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 100 { 101 sysctrl_t *sysctrl = opaque; 102 103 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 104 switch (addr) { 105 case 0x0092: 106 /* Special port 92 */ 107 /* Check soft reset asked */ 108 if (val & 0x01) { 109 qemu_irq_raise(sysctrl->reset_irq); 110 } else { 111 qemu_irq_lower(sysctrl->reset_irq); 112 } 113 /* Check LE mode */ 114 if (val & 0x02) { 115 sysctrl->endian = 1; 116 } else { 117 sysctrl->endian = 0; 118 } 119 break; 120 case 0x0800: 121 /* Motorola CPU configuration register : read-only */ 122 break; 123 case 0x0802: 124 /* Motorola base module feature register : read-only */ 125 break; 126 case 0x0803: 127 /* Motorola base module status register : read-only */ 128 break; 129 case 0x0808: 130 /* Hardfile light register */ 131 if (val & 1) 132 sysctrl->state |= STATE_HARDFILE; 133 else 134 sysctrl->state &= ~STATE_HARDFILE; 135 break; 136 case 0x0810: 137 /* Password protect 1 register */ 138 if (sysctrl->nvram != NULL) { 139 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 140 (k->toggle_lock)(sysctrl->nvram, 1); 141 } 142 break; 143 case 0x0812: 144 /* Password protect 2 register */ 145 if (sysctrl->nvram != NULL) { 146 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 147 (k->toggle_lock)(sysctrl->nvram, 2); 148 } 149 break; 150 case 0x0814: 151 /* L2 invalidate register */ 152 // tlb_flush(first_cpu, 1); 153 break; 154 case 0x081C: 155 /* system control register */ 156 sysctrl->syscontrol = val & 0x0F; 157 break; 158 case 0x0850: 159 /* I/O map type register */ 160 sysctrl->contiguous_map = val & 0x01; 161 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 162 break; 163 default: 164 printf("ERROR: unaffected IO port write: %04" PRIx32 165 " => %02" PRIx32"\n", addr, val); 166 break; 167 } 168 } 169 170 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 171 { 172 sysctrl_t *sysctrl = opaque; 173 uint32_t retval = 0xFF; 174 175 switch (addr) { 176 case 0x0092: 177 /* Special port 92 */ 178 retval = sysctrl->endian << 1; 179 break; 180 case 0x0800: 181 /* Motorola CPU configuration register */ 182 retval = 0xEF; /* MPC750 */ 183 break; 184 case 0x0802: 185 /* Motorola Base module feature register */ 186 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 187 break; 188 case 0x0803: 189 /* Motorola base module status register */ 190 retval = 0xE0; /* Standard MPC750 */ 191 break; 192 case 0x080C: 193 /* Equipment present register: 194 * no L2 cache 195 * no upgrade processor 196 * no cards in PCI slots 197 * SCSI fuse is bad 198 */ 199 retval = 0x3C; 200 break; 201 case 0x0810: 202 /* Motorola base module extended feature register */ 203 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 204 break; 205 case 0x0814: 206 /* L2 invalidate: don't care */ 207 break; 208 case 0x0818: 209 /* Keylock */ 210 retval = 0x00; 211 break; 212 case 0x081C: 213 /* system control register 214 * 7 - 6 / 1 - 0: L2 cache enable 215 */ 216 retval = sysctrl->syscontrol; 217 break; 218 case 0x0823: 219 /* */ 220 retval = 0x03; /* no L2 cache */ 221 break; 222 case 0x0850: 223 /* I/O map type register */ 224 retval = sysctrl->contiguous_map; 225 break; 226 default: 227 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 228 break; 229 } 230 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 231 232 return retval; 233 } 234 235 236 #define NVRAM_SIZE 0x2000 237 238 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 239 Error **errp) 240 { 241 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 242 } 243 244 static void ppc_prep_reset(void *opaque) 245 { 246 PowerPCCPU *cpu = opaque; 247 248 cpu_reset(CPU(cpu)); 249 } 250 251 static const MemoryRegionPortio prep_portio_list[] = { 252 /* System control ports */ 253 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 254 { 0x0800, 0x52, 1, 255 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 256 /* Special port to get debug messages from Open-Firmware */ 257 { 0x0F00, 4, 1, .write = PPC_debug_write, }, 258 PORTIO_END_OF_LIST(), 259 }; 260 261 static PortioList prep_port_list; 262 263 /*****************************************************************************/ 264 /* NVRAM helpers */ 265 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 266 { 267 NvramClass *k = NVRAM_GET_CLASS(nvram); 268 return (k->read)(nvram, addr); 269 } 270 271 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 272 { 273 NvramClass *k = NVRAM_GET_CLASS(nvram); 274 (k->write)(nvram, addr, val); 275 } 276 277 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 278 { 279 nvram_write(nvram, addr, value); 280 } 281 282 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 283 { 284 return nvram_read(nvram, addr); 285 } 286 287 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 288 { 289 nvram_write(nvram, addr, value >> 8); 290 nvram_write(nvram, addr + 1, value & 0xFF); 291 } 292 293 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 294 { 295 uint16_t tmp; 296 297 tmp = nvram_read(nvram, addr) << 8; 298 tmp |= nvram_read(nvram, addr + 1); 299 300 return tmp; 301 } 302 303 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 304 { 305 nvram_write(nvram, addr, value >> 24); 306 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 307 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 308 nvram_write(nvram, addr + 3, value & 0xFF); 309 } 310 311 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 312 uint32_t max) 313 { 314 int i; 315 316 for (i = 0; i < max && str[i] != '\0'; i++) { 317 nvram_write(nvram, addr + i, str[i]); 318 } 319 nvram_write(nvram, addr + i, str[i]); 320 nvram_write(nvram, addr + max - 1, '\0'); 321 } 322 323 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 324 { 325 uint16_t tmp; 326 uint16_t pd, pd1, pd2; 327 328 tmp = prev >> 8; 329 pd = prev ^ value; 330 pd1 = pd & 0x000F; 331 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 332 tmp ^= (pd1 << 3) | (pd1 << 8); 333 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 334 335 return tmp; 336 } 337 338 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 339 { 340 uint32_t i; 341 uint16_t crc = 0xFFFF; 342 int odd; 343 344 odd = count & 1; 345 count &= ~1; 346 for (i = 0; i != count; i++) { 347 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 348 } 349 if (odd) { 350 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 351 } 352 353 return crc; 354 } 355 356 #define CMDLINE_ADDR 0x017ff000 357 358 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 359 const char *arch, 360 uint32_t RAM_size, int boot_device, 361 uint32_t kernel_image, uint32_t kernel_size, 362 const char *cmdline, 363 uint32_t initrd_image, uint32_t initrd_size, 364 uint32_t NVRAM_image, 365 int width, int height, int depth) 366 { 367 uint16_t crc; 368 369 /* Set parameters for Open Hack'Ware BIOS */ 370 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 371 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 372 NVRAM_set_word(nvram, 0x14, NVRAM_size); 373 NVRAM_set_string(nvram, 0x20, arch, 16); 374 NVRAM_set_lword(nvram, 0x30, RAM_size); 375 NVRAM_set_byte(nvram, 0x34, boot_device); 376 NVRAM_set_lword(nvram, 0x38, kernel_image); 377 NVRAM_set_lword(nvram, 0x3C, kernel_size); 378 if (cmdline) { 379 /* XXX: put the cmdline in NVRAM too ? */ 380 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 381 cmdline); 382 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 383 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 384 } else { 385 NVRAM_set_lword(nvram, 0x40, 0); 386 NVRAM_set_lword(nvram, 0x44, 0); 387 } 388 NVRAM_set_lword(nvram, 0x48, initrd_image); 389 NVRAM_set_lword(nvram, 0x4C, initrd_size); 390 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 391 392 NVRAM_set_word(nvram, 0x54, width); 393 NVRAM_set_word(nvram, 0x56, height); 394 NVRAM_set_word(nvram, 0x58, depth); 395 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 396 NVRAM_set_word(nvram, 0xFC, crc); 397 398 return 0; 399 } 400 401 /* PowerPC PREP hardware initialisation */ 402 static void ppc_prep_init(MachineState *machine) 403 { 404 ram_addr_t ram_size = machine->ram_size; 405 const char *kernel_filename = machine->kernel_filename; 406 const char *kernel_cmdline = machine->kernel_cmdline; 407 const char *initrd_filename = machine->initrd_filename; 408 const char *boot_device = machine->boot_order; 409 MemoryRegion *sysmem = get_system_memory(); 410 PowerPCCPU *cpu = NULL; 411 CPUPPCState *env = NULL; 412 Nvram *m48t59; 413 #if 0 414 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 415 #endif 416 int linux_boot, i, nb_nics1; 417 MemoryRegion *ram = g_new(MemoryRegion, 1); 418 uint32_t kernel_base, initrd_base; 419 long kernel_size, initrd_size; 420 DeviceState *dev; 421 PCIHostState *pcihost; 422 PCIBus *pci_bus; 423 PCIDevice *pci; 424 ISABus *isa_bus; 425 ISADevice *isa; 426 int ppc_boot_device; 427 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 428 429 sysctrl = g_malloc0(sizeof(sysctrl_t)); 430 431 linux_boot = (kernel_filename != NULL); 432 433 /* init CPUs */ 434 for (i = 0; i < machine->smp.cpus; i++) { 435 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 436 env = &cpu->env; 437 438 if (env->flags & POWERPC_FLAG_RTC_CLK) { 439 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 440 cpu_ppc_tb_init(env, 7812500UL); 441 } else { 442 /* Set time-base frequency to 100 Mhz */ 443 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 444 } 445 qemu_register_reset(ppc_prep_reset, cpu); 446 } 447 448 /* allocate RAM */ 449 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 450 memory_region_add_subregion(sysmem, 0, ram); 451 452 if (linux_boot) { 453 kernel_base = KERNEL_LOAD_ADDR; 454 /* now we can load the kernel */ 455 kernel_size = load_image_targphys(kernel_filename, kernel_base, 456 ram_size - kernel_base); 457 if (kernel_size < 0) { 458 error_report("could not load kernel '%s'", kernel_filename); 459 exit(1); 460 } 461 /* load initrd */ 462 if (initrd_filename) { 463 initrd_base = INITRD_LOAD_ADDR; 464 initrd_size = load_image_targphys(initrd_filename, initrd_base, 465 ram_size - initrd_base); 466 if (initrd_size < 0) { 467 error_report("could not load initial ram disk '%s'", 468 initrd_filename); 469 exit(1); 470 } 471 } else { 472 initrd_base = 0; 473 initrd_size = 0; 474 } 475 ppc_boot_device = 'm'; 476 } else { 477 kernel_base = 0; 478 kernel_size = 0; 479 initrd_base = 0; 480 initrd_size = 0; 481 ppc_boot_device = '\0'; 482 /* For now, OHW cannot boot from the network. */ 483 for (i = 0; boot_device[i] != '\0'; i++) { 484 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 485 ppc_boot_device = boot_device[i]; 486 break; 487 } 488 } 489 if (ppc_boot_device == '\0') { 490 error_report("No valid boot device for Mac99 machine"); 491 exit(1); 492 } 493 } 494 495 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 496 error_report("Only 6xx bus is supported on PREP machine"); 497 exit(1); 498 } 499 500 dev = qdev_create(NULL, "raven-pcihost"); 501 if (bios_name == NULL) { 502 bios_name = BIOS_FILENAME; 503 } 504 qdev_prop_set_string(dev, "bios-name", bios_name); 505 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 506 qdev_prop_set_bit(dev, "is-legacy-prep", true); 507 pcihost = PCI_HOST_BRIDGE(dev); 508 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 509 qdev_init_nofail(dev); 510 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 511 if (pci_bus == NULL) { 512 error_report("Couldn't create PCI host controller"); 513 exit(1); 514 } 515 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 516 517 /* PCI -> ISA bridge */ 518 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 519 cpu = POWERPC_CPU(first_cpu); 520 qdev_connect_gpio_out(&pci->qdev, 0, 521 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 522 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 523 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 524 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 525 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 526 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 527 528 /* Super I/O (parallel + serial ports) */ 529 isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO); 530 dev = DEVICE(isa); 531 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 532 qdev_init_nofail(dev); 533 534 /* init basic PC hardware */ 535 pci_vga_init(pci_bus); 536 537 nb_nics1 = nb_nics; 538 if (nb_nics1 > NE2000_NB_MAX) 539 nb_nics1 = NE2000_NB_MAX; 540 for(i = 0; i < nb_nics1; i++) { 541 if (nd_table[i].model == NULL) { 542 nd_table[i].model = g_strdup("ne2k_isa"); 543 } 544 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 545 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 546 &nd_table[i]); 547 } else { 548 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 549 } 550 } 551 552 ide_drive_get(hd, ARRAY_SIZE(hd)); 553 for(i = 0; i < MAX_IDE_BUS; i++) { 554 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 555 hd[2 * i], 556 hd[2 * i + 1]); 557 } 558 559 cpu = POWERPC_CPU(first_cpu); 560 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 561 562 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 563 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 564 565 /* 566 * PowerPC control and status register group: unimplemented, 567 * would be at address 0xFEFF0000. 568 */ 569 570 if (machine_usb(machine)) { 571 pci_create_simple(pci_bus, -1, "pci-ohci"); 572 } 573 574 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 575 if (m48t59 == NULL) 576 return; 577 sysctrl->nvram = m48t59; 578 579 /* Initialise NVRAM */ 580 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 581 ppc_boot_device, 582 kernel_base, kernel_size, 583 kernel_cmdline, 584 initrd_base, initrd_size, 585 /* XXX: need an option to load a NVRAM image */ 586 0, 587 graphic_width, graphic_height, graphic_depth); 588 } 589 590 static void prep_machine_init(MachineClass *mc) 591 { 592 mc->deprecation_reason = "use 40p machine type instead"; 593 mc->desc = "PowerPC PREP platform"; 594 mc->init = ppc_prep_init; 595 mc->block_default_type = IF_IDE; 596 mc->max_cpus = MAX_CPUS; 597 mc->default_boot_order = "cad"; 598 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602"); 599 mc->default_display = "std"; 600 } 601 602 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 603 { 604 uint16_t checksum = *(uint16_t *)opaque; 605 ISADevice *rtc; 606 607 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 608 rtc = ISA_DEVICE(dev); 609 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 610 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 611 rtc_set_memory(rtc, 0x2f, checksum >> 8); 612 rtc_set_memory(rtc, 0x3f, checksum >> 8); 613 614 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), 615 "date", NULL); 616 } 617 return 0; 618 } 619 620 static void ibm_40p_init(MachineState *machine) 621 { 622 CPUPPCState *env = NULL; 623 uint16_t cmos_checksum; 624 PowerPCCPU *cpu; 625 DeviceState *dev, *i82378_dev; 626 SysBusDevice *pcihost, *s; 627 Nvram *m48t59 = NULL; 628 PCIBus *pci_bus; 629 ISABus *isa_bus; 630 void *fw_cfg; 631 int i; 632 uint32_t kernel_base = 0, initrd_base = 0; 633 long kernel_size = 0, initrd_size = 0; 634 char boot_device; 635 636 /* init CPU */ 637 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 638 env = &cpu->env; 639 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 640 error_report("only 6xx bus is supported on this machine"); 641 exit(1); 642 } 643 644 if (env->flags & POWERPC_FLAG_RTC_CLK) { 645 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 646 cpu_ppc_tb_init(env, 7812500UL); 647 } else { 648 /* Set time-base frequency to 100 Mhz */ 649 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 650 } 651 qemu_register_reset(ppc_prep_reset, cpu); 652 653 /* PCI host */ 654 dev = qdev_create(NULL, "raven-pcihost"); 655 if (!bios_name) { 656 bios_name = "openbios-ppc"; 657 } 658 qdev_prop_set_string(dev, "bios-name", bios_name); 659 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 660 pcihost = SYS_BUS_DEVICE(dev); 661 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 662 qdev_init_nofail(dev); 663 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 664 if (!pci_bus) { 665 error_report("could not create PCI host controller"); 666 exit(1); 667 } 668 669 /* PCI -> ISA bridge */ 670 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 671 qdev_connect_gpio_out(i82378_dev, 0, 672 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 673 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); 674 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); 675 676 /* Memory controller */ 677 dev = DEVICE(isa_create(isa_bus, "rs6000-mc")); 678 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 679 qdev_init_nofail(dev); 680 681 /* RTC */ 682 dev = DEVICE(isa_create(isa_bus, TYPE_MC146818_RTC)); 683 qdev_prop_set_int32(dev, "base_year", 1900); 684 qdev_init_nofail(dev); 685 686 /* initialize CMOS checksums */ 687 cmos_checksum = 0x6aa9; 688 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 689 &cmos_checksum); 690 691 /* add some more devices */ 692 if (defaults_enabled()) { 693 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 694 695 dev = DEVICE(isa_create(isa_bus, "cs4231a")); 696 qdev_prop_set_uint32(dev, "iobase", 0x830); 697 qdev_prop_set_uint32(dev, "irq", 10); 698 qdev_init_nofail(dev); 699 700 dev = DEVICE(isa_create(isa_bus, "pc87312")); 701 qdev_prop_set_uint32(dev, "config", 12); 702 qdev_init_nofail(dev); 703 704 dev = DEVICE(isa_create(isa_bus, "prep-systemio")); 705 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 706 qdev_prop_set_uint32(dev, "equipment", 0xc0); 707 qdev_init_nofail(dev); 708 709 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), 710 "lsi53c810")); 711 lsi53c8xx_handle_legacy_cmdline(dev); 712 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); 713 714 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 715 pci_vga_init(pci_bus); 716 717 for (i = 0; i < nb_nics; i++) { 718 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 719 i == 0 ? "3" : NULL); 720 } 721 } 722 723 /* Prepare firmware configuration for OpenBIOS */ 724 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 725 fw_cfg = FW_CFG(dev); 726 qdev_prop_set_uint32(dev, "data_width", 1); 727 qdev_prop_set_bit(dev, "dma_enabled", false); 728 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 729 OBJECT(fw_cfg), NULL); 730 qdev_init_nofail(dev); 731 s = SYS_BUS_DEVICE(dev); 732 sysbus_mmio_map(s, 0, CFG_ADDR); 733 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 734 735 if (machine->kernel_filename) { 736 /* load kernel */ 737 kernel_base = KERNEL_LOAD_ADDR; 738 kernel_size = load_image_targphys(machine->kernel_filename, 739 kernel_base, 740 machine->ram_size - kernel_base); 741 if (kernel_size < 0) { 742 error_report("could not load kernel '%s'", 743 machine->kernel_filename); 744 exit(1); 745 } 746 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 747 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 748 /* load initrd */ 749 if (machine->initrd_filename) { 750 initrd_base = INITRD_LOAD_ADDR; 751 initrd_size = load_image_targphys(machine->initrd_filename, 752 initrd_base, 753 machine->ram_size - initrd_base); 754 if (initrd_size < 0) { 755 error_report("could not load initial ram disk '%s'", 756 machine->initrd_filename); 757 exit(1); 758 } 759 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 760 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 761 } 762 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 763 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 764 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 765 machine->kernel_cmdline); 766 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 767 machine->kernel_cmdline); 768 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 769 strlen(machine->kernel_cmdline) + 1); 770 } 771 boot_device = 'm'; 772 } else { 773 boot_device = machine->boot_order[0]; 774 } 775 776 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 777 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 778 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 779 780 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 781 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 782 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 783 784 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 785 if (kvm_enabled()) { 786 uint8_t *hypercall; 787 788 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 789 hypercall = g_malloc(16); 790 kvmppc_get_hypercall(env, hypercall, 16); 791 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 792 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 793 } else { 794 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 795 } 796 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 797 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 798 799 /* Prepare firmware configuration for Open Hack'Ware */ 800 if (m48t59) { 801 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 802 boot_device, 803 kernel_base, kernel_size, 804 machine->kernel_cmdline, 805 initrd_base, initrd_size, 806 /* XXX: need an option to load a NVRAM image */ 807 0, 808 graphic_width, graphic_height, graphic_depth); 809 } 810 } 811 812 static void ibm_40p_machine_init(MachineClass *mc) 813 { 814 mc->desc = "IBM RS/6000 7020 (40p)", 815 mc->init = ibm_40p_init; 816 mc->max_cpus = 1; 817 mc->default_ram_size = 128 * MiB; 818 mc->block_default_type = IF_SCSI; 819 mc->default_boot_order = "c"; 820 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); 821 mc->default_display = "std"; 822 } 823 824 DEFINE_MACHINE("40p", ibm_40p_machine_init) 825 DEFINE_MACHINE("prep", prep_machine_init) 826