1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/timer/m48t59.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/block/fdc.h" 29 #include "net/net.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/isa/isa.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/boards.h" 36 #include "qemu/log.h" 37 #include "hw/ide.h" 38 #include "hw/loader.h" 39 #include "hw/timer/mc146818rtc.h" 40 #include "hw/isa/pc87312.h" 41 #include "sysemu/block-backend.h" 42 #include "sysemu/arch_init.h" 43 #include "sysemu/qtest.h" 44 #include "exec/address-spaces.h" 45 #include "trace.h" 46 #include "elf.h" 47 48 /* SMP is not enabled, for now */ 49 #define MAX_CPUS 1 50 51 #define MAX_IDE_BUS 2 52 53 #define BIOS_SIZE (1024 * 1024) 54 #define BIOS_FILENAME "ppc_rom.bin" 55 #define KERNEL_LOAD_ADDR 0x01000000 56 #define INITRD_LOAD_ADDR 0x01800000 57 58 /* Constants for devices init */ 59 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 60 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 61 static const int ide_irq[2] = { 13, 13 }; 62 63 #define NE2000_NB_MAX 6 64 65 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 66 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 67 68 /* ISA IO ports bridge */ 69 #define PPC_IO_BASE 0x80000000 70 71 /* PowerPC control and status registers */ 72 #if 0 // Not used 73 static struct { 74 /* IDs */ 75 uint32_t veni_devi; 76 uint32_t revi; 77 /* Control and status */ 78 uint32_t gcsr; 79 uint32_t xcfr; 80 uint32_t ct32; 81 uint32_t mcsr; 82 /* General purpose registers */ 83 uint32_t gprg[6]; 84 /* Exceptions */ 85 uint32_t feen; 86 uint32_t fest; 87 uint32_t fema; 88 uint32_t fecl; 89 uint32_t eeen; 90 uint32_t eest; 91 uint32_t eecl; 92 uint32_t eeint; 93 uint32_t eemck0; 94 uint32_t eemck1; 95 /* Error diagnostic */ 96 } XCSR; 97 98 static void PPC_XCSR_writeb (void *opaque, 99 hwaddr addr, uint32_t value) 100 { 101 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 102 value); 103 } 104 105 static void PPC_XCSR_writew (void *opaque, 106 hwaddr addr, uint32_t value) 107 { 108 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 109 value); 110 } 111 112 static void PPC_XCSR_writel (void *opaque, 113 hwaddr addr, uint32_t value) 114 { 115 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 116 value); 117 } 118 119 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) 120 { 121 uint32_t retval = 0; 122 123 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 124 retval); 125 126 return retval; 127 } 128 129 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) 130 { 131 uint32_t retval = 0; 132 133 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 134 retval); 135 136 return retval; 137 } 138 139 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) 140 { 141 uint32_t retval = 0; 142 143 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 144 retval); 145 146 return retval; 147 } 148 149 static const MemoryRegionOps PPC_XCSR_ops = { 150 .old_mmio = { 151 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, 152 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, 153 }, 154 .endianness = DEVICE_LITTLE_ENDIAN, 155 }; 156 157 #endif 158 159 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 160 typedef struct sysctrl_t { 161 qemu_irq reset_irq; 162 Nvram *nvram; 163 uint8_t state; 164 uint8_t syscontrol; 165 int contiguous_map; 166 qemu_irq contiguous_map_irq; 167 int endian; 168 } sysctrl_t; 169 170 enum { 171 STATE_HARDFILE = 0x01, 172 }; 173 174 static sysctrl_t *sysctrl; 175 176 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 177 { 178 sysctrl_t *sysctrl = opaque; 179 180 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 181 switch (addr) { 182 case 0x0092: 183 /* Special port 92 */ 184 /* Check soft reset asked */ 185 if (val & 0x01) { 186 qemu_irq_raise(sysctrl->reset_irq); 187 } else { 188 qemu_irq_lower(sysctrl->reset_irq); 189 } 190 /* Check LE mode */ 191 if (val & 0x02) { 192 sysctrl->endian = 1; 193 } else { 194 sysctrl->endian = 0; 195 } 196 break; 197 case 0x0800: 198 /* Motorola CPU configuration register : read-only */ 199 break; 200 case 0x0802: 201 /* Motorola base module feature register : read-only */ 202 break; 203 case 0x0803: 204 /* Motorola base module status register : read-only */ 205 break; 206 case 0x0808: 207 /* Hardfile light register */ 208 if (val & 1) 209 sysctrl->state |= STATE_HARDFILE; 210 else 211 sysctrl->state &= ~STATE_HARDFILE; 212 break; 213 case 0x0810: 214 /* Password protect 1 register */ 215 if (sysctrl->nvram != NULL) { 216 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 217 (k->toggle_lock)(sysctrl->nvram, 1); 218 } 219 break; 220 case 0x0812: 221 /* Password protect 2 register */ 222 if (sysctrl->nvram != NULL) { 223 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 224 (k->toggle_lock)(sysctrl->nvram, 2); 225 } 226 break; 227 case 0x0814: 228 /* L2 invalidate register */ 229 // tlb_flush(first_cpu, 1); 230 break; 231 case 0x081C: 232 /* system control register */ 233 sysctrl->syscontrol = val & 0x0F; 234 break; 235 case 0x0850: 236 /* I/O map type register */ 237 sysctrl->contiguous_map = val & 0x01; 238 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 239 break; 240 default: 241 printf("ERROR: unaffected IO port write: %04" PRIx32 242 " => %02" PRIx32"\n", addr, val); 243 break; 244 } 245 } 246 247 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 248 { 249 sysctrl_t *sysctrl = opaque; 250 uint32_t retval = 0xFF; 251 252 switch (addr) { 253 case 0x0092: 254 /* Special port 92 */ 255 retval = sysctrl->endian << 1; 256 break; 257 case 0x0800: 258 /* Motorola CPU configuration register */ 259 retval = 0xEF; /* MPC750 */ 260 break; 261 case 0x0802: 262 /* Motorola Base module feature register */ 263 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 264 break; 265 case 0x0803: 266 /* Motorola base module status register */ 267 retval = 0xE0; /* Standard MPC750 */ 268 break; 269 case 0x080C: 270 /* Equipment present register: 271 * no L2 cache 272 * no upgrade processor 273 * no cards in PCI slots 274 * SCSI fuse is bad 275 */ 276 retval = 0x3C; 277 break; 278 case 0x0810: 279 /* Motorola base module extended feature register */ 280 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 281 break; 282 case 0x0814: 283 /* L2 invalidate: don't care */ 284 break; 285 case 0x0818: 286 /* Keylock */ 287 retval = 0x00; 288 break; 289 case 0x081C: 290 /* system control register 291 * 7 - 6 / 1 - 0: L2 cache enable 292 */ 293 retval = sysctrl->syscontrol; 294 break; 295 case 0x0823: 296 /* */ 297 retval = 0x03; /* no L2 cache */ 298 break; 299 case 0x0850: 300 /* I/O map type register */ 301 retval = sysctrl->contiguous_map; 302 break; 303 default: 304 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 305 break; 306 } 307 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 308 309 return retval; 310 } 311 312 313 #define NVRAM_SIZE 0x2000 314 315 static void ppc_prep_reset(void *opaque) 316 { 317 PowerPCCPU *cpu = opaque; 318 319 cpu_reset(CPU(cpu)); 320 } 321 322 static const MemoryRegionPortio prep_portio_list[] = { 323 /* System control ports */ 324 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 325 { 0x0800, 0x52, 1, 326 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 327 /* Special port to get debug messages from Open-Firmware */ 328 { 0x0F00, 4, 1, .write = PPC_debug_write, }, 329 PORTIO_END_OF_LIST(), 330 }; 331 332 static PortioList prep_port_list; 333 334 /*****************************************************************************/ 335 /* NVRAM helpers */ 336 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 337 { 338 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 339 return (k->read)(nvram, addr); 340 } 341 342 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 343 { 344 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 345 (k->write)(nvram, addr, val); 346 } 347 348 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 349 { 350 nvram_write(nvram, addr, value); 351 } 352 353 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 354 { 355 return nvram_read(nvram, addr); 356 } 357 358 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 359 { 360 nvram_write(nvram, addr, value >> 8); 361 nvram_write(nvram, addr + 1, value & 0xFF); 362 } 363 364 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 365 { 366 uint16_t tmp; 367 368 tmp = nvram_read(nvram, addr) << 8; 369 tmp |= nvram_read(nvram, addr + 1); 370 371 return tmp; 372 } 373 374 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 375 { 376 nvram_write(nvram, addr, value >> 24); 377 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 378 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 379 nvram_write(nvram, addr + 3, value & 0xFF); 380 } 381 382 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 383 uint32_t max) 384 { 385 int i; 386 387 for (i = 0; i < max && str[i] != '\0'; i++) { 388 nvram_write(nvram, addr + i, str[i]); 389 } 390 nvram_write(nvram, addr + i, str[i]); 391 nvram_write(nvram, addr + max - 1, '\0'); 392 } 393 394 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 395 { 396 uint16_t tmp; 397 uint16_t pd, pd1, pd2; 398 399 tmp = prev >> 8; 400 pd = prev ^ value; 401 pd1 = pd & 0x000F; 402 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 403 tmp ^= (pd1 << 3) | (pd1 << 8); 404 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 405 406 return tmp; 407 } 408 409 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 410 { 411 uint32_t i; 412 uint16_t crc = 0xFFFF; 413 int odd; 414 415 odd = count & 1; 416 count &= ~1; 417 for (i = 0; i != count; i++) { 418 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 419 } 420 if (odd) { 421 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 422 } 423 424 return crc; 425 } 426 427 #define CMDLINE_ADDR 0x017ff000 428 429 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 430 const char *arch, 431 uint32_t RAM_size, int boot_device, 432 uint32_t kernel_image, uint32_t kernel_size, 433 const char *cmdline, 434 uint32_t initrd_image, uint32_t initrd_size, 435 uint32_t NVRAM_image, 436 int width, int height, int depth) 437 { 438 uint16_t crc; 439 440 /* Set parameters for Open Hack'Ware BIOS */ 441 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 442 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 443 NVRAM_set_word(nvram, 0x14, NVRAM_size); 444 NVRAM_set_string(nvram, 0x20, arch, 16); 445 NVRAM_set_lword(nvram, 0x30, RAM_size); 446 NVRAM_set_byte(nvram, 0x34, boot_device); 447 NVRAM_set_lword(nvram, 0x38, kernel_image); 448 NVRAM_set_lword(nvram, 0x3C, kernel_size); 449 if (cmdline) { 450 /* XXX: put the cmdline in NVRAM too ? */ 451 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 452 cmdline); 453 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 454 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 455 } else { 456 NVRAM_set_lword(nvram, 0x40, 0); 457 NVRAM_set_lword(nvram, 0x44, 0); 458 } 459 NVRAM_set_lword(nvram, 0x48, initrd_image); 460 NVRAM_set_lword(nvram, 0x4C, initrd_size); 461 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 462 463 NVRAM_set_word(nvram, 0x54, width); 464 NVRAM_set_word(nvram, 0x56, height); 465 NVRAM_set_word(nvram, 0x58, depth); 466 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 467 NVRAM_set_word(nvram, 0xFC, crc); 468 469 return 0; 470 } 471 472 /* PowerPC PREP hardware initialisation */ 473 static void ppc_prep_init(MachineState *machine) 474 { 475 ram_addr_t ram_size = machine->ram_size; 476 const char *kernel_filename = machine->kernel_filename; 477 const char *kernel_cmdline = machine->kernel_cmdline; 478 const char *initrd_filename = machine->initrd_filename; 479 const char *boot_device = machine->boot_order; 480 MemoryRegion *sysmem = get_system_memory(); 481 PowerPCCPU *cpu = NULL; 482 CPUPPCState *env = NULL; 483 Nvram *m48t59; 484 #if 0 485 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 486 #endif 487 int linux_boot, i, nb_nics1; 488 MemoryRegion *ram = g_new(MemoryRegion, 1); 489 uint32_t kernel_base, initrd_base; 490 long kernel_size, initrd_size; 491 DeviceState *dev; 492 PCIHostState *pcihost; 493 PCIBus *pci_bus; 494 PCIDevice *pci; 495 ISABus *isa_bus; 496 ISADevice *isa; 497 int ppc_boot_device; 498 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 499 500 sysctrl = g_malloc0(sizeof(sysctrl_t)); 501 502 linux_boot = (kernel_filename != NULL); 503 504 /* init CPUs */ 505 if (machine->cpu_model == NULL) 506 machine->cpu_model = "602"; 507 for (i = 0; i < smp_cpus; i++) { 508 cpu = cpu_ppc_init(machine->cpu_model); 509 if (cpu == NULL) { 510 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 511 exit(1); 512 } 513 env = &cpu->env; 514 515 if (env->flags & POWERPC_FLAG_RTC_CLK) { 516 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 517 cpu_ppc_tb_init(env, 7812500UL); 518 } else { 519 /* Set time-base frequency to 100 Mhz */ 520 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 521 } 522 qemu_register_reset(ppc_prep_reset, cpu); 523 } 524 525 /* allocate RAM */ 526 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 527 memory_region_add_subregion(sysmem, 0, ram); 528 529 if (linux_boot) { 530 kernel_base = KERNEL_LOAD_ADDR; 531 /* now we can load the kernel */ 532 kernel_size = load_image_targphys(kernel_filename, kernel_base, 533 ram_size - kernel_base); 534 if (kernel_size < 0) { 535 hw_error("qemu: could not load kernel '%s'\n", kernel_filename); 536 exit(1); 537 } 538 /* load initrd */ 539 if (initrd_filename) { 540 initrd_base = INITRD_LOAD_ADDR; 541 initrd_size = load_image_targphys(initrd_filename, initrd_base, 542 ram_size - initrd_base); 543 if (initrd_size < 0) { 544 hw_error("qemu: could not load initial ram disk '%s'\n", 545 initrd_filename); 546 } 547 } else { 548 initrd_base = 0; 549 initrd_size = 0; 550 } 551 ppc_boot_device = 'm'; 552 } else { 553 kernel_base = 0; 554 kernel_size = 0; 555 initrd_base = 0; 556 initrd_size = 0; 557 ppc_boot_device = '\0'; 558 /* For now, OHW cannot boot from the network. */ 559 for (i = 0; boot_device[i] != '\0'; i++) { 560 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 561 ppc_boot_device = boot_device[i]; 562 break; 563 } 564 } 565 if (ppc_boot_device == '\0') { 566 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 567 exit(1); 568 } 569 } 570 571 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 572 hw_error("Only 6xx bus is supported on PREP machine\n"); 573 } 574 575 dev = qdev_create(NULL, "raven-pcihost"); 576 if (bios_name == NULL) { 577 bios_name = BIOS_FILENAME; 578 } 579 qdev_prop_set_string(dev, "bios-name", bios_name); 580 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 581 pcihost = PCI_HOST_BRIDGE(dev); 582 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 583 qdev_init_nofail(dev); 584 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 585 if (pci_bus == NULL) { 586 fprintf(stderr, "Couldn't create PCI host controller.\n"); 587 exit(1); 588 } 589 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 590 591 /* PCI -> ISA bridge */ 592 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 593 cpu = POWERPC_CPU(first_cpu); 594 qdev_connect_gpio_out(&pci->qdev, 0, 595 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 596 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 597 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 598 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 599 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 600 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 601 602 /* Super I/O (parallel + serial ports) */ 603 isa = isa_create(isa_bus, TYPE_PC87312); 604 dev = DEVICE(isa); 605 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 606 qdev_init_nofail(dev); 607 608 /* init basic PC hardware */ 609 pci_vga_init(pci_bus); 610 611 nb_nics1 = nb_nics; 612 if (nb_nics1 > NE2000_NB_MAX) 613 nb_nics1 = NE2000_NB_MAX; 614 for(i = 0; i < nb_nics1; i++) { 615 if (nd_table[i].model == NULL) { 616 nd_table[i].model = g_strdup("ne2k_isa"); 617 } 618 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 619 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 620 &nd_table[i]); 621 } else { 622 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 623 } 624 } 625 626 ide_drive_get(hd, ARRAY_SIZE(hd)); 627 for(i = 0; i < MAX_IDE_BUS; i++) { 628 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 629 hd[2 * i], 630 hd[2 * i + 1]); 631 } 632 isa_create_simple(isa_bus, "i8042"); 633 634 cpu = POWERPC_CPU(first_cpu); 635 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 636 637 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 638 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 639 640 /* PowerPC control and status register group */ 641 #if 0 642 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); 643 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); 644 #endif 645 646 if (usb_enabled()) { 647 pci_create_simple(pci_bus, -1, "pci-ohci"); 648 } 649 650 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 651 if (m48t59 == NULL) 652 return; 653 sysctrl->nvram = m48t59; 654 655 /* Initialise NVRAM */ 656 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 657 ppc_boot_device, 658 kernel_base, kernel_size, 659 kernel_cmdline, 660 initrd_base, initrd_size, 661 /* XXX: need an option to load a NVRAM image */ 662 0, 663 graphic_width, graphic_height, graphic_depth); 664 } 665 666 static void prep_machine_init(MachineClass *mc) 667 { 668 mc->desc = "PowerPC PREP platform"; 669 mc->init = ppc_prep_init; 670 mc->max_cpus = MAX_CPUS; 671 mc->default_boot_order = "cad"; 672 } 673 674 DEFINE_MACHINE("prep", prep_machine_init) 675