1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/timer/m48t59.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/block/fdc.h" 29 #include "net/net.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/isa/isa.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_host.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/boards.h" 36 #include "qemu/log.h" 37 #include "hw/ide.h" 38 #include "hw/loader.h" 39 #include "hw/timer/mc146818rtc.h" 40 #include "hw/isa/pc87312.h" 41 #include "sysemu/blockdev.h" 42 #include "sysemu/arch_init.h" 43 #include "exec/address-spaces.h" 44 45 //#define HARD_DEBUG_PPC_IO 46 //#define DEBUG_PPC_IO 47 48 /* SMP is not enabled, for now */ 49 #define MAX_CPUS 1 50 51 #define MAX_IDE_BUS 2 52 53 #define BIOS_SIZE (1024 * 1024) 54 #define BIOS_FILENAME "ppc_rom.bin" 55 #define KERNEL_LOAD_ADDR 0x01000000 56 #define INITRD_LOAD_ADDR 0x01800000 57 58 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) 59 #define DEBUG_PPC_IO 60 #endif 61 62 #if defined (HARD_DEBUG_PPC_IO) 63 #define PPC_IO_DPRINTF(fmt, ...) \ 64 do { \ 65 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ 66 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ 67 } else { \ 68 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ 69 } \ 70 } while (0) 71 #elif defined (DEBUG_PPC_IO) 72 #define PPC_IO_DPRINTF(fmt, ...) \ 73 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) 74 #else 75 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) 76 #endif 77 78 /* Constants for devices init */ 79 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 80 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 81 static const int ide_irq[2] = { 13, 13 }; 82 83 #define NE2000_NB_MAX 6 84 85 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 86 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 87 88 /* ISA IO ports bridge */ 89 #define PPC_IO_BASE 0x80000000 90 91 /* PowerPC control and status registers */ 92 #if 0 // Not used 93 static struct { 94 /* IDs */ 95 uint32_t veni_devi; 96 uint32_t revi; 97 /* Control and status */ 98 uint32_t gcsr; 99 uint32_t xcfr; 100 uint32_t ct32; 101 uint32_t mcsr; 102 /* General purpose registers */ 103 uint32_t gprg[6]; 104 /* Exceptions */ 105 uint32_t feen; 106 uint32_t fest; 107 uint32_t fema; 108 uint32_t fecl; 109 uint32_t eeen; 110 uint32_t eest; 111 uint32_t eecl; 112 uint32_t eeint; 113 uint32_t eemck0; 114 uint32_t eemck1; 115 /* Error diagnostic */ 116 } XCSR; 117 118 static void PPC_XCSR_writeb (void *opaque, 119 hwaddr addr, uint32_t value) 120 { 121 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 122 value); 123 } 124 125 static void PPC_XCSR_writew (void *opaque, 126 hwaddr addr, uint32_t value) 127 { 128 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 129 value); 130 } 131 132 static void PPC_XCSR_writel (void *opaque, 133 hwaddr addr, uint32_t value) 134 { 135 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 136 value); 137 } 138 139 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) 140 { 141 uint32_t retval = 0; 142 143 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 144 retval); 145 146 return retval; 147 } 148 149 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) 150 { 151 uint32_t retval = 0; 152 153 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 154 retval); 155 156 return retval; 157 } 158 159 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) 160 { 161 uint32_t retval = 0; 162 163 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 164 retval); 165 166 return retval; 167 } 168 169 static const MemoryRegionOps PPC_XCSR_ops = { 170 .old_mmio = { 171 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, 172 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, 173 }, 174 .endianness = DEVICE_LITTLE_ENDIAN, 175 }; 176 177 #endif 178 179 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 180 typedef struct sysctrl_t { 181 qemu_irq reset_irq; 182 M48t59State *nvram; 183 uint8_t state; 184 uint8_t syscontrol; 185 int contiguous_map; 186 int endian; 187 } sysctrl_t; 188 189 enum { 190 STATE_HARDFILE = 0x01, 191 }; 192 193 static sysctrl_t *sysctrl; 194 195 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 196 { 197 sysctrl_t *sysctrl = opaque; 198 199 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", 200 addr - PPC_IO_BASE, val); 201 switch (addr) { 202 case 0x0092: 203 /* Special port 92 */ 204 /* Check soft reset asked */ 205 if (val & 0x01) { 206 qemu_irq_raise(sysctrl->reset_irq); 207 } else { 208 qemu_irq_lower(sysctrl->reset_irq); 209 } 210 /* Check LE mode */ 211 if (val & 0x02) { 212 sysctrl->endian = 1; 213 } else { 214 sysctrl->endian = 0; 215 } 216 break; 217 case 0x0800: 218 /* Motorola CPU configuration register : read-only */ 219 break; 220 case 0x0802: 221 /* Motorola base module feature register : read-only */ 222 break; 223 case 0x0803: 224 /* Motorola base module status register : read-only */ 225 break; 226 case 0x0808: 227 /* Hardfile light register */ 228 if (val & 1) 229 sysctrl->state |= STATE_HARDFILE; 230 else 231 sysctrl->state &= ~STATE_HARDFILE; 232 break; 233 case 0x0810: 234 /* Password protect 1 register */ 235 if (sysctrl->nvram != NULL) 236 m48t59_toggle_lock(sysctrl->nvram, 1); 237 break; 238 case 0x0812: 239 /* Password protect 2 register */ 240 if (sysctrl->nvram != NULL) 241 m48t59_toggle_lock(sysctrl->nvram, 2); 242 break; 243 case 0x0814: 244 /* L2 invalidate register */ 245 // tlb_flush(first_cpu, 1); 246 break; 247 case 0x081C: 248 /* system control register */ 249 sysctrl->syscontrol = val & 0x0F; 250 break; 251 case 0x0850: 252 /* I/O map type register */ 253 sysctrl->contiguous_map = val & 0x01; 254 break; 255 default: 256 printf("ERROR: unaffected IO port write: %04" PRIx32 257 " => %02" PRIx32"\n", addr, val); 258 break; 259 } 260 } 261 262 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 263 { 264 sysctrl_t *sysctrl = opaque; 265 uint32_t retval = 0xFF; 266 267 switch (addr) { 268 case 0x0092: 269 /* Special port 92 */ 270 retval = 0x00; 271 break; 272 case 0x0800: 273 /* Motorola CPU configuration register */ 274 retval = 0xEF; /* MPC750 */ 275 break; 276 case 0x0802: 277 /* Motorola Base module feature register */ 278 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 279 break; 280 case 0x0803: 281 /* Motorola base module status register */ 282 retval = 0xE0; /* Standard MPC750 */ 283 break; 284 case 0x080C: 285 /* Equipment present register: 286 * no L2 cache 287 * no upgrade processor 288 * no cards in PCI slots 289 * SCSI fuse is bad 290 */ 291 retval = 0x3C; 292 break; 293 case 0x0810: 294 /* Motorola base module extended feature register */ 295 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 296 break; 297 case 0x0814: 298 /* L2 invalidate: don't care */ 299 break; 300 case 0x0818: 301 /* Keylock */ 302 retval = 0x00; 303 break; 304 case 0x081C: 305 /* system control register 306 * 7 - 6 / 1 - 0: L2 cache enable 307 */ 308 retval = sysctrl->syscontrol; 309 break; 310 case 0x0823: 311 /* */ 312 retval = 0x03; /* no L2 cache */ 313 break; 314 case 0x0850: 315 /* I/O map type register */ 316 retval = sysctrl->contiguous_map; 317 break; 318 default: 319 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 320 break; 321 } 322 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", 323 addr - PPC_IO_BASE, retval); 324 325 return retval; 326 } 327 328 static inline hwaddr prep_IO_address(sysctrl_t *sysctrl, 329 hwaddr addr) 330 { 331 if (sysctrl->contiguous_map == 0) { 332 /* 64 KB contiguous space for IOs */ 333 addr &= 0xFFFF; 334 } else { 335 /* 8 MB non-contiguous space for IOs */ 336 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); 337 } 338 339 return addr; 340 } 341 342 static void PPC_prep_io_writeb (void *opaque, hwaddr addr, 343 uint32_t value) 344 { 345 sysctrl_t *sysctrl = opaque; 346 347 addr = prep_IO_address(sysctrl, addr); 348 cpu_outb(addr, value); 349 } 350 351 static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr) 352 { 353 sysctrl_t *sysctrl = opaque; 354 uint32_t ret; 355 356 addr = prep_IO_address(sysctrl, addr); 357 ret = cpu_inb(addr); 358 359 return ret; 360 } 361 362 static void PPC_prep_io_writew (void *opaque, hwaddr addr, 363 uint32_t value) 364 { 365 sysctrl_t *sysctrl = opaque; 366 367 addr = prep_IO_address(sysctrl, addr); 368 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); 369 cpu_outw(addr, value); 370 } 371 372 static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr) 373 { 374 sysctrl_t *sysctrl = opaque; 375 uint32_t ret; 376 377 addr = prep_IO_address(sysctrl, addr); 378 ret = cpu_inw(addr); 379 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); 380 381 return ret; 382 } 383 384 static void PPC_prep_io_writel (void *opaque, hwaddr addr, 385 uint32_t value) 386 { 387 sysctrl_t *sysctrl = opaque; 388 389 addr = prep_IO_address(sysctrl, addr); 390 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); 391 cpu_outl(addr, value); 392 } 393 394 static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr) 395 { 396 sysctrl_t *sysctrl = opaque; 397 uint32_t ret; 398 399 addr = prep_IO_address(sysctrl, addr); 400 ret = cpu_inl(addr); 401 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); 402 403 return ret; 404 } 405 406 static const MemoryRegionOps PPC_prep_io_ops = { 407 .old_mmio = { 408 .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, 409 .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, 410 }, 411 .endianness = DEVICE_LITTLE_ENDIAN, 412 }; 413 414 #define NVRAM_SIZE 0x2000 415 416 static void cpu_request_exit(void *opaque, int irq, int level) 417 { 418 CPUPPCState *env = cpu_single_env; 419 420 if (env && level) { 421 cpu_exit(env); 422 } 423 } 424 425 static void ppc_prep_reset(void *opaque) 426 { 427 PowerPCCPU *cpu = opaque; 428 429 cpu_reset(CPU(cpu)); 430 } 431 432 /* PowerPC PREP hardware initialisation */ 433 static void ppc_prep_init(QEMUMachineInitArgs *args) 434 { 435 ram_addr_t ram_size = args->ram_size; 436 const char *cpu_model = args->cpu_model; 437 const char *kernel_filename = args->kernel_filename; 438 const char *kernel_cmdline = args->kernel_cmdline; 439 const char *initrd_filename = args->initrd_filename; 440 const char *boot_device = args->boot_device; 441 MemoryRegion *sysmem = get_system_memory(); 442 PowerPCCPU *cpu = NULL; 443 CPUPPCState *env = NULL; 444 char *filename; 445 nvram_t nvram; 446 M48t59State *m48t59; 447 MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); 448 #if 0 449 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 450 #endif 451 int linux_boot, i, nb_nics1, bios_size; 452 MemoryRegion *ram = g_new(MemoryRegion, 1); 453 MemoryRegion *bios = g_new(MemoryRegion, 1); 454 uint32_t kernel_base, initrd_base; 455 long kernel_size, initrd_size; 456 DeviceState *dev; 457 PCIHostState *pcihost; 458 PCIBus *pci_bus; 459 PCIDevice *pci; 460 ISABus *isa_bus; 461 ISADevice *isa; 462 qemu_irq *cpu_exit_irq; 463 int ppc_boot_device; 464 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 465 466 sysctrl = g_malloc0(sizeof(sysctrl_t)); 467 468 linux_boot = (kernel_filename != NULL); 469 470 /* init CPUs */ 471 if (cpu_model == NULL) 472 cpu_model = "602"; 473 for (i = 0; i < smp_cpus; i++) { 474 cpu = cpu_ppc_init(cpu_model); 475 if (cpu == NULL) { 476 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 477 exit(1); 478 } 479 env = &cpu->env; 480 481 if (env->flags & POWERPC_FLAG_RTC_CLK) { 482 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 483 cpu_ppc_tb_init(env, 7812500UL); 484 } else { 485 /* Set time-base frequency to 100 Mhz */ 486 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 487 } 488 qemu_register_reset(ppc_prep_reset, cpu); 489 } 490 491 /* allocate RAM */ 492 memory_region_init_ram(ram, "ppc_prep.ram", ram_size); 493 vmstate_register_ram_global(ram); 494 memory_region_add_subregion(sysmem, 0, ram); 495 496 /* allocate and load BIOS */ 497 memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE); 498 memory_region_set_readonly(bios, true); 499 memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios); 500 vmstate_register_ram_global(bios); 501 if (bios_name == NULL) 502 bios_name = BIOS_FILENAME; 503 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 504 if (filename) { 505 bios_size = get_image_size(filename); 506 } else { 507 bios_size = -1; 508 } 509 if (bios_size > 0 && bios_size <= BIOS_SIZE) { 510 hwaddr bios_addr; 511 bios_size = (bios_size + 0xfff) & ~0xfff; 512 bios_addr = (uint32_t)(-bios_size); 513 bios_size = load_image_targphys(filename, bios_addr, bios_size); 514 } 515 if (bios_size < 0 || bios_size > BIOS_SIZE) { 516 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); 517 } 518 if (filename) { 519 g_free(filename); 520 } 521 522 if (linux_boot) { 523 kernel_base = KERNEL_LOAD_ADDR; 524 /* now we can load the kernel */ 525 kernel_size = load_image_targphys(kernel_filename, kernel_base, 526 ram_size - kernel_base); 527 if (kernel_size < 0) { 528 hw_error("qemu: could not load kernel '%s'\n", kernel_filename); 529 exit(1); 530 } 531 /* load initrd */ 532 if (initrd_filename) { 533 initrd_base = INITRD_LOAD_ADDR; 534 initrd_size = load_image_targphys(initrd_filename, initrd_base, 535 ram_size - initrd_base); 536 if (initrd_size < 0) { 537 hw_error("qemu: could not load initial ram disk '%s'\n", 538 initrd_filename); 539 } 540 } else { 541 initrd_base = 0; 542 initrd_size = 0; 543 } 544 ppc_boot_device = 'm'; 545 } else { 546 kernel_base = 0; 547 kernel_size = 0; 548 initrd_base = 0; 549 initrd_size = 0; 550 ppc_boot_device = '\0'; 551 /* For now, OHW cannot boot from the network. */ 552 for (i = 0; boot_device[i] != '\0'; i++) { 553 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 554 ppc_boot_device = boot_device[i]; 555 break; 556 } 557 } 558 if (ppc_boot_device == '\0') { 559 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 560 exit(1); 561 } 562 } 563 564 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 565 hw_error("Only 6xx bus is supported on PREP machine\n"); 566 } 567 568 dev = qdev_create(NULL, "raven-pcihost"); 569 pcihost = PCI_HOST_BRIDGE(dev); 570 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 571 qdev_init_nofail(dev); 572 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 573 if (pci_bus == NULL) { 574 fprintf(stderr, "Couldn't create PCI host controller.\n"); 575 exit(1); 576 } 577 578 /* PCI -> ISA bridge */ 579 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 580 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 581 qdev_connect_gpio_out(&pci->qdev, 0, 582 first_cpu->irq_inputs[PPC6xx_INPUT_INT]); 583 qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq); 584 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 585 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 586 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 587 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 588 isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0")); 589 590 /* Super I/O (parallel + serial ports) */ 591 isa = isa_create(isa_bus, TYPE_PC87312); 592 qdev_prop_set_uint8(&isa->qdev, "config", 13); /* fdc, ser0, ser1, par0 */ 593 qdev_init_nofail(&isa->qdev); 594 595 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ 596 memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, 597 "ppc-io", 0x00800000); 598 memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); 599 600 /* init basic PC hardware */ 601 pci_vga_init(pci_bus); 602 603 nb_nics1 = nb_nics; 604 if (nb_nics1 > NE2000_NB_MAX) 605 nb_nics1 = NE2000_NB_MAX; 606 for(i = 0; i < nb_nics1; i++) { 607 if (nd_table[i].model == NULL) { 608 nd_table[i].model = g_strdup("ne2k_isa"); 609 } 610 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 611 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 612 &nd_table[i]); 613 } else { 614 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); 615 } 616 } 617 618 ide_drive_get(hd, MAX_IDE_BUS); 619 for(i = 0; i < MAX_IDE_BUS; i++) { 620 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 621 hd[2 * i], 622 hd[2 * i + 1]); 623 } 624 isa_create_simple(isa_bus, "i8042"); 625 626 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; 627 /* System control ports */ 628 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); 629 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); 630 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); 631 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); 632 /* PowerPC control and status register group */ 633 #if 0 634 memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); 635 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); 636 #endif 637 638 if (usb_enabled(false)) { 639 pci_create_simple(pci_bus, -1, "pci-ohci"); 640 } 641 642 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); 643 if (m48t59 == NULL) 644 return; 645 sysctrl->nvram = m48t59; 646 647 /* Initialise NVRAM */ 648 nvram.opaque = m48t59; 649 nvram.read_fn = &m48t59_read; 650 nvram.write_fn = &m48t59_write; 651 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, 652 kernel_base, kernel_size, 653 kernel_cmdline, 654 initrd_base, initrd_size, 655 /* XXX: need an option to load a NVRAM image */ 656 0, 657 graphic_width, graphic_height, graphic_depth); 658 659 /* Special port to get debug messages from Open-Firmware */ 660 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); 661 662 /* Initialize audio subsystem */ 663 audio_init(isa_bus, pci_bus); 664 } 665 666 static QEMUMachine prep_machine = { 667 .name = "prep", 668 .desc = "PowerPC PREP platform", 669 .init = ppc_prep_init, 670 .max_cpus = MAX_CPUS, 671 DEFAULT_MACHINE_OPTIONS, 672 }; 673 674 static void prep_machine_init(void) 675 { 676 qemu_register_machine(&prep_machine); 677 } 678 679 machine_init(prep_machine_init); 680