1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "hw/rtc/m48t59.h" 29 #include "hw/char/serial.h" 30 #include "hw/block/fdc.h" 31 #include "net/net.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/isa/isa.h" 34 #include "hw/pci/pci.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/boards.h" 38 #include "qapi/error.h" 39 #include "qemu/error-report.h" 40 #include "qemu/log.h" 41 #include "hw/loader.h" 42 #include "hw/rtc/mc146818rtc.h" 43 #include "hw/isa/pc87312.h" 44 #include "hw/qdev-properties.h" 45 #include "sysemu/arch_init.h" 46 #include "sysemu/kvm.h" 47 #include "sysemu/reset.h" 48 #include "exec/address-spaces.h" 49 #include "trace.h" 50 #include "elf.h" 51 #include "qemu/units.h" 52 #include "kvm_ppc.h" 53 54 /* SMP is not enabled, for now */ 55 #define MAX_CPUS 1 56 57 #define MAX_IDE_BUS 2 58 59 #define CFG_ADDR 0xf0000510 60 61 #define KERNEL_LOAD_ADDR 0x01000000 62 #define INITRD_LOAD_ADDR 0x01800000 63 64 #define NVRAM_SIZE 0x2000 65 66 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 67 Error **errp) 68 { 69 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 70 } 71 72 static void ppc_prep_reset(void *opaque) 73 { 74 PowerPCCPU *cpu = opaque; 75 76 cpu_reset(CPU(cpu)); 77 } 78 79 80 /*****************************************************************************/ 81 /* NVRAM helpers */ 82 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 83 { 84 NvramClass *k = NVRAM_GET_CLASS(nvram); 85 return (k->read)(nvram, addr); 86 } 87 88 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 89 { 90 NvramClass *k = NVRAM_GET_CLASS(nvram); 91 (k->write)(nvram, addr, val); 92 } 93 94 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 95 { 96 nvram_write(nvram, addr, value); 97 } 98 99 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 100 { 101 return nvram_read(nvram, addr); 102 } 103 104 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 105 { 106 nvram_write(nvram, addr, value >> 8); 107 nvram_write(nvram, addr + 1, value & 0xFF); 108 } 109 110 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 111 { 112 uint16_t tmp; 113 114 tmp = nvram_read(nvram, addr) << 8; 115 tmp |= nvram_read(nvram, addr + 1); 116 117 return tmp; 118 } 119 120 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 121 { 122 nvram_write(nvram, addr, value >> 24); 123 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 124 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 125 nvram_write(nvram, addr + 3, value & 0xFF); 126 } 127 128 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 129 uint32_t max) 130 { 131 int i; 132 133 for (i = 0; i < max && str[i] != '\0'; i++) { 134 nvram_write(nvram, addr + i, str[i]); 135 } 136 nvram_write(nvram, addr + i, str[i]); 137 nvram_write(nvram, addr + max - 1, '\0'); 138 } 139 140 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 141 { 142 uint16_t tmp; 143 uint16_t pd, pd1, pd2; 144 145 tmp = prev >> 8; 146 pd = prev ^ value; 147 pd1 = pd & 0x000F; 148 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 149 tmp ^= (pd1 << 3) | (pd1 << 8); 150 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 151 152 return tmp; 153 } 154 155 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 156 { 157 uint32_t i; 158 uint16_t crc = 0xFFFF; 159 int odd; 160 161 odd = count & 1; 162 count &= ~1; 163 for (i = 0; i != count; i++) { 164 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 165 } 166 if (odd) { 167 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 168 } 169 170 return crc; 171 } 172 173 #define CMDLINE_ADDR 0x017ff000 174 175 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 176 const char *arch, 177 uint32_t RAM_size, int boot_device, 178 uint32_t kernel_image, uint32_t kernel_size, 179 const char *cmdline, 180 uint32_t initrd_image, uint32_t initrd_size, 181 uint32_t NVRAM_image, 182 int width, int height, int depth) 183 { 184 uint16_t crc; 185 186 /* Set parameters for Open Hack'Ware BIOS */ 187 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 188 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 189 NVRAM_set_word(nvram, 0x14, NVRAM_size); 190 NVRAM_set_string(nvram, 0x20, arch, 16); 191 NVRAM_set_lword(nvram, 0x30, RAM_size); 192 NVRAM_set_byte(nvram, 0x34, boot_device); 193 NVRAM_set_lword(nvram, 0x38, kernel_image); 194 NVRAM_set_lword(nvram, 0x3C, kernel_size); 195 if (cmdline) { 196 /* XXX: put the cmdline in NVRAM too ? */ 197 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 198 cmdline); 199 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 200 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 201 } else { 202 NVRAM_set_lword(nvram, 0x40, 0); 203 NVRAM_set_lword(nvram, 0x44, 0); 204 } 205 NVRAM_set_lword(nvram, 0x48, initrd_image); 206 NVRAM_set_lword(nvram, 0x4C, initrd_size); 207 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 208 209 NVRAM_set_word(nvram, 0x54, width); 210 NVRAM_set_word(nvram, 0x56, height); 211 NVRAM_set_word(nvram, 0x58, depth); 212 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 213 NVRAM_set_word(nvram, 0xFC, crc); 214 215 return 0; 216 } 217 218 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 219 { 220 uint16_t checksum = *(uint16_t *)opaque; 221 ISADevice *rtc; 222 223 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 224 rtc = ISA_DEVICE(dev); 225 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 226 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 227 rtc_set_memory(rtc, 0x2f, checksum >> 8); 228 rtc_set_memory(rtc, 0x3f, checksum >> 8); 229 230 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), 231 "date"); 232 } 233 return 0; 234 } 235 236 static void ibm_40p_init(MachineState *machine) 237 { 238 const char *bios_name = machine->firmware ?: "openbios-ppc"; 239 CPUPPCState *env = NULL; 240 uint16_t cmos_checksum; 241 PowerPCCPU *cpu; 242 DeviceState *dev, *i82378_dev; 243 SysBusDevice *pcihost, *s; 244 Nvram *m48t59 = NULL; 245 PCIBus *pci_bus; 246 ISADevice *isa_dev; 247 ISABus *isa_bus; 248 void *fw_cfg; 249 int i; 250 uint32_t kernel_base = 0, initrd_base = 0; 251 long kernel_size = 0, initrd_size = 0; 252 char boot_device; 253 254 /* init CPU */ 255 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 256 env = &cpu->env; 257 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 258 error_report("only 6xx bus is supported on this machine"); 259 exit(1); 260 } 261 262 if (env->flags & POWERPC_FLAG_RTC_CLK) { 263 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 264 cpu_ppc_tb_init(env, 7812500UL); 265 } else { 266 /* Set time-base frequency to 100 Mhz */ 267 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 268 } 269 qemu_register_reset(ppc_prep_reset, cpu); 270 271 /* PCI host */ 272 dev = qdev_new("raven-pcihost"); 273 qdev_prop_set_string(dev, "bios-name", bios_name); 274 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 275 pcihost = SYS_BUS_DEVICE(dev); 276 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); 277 sysbus_realize_and_unref(pcihost, &error_fatal); 278 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 279 if (!pci_bus) { 280 error_report("could not create PCI host controller"); 281 exit(1); 282 } 283 284 /* PCI -> ISA bridge */ 285 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 286 qdev_connect_gpio_out(i82378_dev, 0, 287 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 288 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); 289 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); 290 291 /* Memory controller */ 292 isa_dev = isa_new("rs6000-mc"); 293 dev = DEVICE(isa_dev); 294 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 295 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 296 297 /* RTC */ 298 isa_dev = isa_new(TYPE_MC146818_RTC); 299 dev = DEVICE(isa_dev); 300 qdev_prop_set_int32(dev, "base_year", 1900); 301 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 302 303 /* initialize CMOS checksums */ 304 cmos_checksum = 0x6aa9; 305 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 306 &cmos_checksum); 307 308 /* add some more devices */ 309 if (defaults_enabled()) { 310 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 311 312 isa_dev = isa_new("cs4231a"); 313 dev = DEVICE(isa_dev); 314 qdev_prop_set_uint32(dev, "iobase", 0x830); 315 qdev_prop_set_uint32(dev, "irq", 10); 316 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 317 318 isa_dev = isa_new("pc87312"); 319 dev = DEVICE(isa_dev); 320 qdev_prop_set_uint32(dev, "config", 12); 321 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 322 323 isa_dev = isa_new("prep-systemio"); 324 dev = DEVICE(isa_dev); 325 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 326 qdev_prop_set_uint32(dev, "equipment", 0xc0); 327 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); 328 329 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), 330 "lsi53c810")); 331 lsi53c8xx_handle_legacy_cmdline(dev); 332 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); 333 334 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 335 pci_vga_init(pci_bus); 336 337 for (i = 0; i < nb_nics; i++) { 338 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 339 i == 0 ? "3" : NULL); 340 } 341 } 342 343 /* Prepare firmware configuration for OpenBIOS */ 344 dev = qdev_new(TYPE_FW_CFG_MEM); 345 fw_cfg = FW_CFG(dev); 346 qdev_prop_set_uint32(dev, "data_width", 1); 347 qdev_prop_set_bit(dev, "dma_enabled", false); 348 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 349 OBJECT(fw_cfg)); 350 s = SYS_BUS_DEVICE(dev); 351 sysbus_realize_and_unref(s, &error_fatal); 352 sysbus_mmio_map(s, 0, CFG_ADDR); 353 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 354 355 if (machine->kernel_filename) { 356 /* load kernel */ 357 kernel_base = KERNEL_LOAD_ADDR; 358 kernel_size = load_image_targphys(machine->kernel_filename, 359 kernel_base, 360 machine->ram_size - kernel_base); 361 if (kernel_size < 0) { 362 error_report("could not load kernel '%s'", 363 machine->kernel_filename); 364 exit(1); 365 } 366 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 367 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 368 /* load initrd */ 369 if (machine->initrd_filename) { 370 initrd_base = INITRD_LOAD_ADDR; 371 initrd_size = load_image_targphys(machine->initrd_filename, 372 initrd_base, 373 machine->ram_size - initrd_base); 374 if (initrd_size < 0) { 375 error_report("could not load initial ram disk '%s'", 376 machine->initrd_filename); 377 exit(1); 378 } 379 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 380 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 381 } 382 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 383 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 384 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 385 machine->kernel_cmdline); 386 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 387 machine->kernel_cmdline); 388 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 389 strlen(machine->kernel_cmdline) + 1); 390 } 391 boot_device = 'm'; 392 } else { 393 boot_device = machine->boot_order[0]; 394 } 395 396 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 397 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 398 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 399 400 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 401 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 402 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 403 404 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 405 if (kvm_enabled()) { 406 uint8_t *hypercall; 407 408 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 409 hypercall = g_malloc(16); 410 kvmppc_get_hypercall(env, hypercall, 16); 411 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 412 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 413 } else { 414 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 415 } 416 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 417 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 418 419 /* Prepare firmware configuration for Open Hack'Ware */ 420 if (m48t59) { 421 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size, 422 boot_device, 423 kernel_base, kernel_size, 424 machine->kernel_cmdline, 425 initrd_base, initrd_size, 426 /* XXX: need an option to load a NVRAM image */ 427 0, 428 graphic_width, graphic_height, graphic_depth); 429 } 430 } 431 432 static void ibm_40p_machine_init(MachineClass *mc) 433 { 434 mc->desc = "IBM RS/6000 7020 (40p)", 435 mc->init = ibm_40p_init; 436 mc->max_cpus = 1; 437 mc->default_ram_size = 128 * MiB; 438 mc->block_default_type = IF_SCSI; 439 mc->default_boot_order = "c"; 440 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); 441 mc->default_display = "std"; 442 } 443 444 DEFINE_MACHINE("40p", ibm_40p_machine_init) 445