1 /* 2 * QEMU PowerPC Booke hardware System Emulator 3 * 4 * Copyright (c) 2011 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu-common.h" 26 #include "cpu.h" 27 #include "hw/hw.h" 28 #include "hw/ppc/ppc.h" 29 #include "qemu/timer.h" 30 #include "sysemu/sysemu.h" 31 #include "hw/timer/m48t59.h" 32 #include "qemu/log.h" 33 #include "hw/loader.h" 34 #include "kvm_ppc.h" 35 36 37 /* Timer Control Register */ 38 39 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ 40 #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT) 41 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ 42 #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT) 43 #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */ 44 #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */ 45 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ 46 #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT) 47 #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */ 48 #define TCR_ARE (1U << 22) /* Auto-Reload Enable */ 49 50 /* Timer Control Register (e500 specific fields) */ 51 52 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ 53 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) 54 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ 55 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) 56 57 /* Timer Status Register */ 58 59 #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */ 60 #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */ 61 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ 62 #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT) 63 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ 64 #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */ 65 66 typedef struct booke_timer_t booke_timer_t; 67 struct booke_timer_t { 68 69 uint64_t fit_next; 70 QEMUTimer *fit_timer; 71 72 uint64_t wdt_next; 73 QEMUTimer *wdt_timer; 74 75 uint32_t flags; 76 }; 77 78 static void booke_update_irq(PowerPCCPU *cpu) 79 { 80 CPUPPCState *env = &cpu->env; 81 82 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 83 (env->spr[SPR_BOOKE_TSR] & TSR_DIS 84 && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); 85 86 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 87 (env->spr[SPR_BOOKE_TSR] & TSR_WIS 88 && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); 89 90 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 91 (env->spr[SPR_BOOKE_TSR] & TSR_FIS 92 && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); 93 } 94 95 /* Return the location of the bit of time base at which the FIT will raise an 96 interrupt */ 97 static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) 98 { 99 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; 100 101 if (tb_env->flags & PPC_TIMER_E500) { 102 /* e500 Fixed-interval timer period extension */ 103 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) 104 >> TCR_E500_FPEXT_SHIFT; 105 fp = 63 - (fp | fpext << 2); 106 } else { 107 fp = env->fit_period[fp]; 108 } 109 110 return fp; 111 } 112 113 /* Return the location of the bit of time base at which the WDT will raise an 114 interrupt */ 115 static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) 116 { 117 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; 118 119 if (tb_env->flags & PPC_TIMER_E500) { 120 /* e500 Watchdog timer period extension */ 121 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) 122 >> TCR_E500_WPEXT_SHIFT; 123 wp = 63 - (wp | wpext << 2); 124 } else { 125 wp = env->wdt_period[wp]; 126 } 127 128 return wp; 129 } 130 131 static void booke_update_fixed_timer(CPUPPCState *env, 132 uint8_t target_bit, 133 uint64_t *next, 134 QEMUTimer *timer, 135 int tsr_bit) 136 { 137 ppc_tb_t *tb_env = env->tb_env; 138 uint64_t delta_tick, ticks = 0; 139 uint64_t tb; 140 uint64_t period; 141 uint64_t now; 142 143 if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) { 144 /* 145 * Don't arm the timer again when the guest has the current 146 * interrupt still pending. Wait for it to ack it. 147 */ 148 return; 149 } 150 151 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 152 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); 153 period = 1ULL << target_bit; 154 delta_tick = period - (tb & (period - 1)); 155 156 /* the timer triggers only when the selected bit toggles from 0 to 1 */ 157 if (tb & period) { 158 ticks = period; 159 } 160 161 if (ticks + delta_tick < ticks) { 162 /* Overflow, so assume the biggest number we can express. */ 163 ticks = UINT64_MAX; 164 } else { 165 ticks += delta_tick; 166 } 167 168 *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 169 if ((*next < now) || (*next > INT64_MAX)) { 170 /* Overflow, so assume the biggest number the qemu timer supports. */ 171 *next = INT64_MAX; 172 } 173 174 /* XXX: If expire time is now. We can't run the callback because we don't 175 * have access to it. So we just set the timer one nanosecond later. 176 */ 177 178 if (*next == now) { 179 (*next)++; 180 } else { 181 /* 182 * There's no point to fake any granularity that's more fine grained 183 * than milliseconds. Anything beyond that just overloads the system. 184 */ 185 *next = MAX(*next, now + SCALE_MS); 186 } 187 188 /* Fire the next timer */ 189 timer_mod(timer, *next); 190 } 191 192 static void booke_decr_cb(void *opaque) 193 { 194 PowerPCCPU *cpu = opaque; 195 CPUPPCState *env = &cpu->env; 196 197 env->spr[SPR_BOOKE_TSR] |= TSR_DIS; 198 booke_update_irq(cpu); 199 200 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) { 201 /* Do not reload 0, it is already there. It would just trigger 202 * the timer again and lead to infinite loop */ 203 if (env->spr[SPR_BOOKE_DECAR] != 0) { 204 /* Auto Reload */ 205 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); 206 } 207 } 208 } 209 210 static void booke_fit_cb(void *opaque) 211 { 212 PowerPCCPU *cpu = opaque; 213 CPUPPCState *env = &cpu->env; 214 ppc_tb_t *tb_env; 215 booke_timer_t *booke_timer; 216 217 tb_env = env->tb_env; 218 booke_timer = tb_env->opaque; 219 env->spr[SPR_BOOKE_TSR] |= TSR_FIS; 220 221 booke_update_irq(cpu); 222 223 booke_update_fixed_timer(env, 224 booke_get_fit_target(env, tb_env), 225 &booke_timer->fit_next, 226 booke_timer->fit_timer, 227 TSR_FIS); 228 } 229 230 static void booke_wdt_cb(void *opaque) 231 { 232 PowerPCCPU *cpu = opaque; 233 CPUPPCState *env = &cpu->env; 234 ppc_tb_t *tb_env; 235 booke_timer_t *booke_timer; 236 237 tb_env = env->tb_env; 238 booke_timer = tb_env->opaque; 239 240 /* TODO: There's lots of complicated stuff to do here */ 241 242 booke_update_irq(cpu); 243 244 booke_update_fixed_timer(env, 245 booke_get_wdt_target(env, tb_env), 246 &booke_timer->wdt_next, 247 booke_timer->wdt_timer, 248 TSR_WIS); 249 } 250 251 void store_booke_tsr(CPUPPCState *env, target_ulong val) 252 { 253 PowerPCCPU *cpu = ppc_env_get_cpu(env); 254 ppc_tb_t *tb_env = env->tb_env; 255 booke_timer_t *booke_timer = tb_env->opaque; 256 257 env->spr[SPR_BOOKE_TSR] &= ~val; 258 kvmppc_clear_tsr_bits(cpu, val); 259 260 if (val & TSR_FIS) { 261 booke_update_fixed_timer(env, 262 booke_get_fit_target(env, tb_env), 263 &booke_timer->fit_next, 264 booke_timer->fit_timer, 265 TSR_FIS); 266 } 267 268 if (val & TSR_WIS) { 269 booke_update_fixed_timer(env, 270 booke_get_wdt_target(env, tb_env), 271 &booke_timer->wdt_next, 272 booke_timer->wdt_timer, 273 TSR_WIS); 274 } 275 276 booke_update_irq(cpu); 277 } 278 279 void store_booke_tcr(CPUPPCState *env, target_ulong val) 280 { 281 PowerPCCPU *cpu = ppc_env_get_cpu(env); 282 ppc_tb_t *tb_env = env->tb_env; 283 booke_timer_t *booke_timer = tb_env->opaque; 284 285 env->spr[SPR_BOOKE_TCR] = val; 286 kvmppc_set_tcr(cpu); 287 288 booke_update_irq(cpu); 289 290 booke_update_fixed_timer(env, 291 booke_get_fit_target(env, tb_env), 292 &booke_timer->fit_next, 293 booke_timer->fit_timer, 294 TSR_FIS); 295 296 booke_update_fixed_timer(env, 297 booke_get_wdt_target(env, tb_env), 298 &booke_timer->wdt_next, 299 booke_timer->wdt_timer, 300 TSR_WIS); 301 } 302 303 static void ppc_booke_timer_reset_handle(void *opaque) 304 { 305 PowerPCCPU *cpu = opaque; 306 CPUPPCState *env = &cpu->env; 307 308 store_booke_tcr(env, 0); 309 store_booke_tsr(env, -1); 310 } 311 312 /* 313 * This function will be called whenever the CPU state changes. 314 * CPU states are defined "typedef enum RunState". 315 * Regarding timer, When CPU state changes to running after debug halt 316 * or similar cases which takes time then in between final watchdog 317 * expiry happenes. This will cause exit to QEMU and configured watchdog 318 * action will be taken. To avoid this we always clear the watchdog state when 319 * state changes to running. 320 */ 321 static void cpu_state_change_handler(void *opaque, int running, RunState state) 322 { 323 PowerPCCPU *cpu = opaque; 324 CPUPPCState *env = &cpu->env; 325 326 if (!running) { 327 return; 328 } 329 330 /* 331 * Clear watchdog interrupt condition by clearing TSR. 332 */ 333 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); 334 } 335 336 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) 337 { 338 ppc_tb_t *tb_env; 339 booke_timer_t *booke_timer; 340 int ret = 0; 341 342 tb_env = g_malloc0(sizeof(ppc_tb_t)); 343 booke_timer = g_malloc0(sizeof(booke_timer_t)); 344 345 cpu->env.tb_env = tb_env; 346 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; 347 348 tb_env->tb_freq = freq; 349 tb_env->decr_freq = freq; 350 tb_env->opaque = booke_timer; 351 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu); 352 353 booke_timer->fit_timer = 354 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu); 355 booke_timer->wdt_timer = 356 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu); 357 358 ret = kvmppc_booke_watchdog_enable(cpu); 359 360 if (ret) { 361 /* TODO: Start the QEMU emulated watchdog if not running on KVM. 362 * Also start the QEMU emulated watchdog if KVM does not support 363 * emulated watchdog or somehow it is not enabled (supported but 364 * not enabled is though some bug and requires debugging :)). 365 */ 366 } 367 368 qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); 369 370 qemu_register_reset(ppc_booke_timer_reset_handle, cpu); 371 } 372