1 /* 2 * QEMU PowerPC Booke hardware System Emulator 3 * 4 * Copyright (c) 2011 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "qemu/timer.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/timer/m48t59.h" 29 #include "qemu/log.h" 30 #include "hw/loader.h" 31 #include "kvm_ppc.h" 32 33 34 /* Timer Control Register */ 35 36 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ 37 #define TCR_WP_MASK (0x3 << TCR_WP_SHIFT) 38 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ 39 #define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT) 40 #define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */ 41 #define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */ 42 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ 43 #define TCR_FP_MASK (0x3 << TCR_FP_SHIFT) 44 #define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */ 45 #define TCR_ARE (1 << 22) /* Auto-Reload Enable */ 46 47 /* Timer Control Register (e500 specific fields) */ 48 49 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ 50 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) 51 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ 52 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) 53 54 /* Timer Status Register */ 55 56 #define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */ 57 #define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */ 58 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ 59 #define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT) 60 #define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */ 61 #define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */ 62 63 typedef struct booke_timer_t booke_timer_t; 64 struct booke_timer_t { 65 66 uint64_t fit_next; 67 struct QEMUTimer *fit_timer; 68 69 uint64_t wdt_next; 70 struct QEMUTimer *wdt_timer; 71 72 uint32_t flags; 73 }; 74 75 static void booke_update_irq(PowerPCCPU *cpu) 76 { 77 CPUPPCState *env = &cpu->env; 78 79 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 80 (env->spr[SPR_BOOKE_TSR] & TSR_DIS 81 && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); 82 83 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 84 (env->spr[SPR_BOOKE_TSR] & TSR_WIS 85 && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); 86 87 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 88 (env->spr[SPR_BOOKE_TSR] & TSR_FIS 89 && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); 90 } 91 92 /* Return the location of the bit of time base at which the FIT will raise an 93 interrupt */ 94 static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) 95 { 96 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; 97 98 if (tb_env->flags & PPC_TIMER_E500) { 99 /* e500 Fixed-interval timer period extension */ 100 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) 101 >> TCR_E500_FPEXT_SHIFT; 102 fp = 63 - (fp | fpext << 2); 103 } else { 104 fp = env->fit_period[fp]; 105 } 106 107 return fp; 108 } 109 110 /* Return the location of the bit of time base at which the WDT will raise an 111 interrupt */ 112 static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) 113 { 114 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; 115 116 if (tb_env->flags & PPC_TIMER_E500) { 117 /* e500 Watchdog timer period extension */ 118 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) 119 >> TCR_E500_WPEXT_SHIFT; 120 wp = 63 - (wp | wpext << 2); 121 } else { 122 wp = env->wdt_period[wp]; 123 } 124 125 return wp; 126 } 127 128 static void booke_update_fixed_timer(CPUPPCState *env, 129 uint8_t target_bit, 130 uint64_t *next, 131 struct QEMUTimer *timer) 132 { 133 ppc_tb_t *tb_env = env->tb_env; 134 uint64_t delta_tick, ticks = 0; 135 uint64_t tb; 136 uint64_t period; 137 uint64_t now; 138 139 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 140 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); 141 period = 1ULL << target_bit; 142 delta_tick = period - (tb & (period - 1)); 143 144 /* the timer triggers only when the selected bit toggles from 0 to 1 */ 145 if (tb & period) { 146 ticks = period; 147 } 148 149 if (ticks + delta_tick < ticks) { 150 /* Overflow, so assume the biggest number we can express. */ 151 ticks = UINT64_MAX; 152 } else { 153 ticks += delta_tick; 154 } 155 156 *next = now + muldiv64(ticks, get_ticks_per_sec(), tb_env->tb_freq); 157 if ((*next < now) || (*next > INT64_MAX)) { 158 /* Overflow, so assume the biggest number the qemu timer supports. */ 159 *next = INT64_MAX; 160 } 161 162 /* XXX: If expire time is now. We can't run the callback because we don't 163 * have access to it. So we just set the timer one nanosecond later. 164 */ 165 166 if (*next == now) { 167 (*next)++; 168 } 169 170 timer_mod(timer, *next); 171 } 172 173 static void booke_decr_cb(void *opaque) 174 { 175 PowerPCCPU *cpu = opaque; 176 CPUPPCState *env = &cpu->env; 177 178 env->spr[SPR_BOOKE_TSR] |= TSR_DIS; 179 booke_update_irq(cpu); 180 181 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) { 182 /* Auto Reload */ 183 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); 184 } 185 } 186 187 static void booke_fit_cb(void *opaque) 188 { 189 PowerPCCPU *cpu = opaque; 190 CPUPPCState *env = &cpu->env; 191 ppc_tb_t *tb_env; 192 booke_timer_t *booke_timer; 193 194 tb_env = env->tb_env; 195 booke_timer = tb_env->opaque; 196 env->spr[SPR_BOOKE_TSR] |= TSR_FIS; 197 198 booke_update_irq(cpu); 199 200 booke_update_fixed_timer(env, 201 booke_get_fit_target(env, tb_env), 202 &booke_timer->fit_next, 203 booke_timer->fit_timer); 204 } 205 206 static void booke_wdt_cb(void *opaque) 207 { 208 PowerPCCPU *cpu = opaque; 209 CPUPPCState *env = &cpu->env; 210 ppc_tb_t *tb_env; 211 booke_timer_t *booke_timer; 212 213 tb_env = env->tb_env; 214 booke_timer = tb_env->opaque; 215 216 /* TODO: There's lots of complicated stuff to do here */ 217 218 booke_update_irq(cpu); 219 220 booke_update_fixed_timer(env, 221 booke_get_wdt_target(env, tb_env), 222 &booke_timer->wdt_next, 223 booke_timer->wdt_timer); 224 } 225 226 void store_booke_tsr(CPUPPCState *env, target_ulong val) 227 { 228 PowerPCCPU *cpu = ppc_env_get_cpu(env); 229 230 env->spr[SPR_BOOKE_TSR] &= ~val; 231 kvmppc_clear_tsr_bits(cpu, val); 232 booke_update_irq(cpu); 233 } 234 235 void store_booke_tcr(CPUPPCState *env, target_ulong val) 236 { 237 PowerPCCPU *cpu = ppc_env_get_cpu(env); 238 ppc_tb_t *tb_env = env->tb_env; 239 booke_timer_t *booke_timer = tb_env->opaque; 240 241 tb_env = env->tb_env; 242 env->spr[SPR_BOOKE_TCR] = val; 243 kvmppc_set_tcr(cpu); 244 245 booke_update_irq(cpu); 246 247 booke_update_fixed_timer(env, 248 booke_get_fit_target(env, tb_env), 249 &booke_timer->fit_next, 250 booke_timer->fit_timer); 251 252 booke_update_fixed_timer(env, 253 booke_get_wdt_target(env, tb_env), 254 &booke_timer->wdt_next, 255 booke_timer->wdt_timer); 256 } 257 258 static void ppc_booke_timer_reset_handle(void *opaque) 259 { 260 PowerPCCPU *cpu = opaque; 261 CPUPPCState *env = &cpu->env; 262 263 store_booke_tcr(env, 0); 264 store_booke_tsr(env, -1); 265 } 266 267 /* 268 * This function will be called whenever the CPU state changes. 269 * CPU states are defined "typedef enum RunState". 270 * Regarding timer, When CPU state changes to running after debug halt 271 * or similar cases which takes time then in between final watchdog 272 * expiry happenes. This will cause exit to QEMU and configured watchdog 273 * action will be taken. To avoid this we always clear the watchdog state when 274 * state changes to running. 275 */ 276 static void cpu_state_change_handler(void *opaque, int running, RunState state) 277 { 278 PowerPCCPU *cpu = opaque; 279 CPUPPCState *env = &cpu->env; 280 281 if (!running) { 282 return; 283 } 284 285 /* 286 * Clear watchdog interrupt condition by clearing TSR. 287 */ 288 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); 289 } 290 291 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) 292 { 293 ppc_tb_t *tb_env; 294 booke_timer_t *booke_timer; 295 int ret = 0; 296 297 tb_env = g_malloc0(sizeof(ppc_tb_t)); 298 booke_timer = g_malloc0(sizeof(booke_timer_t)); 299 300 cpu->env.tb_env = tb_env; 301 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; 302 303 tb_env->tb_freq = freq; 304 tb_env->decr_freq = freq; 305 tb_env->opaque = booke_timer; 306 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu); 307 308 booke_timer->fit_timer = 309 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu); 310 booke_timer->wdt_timer = 311 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu); 312 313 ret = kvmppc_booke_watchdog_enable(cpu); 314 315 if (ret) { 316 /* TODO: Start the QEMU emulated watchdog if not running on KVM. 317 * Also start the QEMU emulated watchdog if KVM does not support 318 * emulated watchdog or somehow it is not enabled (supported but 319 * not enabled is though some bug and requires debugging :)). 320 */ 321 } 322 323 qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); 324 325 qemu_register_reset(ppc_booke_timer_reset_handle, cpu); 326 } 327