153018216SPaolo Bonzini /*
253018216SPaolo Bonzini * QEMU PowerPC Booke hardware System Emulator
353018216SPaolo Bonzini *
453018216SPaolo Bonzini * Copyright (c) 2011 AdaCore
553018216SPaolo Bonzini *
653018216SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy
753018216SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal
853018216SPaolo Bonzini * in the Software without restriction, including without limitation the rights
953018216SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
1053018216SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is
1153018216SPaolo Bonzini * furnished to do so, subject to the following conditions:
1253018216SPaolo Bonzini *
1353018216SPaolo Bonzini * The above copyright notice and this permission notice shall be included in
1453018216SPaolo Bonzini * all copies or substantial portions of the Software.
1553018216SPaolo Bonzini *
1653018216SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1753018216SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1853018216SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1953018216SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2053018216SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2153018216SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
2253018216SPaolo Bonzini * THE SOFTWARE.
2353018216SPaolo Bonzini */
2471e8a915SMarkus Armbruster
250d75590dSPeter Maydell #include "qemu/osdep.h"
264771d756SPaolo Bonzini #include "cpu.h"
270d09e41aSPaolo Bonzini #include "hw/ppc/ppc.h"
2853018216SPaolo Bonzini #include "qemu/timer.h"
2971e8a915SMarkus Armbruster #include "sysemu/reset.h"
3054d31236SMarkus Armbruster #include "sysemu/runstate.h"
3153018216SPaolo Bonzini #include "hw/loader.h"
3231f2cb8fSBharat Bhushan #include "kvm_ppc.h"
3353018216SPaolo Bonzini
3453018216SPaolo Bonzini
3553018216SPaolo Bonzini /* Timer Control Register */
3653018216SPaolo Bonzini
3753018216SPaolo Bonzini #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
38a1f7f97bSPeter Maydell #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
3953018216SPaolo Bonzini #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
40a1f7f97bSPeter Maydell #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
41a1f7f97bSPeter Maydell #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
42a1f7f97bSPeter Maydell #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
4353018216SPaolo Bonzini #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
44a1f7f97bSPeter Maydell #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
45a1f7f97bSPeter Maydell #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
46a1f7f97bSPeter Maydell #define TCR_ARE (1U << 22) /* Auto-Reload Enable */
4753018216SPaolo Bonzini
4853018216SPaolo Bonzini /* Timer Control Register (e500 specific fields) */
4953018216SPaolo Bonzini
5053018216SPaolo Bonzini #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
5153018216SPaolo Bonzini #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
5253018216SPaolo Bonzini #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
5353018216SPaolo Bonzini #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
5453018216SPaolo Bonzini
5553018216SPaolo Bonzini /* Timer Status Register */
5653018216SPaolo Bonzini
57a1f7f97bSPeter Maydell #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
58a1f7f97bSPeter Maydell #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
5953018216SPaolo Bonzini #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
60a1f7f97bSPeter Maydell #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
61a1f7f97bSPeter Maydell #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
62a1f7f97bSPeter Maydell #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
6353018216SPaolo Bonzini
6453018216SPaolo Bonzini typedef struct booke_timer_t booke_timer_t;
6553018216SPaolo Bonzini struct booke_timer_t {
6653018216SPaolo Bonzini
6753018216SPaolo Bonzini uint64_t fit_next;
681246b259SStefan Weil QEMUTimer *fit_timer;
6953018216SPaolo Bonzini
7053018216SPaolo Bonzini uint64_t wdt_next;
711246b259SStefan Weil QEMUTimer *wdt_timer;
7253018216SPaolo Bonzini
7353018216SPaolo Bonzini uint32_t flags;
7453018216SPaolo Bonzini };
7553018216SPaolo Bonzini
booke_update_irq(PowerPCCPU * cpu)7653018216SPaolo Bonzini static void booke_update_irq(PowerPCCPU *cpu)
7753018216SPaolo Bonzini {
7853018216SPaolo Bonzini CPUPPCState *env = &cpu->env;
7953018216SPaolo Bonzini
8053018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
8153018216SPaolo Bonzini (env->spr[SPR_BOOKE_TSR] & TSR_DIS
8253018216SPaolo Bonzini && env->spr[SPR_BOOKE_TCR] & TCR_DIE));
8353018216SPaolo Bonzini
8453018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
8553018216SPaolo Bonzini (env->spr[SPR_BOOKE_TSR] & TSR_WIS
8653018216SPaolo Bonzini && env->spr[SPR_BOOKE_TCR] & TCR_WIE));
8753018216SPaolo Bonzini
8853018216SPaolo Bonzini ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
8953018216SPaolo Bonzini (env->spr[SPR_BOOKE_TSR] & TSR_FIS
9053018216SPaolo Bonzini && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
9153018216SPaolo Bonzini }
9253018216SPaolo Bonzini
9353018216SPaolo Bonzini /* Return the location of the bit of time base at which the FIT will raise an
9453018216SPaolo Bonzini interrupt */
booke_get_fit_target(CPUPPCState * env,ppc_tb_t * tb_env)9553018216SPaolo Bonzini static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
9653018216SPaolo Bonzini {
9753018216SPaolo Bonzini uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
9853018216SPaolo Bonzini
9953018216SPaolo Bonzini if (tb_env->flags & PPC_TIMER_E500) {
10053018216SPaolo Bonzini /* e500 Fixed-interval timer period extension */
10153018216SPaolo Bonzini uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
10253018216SPaolo Bonzini >> TCR_E500_FPEXT_SHIFT;
10353018216SPaolo Bonzini fp = 63 - (fp | fpext << 2);
10453018216SPaolo Bonzini } else {
10553018216SPaolo Bonzini fp = env->fit_period[fp];
10653018216SPaolo Bonzini }
10753018216SPaolo Bonzini
10853018216SPaolo Bonzini return fp;
10953018216SPaolo Bonzini }
11053018216SPaolo Bonzini
11153018216SPaolo Bonzini /* Return the location of the bit of time base at which the WDT will raise an
11253018216SPaolo Bonzini interrupt */
booke_get_wdt_target(CPUPPCState * env,ppc_tb_t * tb_env)11353018216SPaolo Bonzini static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
11453018216SPaolo Bonzini {
11553018216SPaolo Bonzini uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
11653018216SPaolo Bonzini
11753018216SPaolo Bonzini if (tb_env->flags & PPC_TIMER_E500) {
11853018216SPaolo Bonzini /* e500 Watchdog timer period extension */
11953018216SPaolo Bonzini uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
12053018216SPaolo Bonzini >> TCR_E500_WPEXT_SHIFT;
12153018216SPaolo Bonzini wp = 63 - (wp | wpext << 2);
12253018216SPaolo Bonzini } else {
12353018216SPaolo Bonzini wp = env->wdt_period[wp];
12453018216SPaolo Bonzini }
12553018216SPaolo Bonzini
12653018216SPaolo Bonzini return wp;
12753018216SPaolo Bonzini }
12853018216SPaolo Bonzini
booke_update_fixed_timer(CPUPPCState * env,uint8_t target_bit,uint64_t * next,QEMUTimer * timer,int tsr_bit)12953018216SPaolo Bonzini static void booke_update_fixed_timer(CPUPPCState *env,
13053018216SPaolo Bonzini uint8_t target_bit,
13153018216SPaolo Bonzini uint64_t *next,
132455df3f3SAlexander Graf QEMUTimer *timer,
133455df3f3SAlexander Graf int tsr_bit)
13453018216SPaolo Bonzini {
13553018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env;
136ab8131afSBharat Bhushan uint64_t delta_tick, ticks = 0;
13753018216SPaolo Bonzini uint64_t tb;
138ab8131afSBharat Bhushan uint64_t period;
13953018216SPaolo Bonzini uint64_t now;
14053018216SPaolo Bonzini
141455df3f3SAlexander Graf if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
142455df3f3SAlexander Graf /*
143455df3f3SAlexander Graf * Don't arm the timer again when the guest has the current
144455df3f3SAlexander Graf * interrupt still pending. Wait for it to ack it.
145455df3f3SAlexander Graf */
146455df3f3SAlexander Graf return;
147455df3f3SAlexander Graf }
148455df3f3SAlexander Graf
149bc72ad67SAlex Bligh now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
15053018216SPaolo Bonzini tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
151ab8131afSBharat Bhushan period = 1ULL << target_bit;
152ab8131afSBharat Bhushan delta_tick = period - (tb & (period - 1));
15353018216SPaolo Bonzini
154ab8131afSBharat Bhushan /* the timer triggers only when the selected bit toggles from 0 to 1 */
155ab8131afSBharat Bhushan if (tb & period) {
156ab8131afSBharat Bhushan ticks = period;
157ab8131afSBharat Bhushan }
15853018216SPaolo Bonzini
159ab8131afSBharat Bhushan if (ticks + delta_tick < ticks) {
160ab8131afSBharat Bhushan /* Overflow, so assume the biggest number we can express. */
161ab8131afSBharat Bhushan ticks = UINT64_MAX;
162ab8131afSBharat Bhushan } else {
163ab8131afSBharat Bhushan ticks += delta_tick;
164ab8131afSBharat Bhushan }
165ab8131afSBharat Bhushan
16673bcb24dSRutuja Shah *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
167ab8131afSBharat Bhushan if ((*next < now) || (*next > INT64_MAX)) {
168ab8131afSBharat Bhushan /* Overflow, so assume the biggest number the qemu timer supports. */
169ab8131afSBharat Bhushan *next = INT64_MAX;
170ab8131afSBharat Bhushan }
17153018216SPaolo Bonzini
17253018216SPaolo Bonzini /* XXX: If expire time is now. We can't run the callback because we don't
17353018216SPaolo Bonzini * have access to it. So we just set the timer one nanosecond later.
17453018216SPaolo Bonzini */
17553018216SPaolo Bonzini
17653018216SPaolo Bonzini if (*next == now) {
17753018216SPaolo Bonzini (*next)++;
17884dc96e1SAlexander Graf } else {
17984dc96e1SAlexander Graf /*
18084dc96e1SAlexander Graf * There's no point to fake any granularity that's more fine grained
18184dc96e1SAlexander Graf * than milliseconds. Anything beyond that just overloads the system.
18284dc96e1SAlexander Graf */
18384dc96e1SAlexander Graf *next = MAX(*next, now + SCALE_MS);
18453018216SPaolo Bonzini }
18553018216SPaolo Bonzini
186455df3f3SAlexander Graf /* Fire the next timer */
187bc72ad67SAlex Bligh timer_mod(timer, *next);
18853018216SPaolo Bonzini }
18953018216SPaolo Bonzini
booke_decr_cb(void * opaque)19053018216SPaolo Bonzini static void booke_decr_cb(void *opaque)
19153018216SPaolo Bonzini {
19253018216SPaolo Bonzini PowerPCCPU *cpu = opaque;
19353018216SPaolo Bonzini CPUPPCState *env = &cpu->env;
19453018216SPaolo Bonzini
19553018216SPaolo Bonzini env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
19653018216SPaolo Bonzini booke_update_irq(cpu);
19753018216SPaolo Bonzini
19853018216SPaolo Bonzini if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
1990dfe952dSRoman Kapl /* Do not reload 0, it is already there. It would just trigger
2000dfe952dSRoman Kapl * the timer again and lead to infinite loop */
2010dfe952dSRoman Kapl if (env->spr[SPR_BOOKE_DECAR] != 0) {
20253018216SPaolo Bonzini /* Auto Reload */
20353018216SPaolo Bonzini cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
20453018216SPaolo Bonzini }
20553018216SPaolo Bonzini }
2060dfe952dSRoman Kapl }
20753018216SPaolo Bonzini
booke_fit_cb(void * opaque)20853018216SPaolo Bonzini static void booke_fit_cb(void *opaque)
20953018216SPaolo Bonzini {
21053018216SPaolo Bonzini PowerPCCPU *cpu = opaque;
21153018216SPaolo Bonzini CPUPPCState *env = &cpu->env;
21253018216SPaolo Bonzini ppc_tb_t *tb_env;
21353018216SPaolo Bonzini booke_timer_t *booke_timer;
21453018216SPaolo Bonzini
21553018216SPaolo Bonzini tb_env = env->tb_env;
21653018216SPaolo Bonzini booke_timer = tb_env->opaque;
21753018216SPaolo Bonzini env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
21853018216SPaolo Bonzini
21953018216SPaolo Bonzini booke_update_irq(cpu);
22053018216SPaolo Bonzini
22153018216SPaolo Bonzini booke_update_fixed_timer(env,
22253018216SPaolo Bonzini booke_get_fit_target(env, tb_env),
22353018216SPaolo Bonzini &booke_timer->fit_next,
224455df3f3SAlexander Graf booke_timer->fit_timer,
225455df3f3SAlexander Graf TSR_FIS);
22653018216SPaolo Bonzini }
22753018216SPaolo Bonzini
booke_wdt_cb(void * opaque)22853018216SPaolo Bonzini static void booke_wdt_cb(void *opaque)
22953018216SPaolo Bonzini {
23053018216SPaolo Bonzini PowerPCCPU *cpu = opaque;
23153018216SPaolo Bonzini CPUPPCState *env = &cpu->env;
23253018216SPaolo Bonzini ppc_tb_t *tb_env;
23353018216SPaolo Bonzini booke_timer_t *booke_timer;
23453018216SPaolo Bonzini
23553018216SPaolo Bonzini tb_env = env->tb_env;
23653018216SPaolo Bonzini booke_timer = tb_env->opaque;
23753018216SPaolo Bonzini
23853018216SPaolo Bonzini /* TODO: There's lots of complicated stuff to do here */
23953018216SPaolo Bonzini
24053018216SPaolo Bonzini booke_update_irq(cpu);
24153018216SPaolo Bonzini
24253018216SPaolo Bonzini booke_update_fixed_timer(env,
24353018216SPaolo Bonzini booke_get_wdt_target(env, tb_env),
24453018216SPaolo Bonzini &booke_timer->wdt_next,
245455df3f3SAlexander Graf booke_timer->wdt_timer,
246455df3f3SAlexander Graf TSR_WIS);
24753018216SPaolo Bonzini }
24853018216SPaolo Bonzini
store_booke_tsr(CPUPPCState * env,target_ulong val)24953018216SPaolo Bonzini void store_booke_tsr(CPUPPCState *env, target_ulong val)
25053018216SPaolo Bonzini {
251db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env);
252455df3f3SAlexander Graf ppc_tb_t *tb_env = env->tb_env;
253455df3f3SAlexander Graf booke_timer_t *booke_timer = tb_env->opaque;
25453018216SPaolo Bonzini
25553018216SPaolo Bonzini env->spr[SPR_BOOKE_TSR] &= ~val;
25631f2cb8fSBharat Bhushan kvmppc_clear_tsr_bits(cpu, val);
257455df3f3SAlexander Graf
258455df3f3SAlexander Graf if (val & TSR_FIS) {
259455df3f3SAlexander Graf booke_update_fixed_timer(env,
260455df3f3SAlexander Graf booke_get_fit_target(env, tb_env),
261455df3f3SAlexander Graf &booke_timer->fit_next,
262455df3f3SAlexander Graf booke_timer->fit_timer,
263455df3f3SAlexander Graf TSR_FIS);
264455df3f3SAlexander Graf }
265455df3f3SAlexander Graf
266455df3f3SAlexander Graf if (val & TSR_WIS) {
267455df3f3SAlexander Graf booke_update_fixed_timer(env,
268455df3f3SAlexander Graf booke_get_wdt_target(env, tb_env),
269455df3f3SAlexander Graf &booke_timer->wdt_next,
270455df3f3SAlexander Graf booke_timer->wdt_timer,
271455df3f3SAlexander Graf TSR_WIS);
272455df3f3SAlexander Graf }
273455df3f3SAlexander Graf
27453018216SPaolo Bonzini booke_update_irq(cpu);
27553018216SPaolo Bonzini }
27653018216SPaolo Bonzini
store_booke_tcr(CPUPPCState * env,target_ulong val)27753018216SPaolo Bonzini void store_booke_tcr(CPUPPCState *env, target_ulong val)
27853018216SPaolo Bonzini {
279db70b311SRichard Henderson PowerPCCPU *cpu = env_archcpu(env);
28053018216SPaolo Bonzini ppc_tb_t *tb_env = env->tb_env;
28153018216SPaolo Bonzini booke_timer_t *booke_timer = tb_env->opaque;
28253018216SPaolo Bonzini
28353018216SPaolo Bonzini env->spr[SPR_BOOKE_TCR] = val;
28431f2cb8fSBharat Bhushan kvmppc_set_tcr(cpu);
28553018216SPaolo Bonzini
28653018216SPaolo Bonzini booke_update_irq(cpu);
28753018216SPaolo Bonzini
28853018216SPaolo Bonzini booke_update_fixed_timer(env,
28953018216SPaolo Bonzini booke_get_fit_target(env, tb_env),
29053018216SPaolo Bonzini &booke_timer->fit_next,
291455df3f3SAlexander Graf booke_timer->fit_timer,
292455df3f3SAlexander Graf TSR_FIS);
29353018216SPaolo Bonzini
29453018216SPaolo Bonzini booke_update_fixed_timer(env,
29553018216SPaolo Bonzini booke_get_wdt_target(env, tb_env),
29653018216SPaolo Bonzini &booke_timer->wdt_next,
297455df3f3SAlexander Graf booke_timer->wdt_timer,
298455df3f3SAlexander Graf TSR_WIS);
29953018216SPaolo Bonzini }
30053018216SPaolo Bonzini
ppc_booke_timer_reset_handle(void * opaque)30153018216SPaolo Bonzini static void ppc_booke_timer_reset_handle(void *opaque)
30253018216SPaolo Bonzini {
30353018216SPaolo Bonzini PowerPCCPU *cpu = opaque;
30453018216SPaolo Bonzini CPUPPCState *env = &cpu->env;
30553018216SPaolo Bonzini
30631f2cb8fSBharat Bhushan store_booke_tcr(env, 0);
30731f2cb8fSBharat Bhushan store_booke_tsr(env, -1);
30831f2cb8fSBharat Bhushan }
30953018216SPaolo Bonzini
31031f2cb8fSBharat Bhushan /*
31131f2cb8fSBharat Bhushan * This function will be called whenever the CPU state changes.
31231f2cb8fSBharat Bhushan * CPU states are defined "typedef enum RunState".
31331f2cb8fSBharat Bhushan * Regarding timer, When CPU state changes to running after debug halt
31431f2cb8fSBharat Bhushan * or similar cases which takes time then in between final watchdog
31531f2cb8fSBharat Bhushan * expiry happenes. This will cause exit to QEMU and configured watchdog
31631f2cb8fSBharat Bhushan * action will be taken. To avoid this we always clear the watchdog state when
31731f2cb8fSBharat Bhushan * state changes to running.
31831f2cb8fSBharat Bhushan */
cpu_state_change_handler(void * opaque,bool running,RunState state)319538f0497SPhilippe Mathieu-Daudé static void cpu_state_change_handler(void *opaque, bool running, RunState state)
32031f2cb8fSBharat Bhushan {
32131f2cb8fSBharat Bhushan PowerPCCPU *cpu = opaque;
32231f2cb8fSBharat Bhushan CPUPPCState *env = &cpu->env;
32331f2cb8fSBharat Bhushan
32431f2cb8fSBharat Bhushan if (!running) {
32531f2cb8fSBharat Bhushan return;
32631f2cb8fSBharat Bhushan }
32731f2cb8fSBharat Bhushan
32831f2cb8fSBharat Bhushan /*
32931f2cb8fSBharat Bhushan * Clear watchdog interrupt condition by clearing TSR.
33031f2cb8fSBharat Bhushan */
33131f2cb8fSBharat Bhushan store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
33253018216SPaolo Bonzini }
33353018216SPaolo Bonzini
ppc_booke_timers_init(PowerPCCPU * cpu,uint32_t freq,uint32_t flags)33453018216SPaolo Bonzini void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
33553018216SPaolo Bonzini {
33653018216SPaolo Bonzini ppc_tb_t *tb_env;
33753018216SPaolo Bonzini booke_timer_t *booke_timer;
33831f2cb8fSBharat Bhushan int ret = 0;
33953018216SPaolo Bonzini
340*b21e2380SMarkus Armbruster tb_env = g_new0(ppc_tb_t, 1);
341*b21e2380SMarkus Armbruster booke_timer = g_new0(booke_timer_t, 1);
34253018216SPaolo Bonzini
34353018216SPaolo Bonzini cpu->env.tb_env = tb_env;
34453018216SPaolo Bonzini tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
34553018216SPaolo Bonzini
34653018216SPaolo Bonzini tb_env->tb_freq = freq;
34753018216SPaolo Bonzini tb_env->decr_freq = freq;
34853018216SPaolo Bonzini tb_env->opaque = booke_timer;
349bc72ad67SAlex Bligh tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
35053018216SPaolo Bonzini
35153018216SPaolo Bonzini booke_timer->fit_timer =
352bc72ad67SAlex Bligh timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
35353018216SPaolo Bonzini booke_timer->wdt_timer =
354bc72ad67SAlex Bligh timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
35553018216SPaolo Bonzini
35631f2cb8fSBharat Bhushan ret = kvmppc_booke_watchdog_enable(cpu);
35731f2cb8fSBharat Bhushan
35831f2cb8fSBharat Bhushan if (ret) {
35931f2cb8fSBharat Bhushan /* TODO: Start the QEMU emulated watchdog if not running on KVM.
36031f2cb8fSBharat Bhushan * Also start the QEMU emulated watchdog if KVM does not support
36131f2cb8fSBharat Bhushan * emulated watchdog or somehow it is not enabled (supported but
36231f2cb8fSBharat Bhushan * not enabled is though some bug and requires debugging :)).
36331f2cb8fSBharat Bhushan */
36431f2cb8fSBharat Bhushan }
36531f2cb8fSBharat Bhushan
36631f2cb8fSBharat Bhushan qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
36731f2cb8fSBharat Bhushan
36853018216SPaolo Bonzini qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
36953018216SPaolo Bonzini }
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