1 /* 2 * QEMU PowerPC 4xx embedded processors SDRAM controller emulation 3 * 4 * DDR SDRAM controller: 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * DDR2 SDRAM controller: 26 * Copyright (c) 2012 François Revol 27 * Copyright (c) 2016-2019 BALATON Zoltan 28 * 29 * This work is licensed under the GNU GPL license version 2 or later. 30 */ 31 32 #include "qemu/osdep.h" 33 #include "qemu/units.h" 34 #include "qapi/error.h" 35 #include "qemu/log.h" 36 #include "exec/address-spaces.h" /* get_system_memory() */ 37 #include "hw/irq.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/ppc/ppc4xx.h" 40 #include "trace.h" 41 42 /*****************************************************************************/ 43 /* Shared functions */ 44 45 /* 46 * Split RAM between SDRAM banks. 47 * 48 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] 49 * and must be 0-terminated. 50 * 51 * The 4xx SDRAM controller supports a small number of banks, and each bank 52 * must be one of a small set of sizes. The number of banks and the supported 53 * sizes varies by SoC. 54 */ 55 static bool ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 56 Ppc4xxSdramBank ram_banks[], 57 const ram_addr_t sdram_bank_sizes[], 58 Error **errp) 59 { 60 ERRP_GUARD(); 61 ram_addr_t size_left = memory_region_size(ram); 62 ram_addr_t base = 0; 63 ram_addr_t bank_size; 64 int i; 65 int j; 66 67 for (i = 0; i < nr_banks; i++) { 68 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 69 bank_size = sdram_bank_sizes[j]; 70 if (bank_size <= size_left) { 71 char name[32]; 72 73 ram_banks[i].base = base; 74 ram_banks[i].size = bank_size; 75 base += bank_size; 76 size_left -= bank_size; 77 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 78 memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram, 79 ram_banks[i].base, ram_banks[i].size); 80 break; 81 } 82 } 83 if (!size_left) { 84 /* No need to use the remaining banks. */ 85 break; 86 } 87 } 88 89 if (size_left) { 90 ram_addr_t used_size = memory_region_size(ram) - size_left; 91 GString *s = g_string_new(NULL); 92 93 for (i = 0; sdram_bank_sizes[i]; i++) { 94 g_string_append_printf(s, "%" PRIi64 "%s", 95 sdram_bank_sizes[i] / MiB, 96 sdram_bank_sizes[i + 1] ? ", " : ""); 97 } 98 error_setg(errp, "Invalid SDRAM banks"); 99 error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n", 100 nr_banks, nr_banks == 1 ? "" : "s", s->str); 101 error_append_hint(errp, "Possible valid RAM size: %" PRIi64 " MiB\n", 102 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); 103 104 g_string_free(s, true); 105 return false; 106 } 107 return true; 108 } 109 110 static void sdram_bank_map(Ppc4xxSdramBank *bank) 111 { 112 trace_ppc4xx_sdram_map(bank->base, bank->size); 113 memory_region_init(&bank->container, NULL, "sdram-container", bank->size); 114 memory_region_add_subregion(&bank->container, 0, &bank->ram); 115 memory_region_add_subregion(get_system_memory(), bank->base, 116 &bank->container); 117 } 118 119 static void sdram_bank_unmap(Ppc4xxSdramBank *bank) 120 { 121 trace_ppc4xx_sdram_unmap(bank->base, bank->size); 122 memory_region_del_subregion(get_system_memory(), &bank->container); 123 memory_region_del_subregion(&bank->container, &bank->ram); 124 object_unparent(OBJECT(&bank->container)); 125 } 126 127 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr, 128 hwaddr base, hwaddr size, int enabled) 129 { 130 if (memory_region_is_mapped(&bank->container)) { 131 sdram_bank_unmap(bank); 132 } 133 bank->bcr = bcr; 134 bank->base = base; 135 bank->size = size; 136 if (enabled && (bcr & 1)) { 137 sdram_bank_map(bank); 138 } 139 } 140 141 enum { 142 SDRAM0_CFGADDR = 0x010, 143 SDRAM0_CFGDATA = 0x011, 144 }; 145 146 /*****************************************************************************/ 147 /* DDR SDRAM controller */ 148 #define SDRAM_DDR_BCR_MASK 0xFFDEE001 149 150 static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) 151 { 152 uint32_t bcr; 153 154 switch (ram_size) { 155 case 4 * MiB: 156 bcr = 0; 157 break; 158 case 8 * MiB: 159 bcr = 0x20000; 160 break; 161 case 16 * MiB: 162 bcr = 0x40000; 163 break; 164 case 32 * MiB: 165 bcr = 0x60000; 166 break; 167 case 64 * MiB: 168 bcr = 0x80000; 169 break; 170 case 128 * MiB: 171 bcr = 0xA0000; 172 break; 173 case 256 * MiB: 174 bcr = 0xC0000; 175 break; 176 default: 177 qemu_log_mask(LOG_GUEST_ERROR, 178 "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__, 179 ram_size); 180 return 0; 181 } 182 bcr |= ram_base & 0xFF800000; 183 bcr |= 1; 184 185 return bcr; 186 } 187 188 static inline hwaddr sdram_ddr_base(uint32_t bcr) 189 { 190 return bcr & 0xFF800000; 191 } 192 193 static hwaddr sdram_ddr_size(uint32_t bcr) 194 { 195 hwaddr size; 196 int sh; 197 198 sh = (bcr >> 17) & 0x7; 199 if (sh == 7) { 200 size = -1; 201 } else { 202 size = (4 * MiB) << sh; 203 } 204 205 return size; 206 } 207 208 static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) 209 { 210 Ppc4xxSdramDdrState *s = opaque; 211 uint32_t ret; 212 213 switch (dcrn) { 214 case SDRAM0_CFGADDR: 215 ret = s->addr; 216 break; 217 case SDRAM0_CFGDATA: 218 switch (s->addr) { 219 case 0x00: /* SDRAM_BESR0 */ 220 ret = s->besr0; 221 break; 222 case 0x08: /* SDRAM_BESR1 */ 223 ret = s->besr1; 224 break; 225 case 0x10: /* SDRAM_BEAR */ 226 ret = s->bear; 227 break; 228 case 0x20: /* SDRAM_CFG */ 229 ret = s->cfg; 230 break; 231 case 0x24: /* SDRAM_STATUS */ 232 ret = s->status; 233 break; 234 case 0x30: /* SDRAM_RTR */ 235 ret = s->rtr; 236 break; 237 case 0x34: /* SDRAM_PMIT */ 238 ret = s->pmit; 239 break; 240 case 0x40: /* SDRAM_B0CR */ 241 ret = s->bank[0].bcr; 242 break; 243 case 0x44: /* SDRAM_B1CR */ 244 ret = s->bank[1].bcr; 245 break; 246 case 0x48: /* SDRAM_B2CR */ 247 ret = s->bank[2].bcr; 248 break; 249 case 0x4C: /* SDRAM_B3CR */ 250 ret = s->bank[3].bcr; 251 break; 252 case 0x80: /* SDRAM_TR */ 253 ret = -1; /* ? */ 254 break; 255 case 0x94: /* SDRAM_ECCCFG */ 256 ret = s->ecccfg; 257 break; 258 case 0x98: /* SDRAM_ECCESR */ 259 ret = s->eccesr; 260 break; 261 default: /* Error */ 262 ret = -1; 263 break; 264 } 265 break; 266 default: 267 /* Avoid gcc warning */ 268 ret = 0; 269 break; 270 } 271 272 return ret; 273 } 274 275 static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) 276 { 277 Ppc4xxSdramDdrState *s = opaque; 278 int i; 279 280 switch (dcrn) { 281 case SDRAM0_CFGADDR: 282 s->addr = val; 283 break; 284 case SDRAM0_CFGDATA: 285 switch (s->addr) { 286 case 0x00: /* SDRAM_BESR0 */ 287 s->besr0 &= ~val; 288 break; 289 case 0x08: /* SDRAM_BESR1 */ 290 s->besr1 &= ~val; 291 break; 292 case 0x10: /* SDRAM_BEAR */ 293 s->bear = val; 294 break; 295 case 0x20: /* SDRAM_CFG */ 296 val &= 0xFFE00000; 297 if (!(s->cfg & 0x80000000) && (val & 0x80000000)) { 298 trace_ppc4xx_sdram_enable("enable"); 299 /* validate all RAM mappings */ 300 for (i = 0; i < s->nbanks; i++) { 301 if (s->bank[i].size) { 302 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, 303 s->bank[i].base, s->bank[i].size, 304 1); 305 } 306 } 307 s->status &= ~0x80000000; 308 } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) { 309 trace_ppc4xx_sdram_enable("disable"); 310 /* invalidate all RAM mappings */ 311 for (i = 0; i < s->nbanks; i++) { 312 if (s->bank[i].size) { 313 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, 314 s->bank[i].base, s->bank[i].size, 315 0); 316 } 317 } 318 s->status |= 0x80000000; 319 } 320 if (!(s->cfg & 0x40000000) && (val & 0x40000000)) { 321 s->status |= 0x40000000; 322 } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) { 323 s->status &= ~0x40000000; 324 } 325 s->cfg = val; 326 break; 327 case 0x24: /* SDRAM_STATUS */ 328 /* Read-only register */ 329 break; 330 case 0x30: /* SDRAM_RTR */ 331 s->rtr = val & 0x3FF80000; 332 break; 333 case 0x34: /* SDRAM_PMIT */ 334 s->pmit = (val & 0xF8000000) | 0x07C00000; 335 break; 336 case 0x40: /* SDRAM_B0CR */ 337 case 0x44: /* SDRAM_B1CR */ 338 case 0x48: /* SDRAM_B2CR */ 339 case 0x4C: /* SDRAM_B3CR */ 340 i = (s->addr - 0x40) / 4; 341 val &= SDRAM_DDR_BCR_MASK; 342 if (s->bank[i].size) { 343 sdram_bank_set_bcr(&s->bank[i], val, 344 sdram_ddr_base(val), sdram_ddr_size(val), 345 s->cfg & 0x80000000); 346 } 347 break; 348 case 0x80: /* SDRAM_TR */ 349 s->tr = val & 0x018FC01F; 350 break; 351 case 0x94: /* SDRAM_ECCCFG */ 352 s->ecccfg = val & 0x00F00000; 353 break; 354 case 0x98: /* SDRAM_ECCESR */ 355 val &= 0xFFF0F000; 356 if (s->eccesr == 0 && val != 0) { 357 qemu_irq_raise(s->irq); 358 } else if (s->eccesr != 0 && val == 0) { 359 qemu_irq_lower(s->irq); 360 } 361 s->eccesr = val; 362 break; 363 default: /* Error */ 364 break; 365 } 366 break; 367 } 368 } 369 370 static void ppc4xx_sdram_ddr_reset(DeviceState *dev) 371 { 372 Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev); 373 374 s->addr = 0; 375 s->bear = 0; 376 s->besr0 = 0; /* No error */ 377 s->besr1 = 0; /* No error */ 378 s->cfg = 0; 379 s->ecccfg = 0; /* No ECC */ 380 s->eccesr = 0; /* No error */ 381 s->pmit = 0x07C00000; 382 s->rtr = 0x05F00000; 383 s->tr = 0x00854009; 384 /* We pre-initialize RAM banks */ 385 s->status = 0; 386 s->cfg = 0x00800000; 387 } 388 389 static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) 390 { 391 Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev); 392 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 393 const ram_addr_t valid_bank_sizes[] = { 394 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0 395 }; 396 int i; 397 398 if (s->nbanks < 1 || s->nbanks > 4) { 399 error_setg(errp, "Invalid number of RAM banks"); 400 return; 401 } 402 if (!s->dram_mr) { 403 error_setg(errp, "Missing dram memory region"); 404 return; 405 } 406 if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, 407 valid_bank_sizes, errp)) { 408 return; 409 } 410 for (i = 0; i < s->nbanks; i++) { 411 if (s->bank[i].size) { 412 s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size); 413 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, 414 s->bank[i].base, s->bank[i].size, 0); 415 } else { 416 sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0); 417 } 418 trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr), 419 sdram_ddr_size(s->bank[i].bcr), 420 s->bank[i].bcr); 421 } 422 423 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 424 425 ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, 426 s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); 427 ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, 428 s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); 429 } 430 431 static Property ppc4xx_sdram_ddr_props[] = { 432 DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION, 433 MemoryRegion *), 434 DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4), 435 DEFINE_PROP_END_OF_LIST(), 436 }; 437 438 static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data) 439 { 440 DeviceClass *dc = DEVICE_CLASS(oc); 441 442 dc->realize = ppc4xx_sdram_ddr_realize; 443 dc->reset = ppc4xx_sdram_ddr_reset; 444 /* Reason: only works as function of a ppc4xx SoC */ 445 dc->user_creatable = false; 446 device_class_set_props(dc, ppc4xx_sdram_ddr_props); 447 } 448 449 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s) 450 { 451 sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20); 452 sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000); 453 } 454 455 /*****************************************************************************/ 456 /* DDR2 SDRAM controller */ 457 #define SDRAM_DDR2_BCR_MASK 0xffe0ffc1 458 459 enum { 460 SDRAM_R0BAS = 0x40, 461 SDRAM_R1BAS, 462 SDRAM_R2BAS, 463 SDRAM_R3BAS, 464 SDRAM_CONF1HB = 0x45, 465 SDRAM_PLBADDULL = 0x4a, 466 SDRAM_CONF1LL = 0x4b, 467 SDRAM_CONFPATHB = 0x4f, 468 SDRAM_PLBADDUHB = 0x50, 469 }; 470 471 static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) 472 { 473 uint32_t bcr; 474 475 switch (ram_size) { 476 case 8 * MiB: 477 bcr = 0xffc0; 478 break; 479 case 16 * MiB: 480 bcr = 0xff80; 481 break; 482 case 32 * MiB: 483 bcr = 0xff00; 484 break; 485 case 64 * MiB: 486 bcr = 0xfe00; 487 break; 488 case 128 * MiB: 489 bcr = 0xfc00; 490 break; 491 case 256 * MiB: 492 bcr = 0xf800; 493 break; 494 case 512 * MiB: 495 bcr = 0xf000; 496 break; 497 case 1 * GiB: 498 bcr = 0xe000; 499 break; 500 case 2 * GiB: 501 bcr = 0xc000; 502 break; 503 case 4 * GiB: 504 bcr = 0x8000; 505 break; 506 default: 507 error_report("invalid RAM size " TARGET_FMT_plx, ram_size); 508 return 0; 509 } 510 bcr |= ram_base >> 2 & 0xffe00000; 511 bcr |= 1; 512 513 return bcr; 514 } 515 516 static inline hwaddr sdram_ddr2_base(uint32_t bcr) 517 { 518 return (bcr & 0xffe00000) << 2; 519 } 520 521 static hwaddr sdram_ddr2_size(uint32_t bcr) 522 { 523 hwaddr size; 524 int sh; 525 526 sh = 1024 - ((bcr >> 6) & 0x3ff); 527 size = 8 * MiB * sh; 528 529 return size; 530 } 531 532 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) 533 { 534 Ppc4xxSdramDdr2State *s = opaque; 535 uint32_t ret = 0; 536 537 switch (dcrn) { 538 case SDRAM_R0BAS: 539 case SDRAM_R1BAS: 540 case SDRAM_R2BAS: 541 case SDRAM_R3BAS: 542 if (s->bank[dcrn - SDRAM_R0BAS].size) { 543 ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base, 544 s->bank[dcrn - SDRAM_R0BAS].size); 545 } 546 break; 547 case SDRAM_CONF1HB: 548 case SDRAM_CONF1LL: 549 case SDRAM_CONFPATHB: 550 case SDRAM_PLBADDULL: 551 case SDRAM_PLBADDUHB: 552 break; 553 case SDRAM0_CFGADDR: 554 ret = s->addr; 555 break; 556 case SDRAM0_CFGDATA: 557 switch (s->addr) { 558 case 0x14: /* SDRAM_MCSTAT (405EX) */ 559 case 0x1F: 560 ret = 0x80000000; 561 break; 562 case 0x21: /* SDRAM_MCOPT2 */ 563 ret = s->mcopt2; 564 break; 565 case 0x40: /* SDRAM_MB0CF */ 566 ret = 0x00008001; 567 break; 568 case 0x7A: /* SDRAM_DLCR */ 569 ret = 0x02000000; 570 break; 571 case 0xE1: /* SDR0_DDR0 */ 572 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 573 break; 574 default: 575 break; 576 } 577 break; 578 default: 579 break; 580 } 581 582 return ret; 583 } 584 585 #define SDRAM_DDR2_MCOPT2_DCEN BIT(27) 586 587 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) 588 { 589 Ppc4xxSdramDdr2State *s = opaque; 590 int i; 591 592 switch (dcrn) { 593 case SDRAM_R0BAS: 594 case SDRAM_R1BAS: 595 case SDRAM_R2BAS: 596 case SDRAM_R3BAS: 597 case SDRAM_CONF1HB: 598 case SDRAM_CONF1LL: 599 case SDRAM_CONFPATHB: 600 case SDRAM_PLBADDULL: 601 case SDRAM_PLBADDUHB: 602 break; 603 case SDRAM0_CFGADDR: 604 s->addr = val; 605 break; 606 case SDRAM0_CFGDATA: 607 switch (s->addr) { 608 case 0x00: /* B0CR */ 609 break; 610 case 0x21: /* SDRAM_MCOPT2 */ 611 if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && 612 (val & SDRAM_DDR2_MCOPT2_DCEN)) { 613 trace_ppc4xx_sdram_enable("enable"); 614 /* validate all RAM mappings */ 615 for (i = 0; i < s->nbanks; i++) { 616 if (s->bank[i].size) { 617 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, 618 s->bank[i].base, s->bank[i].size, 619 1); 620 } 621 } 622 s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN; 623 } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && 624 !(val & SDRAM_DDR2_MCOPT2_DCEN)) { 625 trace_ppc4xx_sdram_enable("disable"); 626 /* invalidate all RAM mappings */ 627 for (i = 0; i < s->nbanks; i++) { 628 if (s->bank[i].size) { 629 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, 630 s->bank[i].base, s->bank[i].size, 631 0); 632 } 633 } 634 s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN; 635 } 636 break; 637 default: 638 break; 639 } 640 break; 641 default: 642 break; 643 } 644 } 645 646 static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) 647 { 648 Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev); 649 650 s->addr = 0; 651 s->mcopt2 = 0; 652 } 653 654 static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) 655 { 656 Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev); 657 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 658 /* 659 * SoC also has 4 GiB but that causes problem with 32 bit 660 * builds (4*GiB overflows the 32 bit ram_addr_t). 661 */ 662 const ram_addr_t valid_bank_sizes[] = { 663 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 664 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 665 }; 666 int i; 667 668 if (s->nbanks < 1 || s->nbanks > 4) { 669 error_setg(errp, "Invalid number of RAM banks"); 670 return; 671 } 672 if (!s->dram_mr) { 673 error_setg(errp, "Missing dram memory region"); 674 return; 675 } 676 if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, 677 valid_bank_sizes, errp)) { 678 return; 679 } 680 for (i = 0; i < s->nbanks; i++) { 681 if (s->bank[i].size) { 682 s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size); 683 s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK; 684 sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, 685 s->bank[i].base, s->bank[i].size, 0); 686 } else { 687 sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0); 688 } 689 trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr), 690 sdram_ddr2_size(s->bank[i].bcr), 691 s->bank[i].bcr); 692 } 693 694 ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, 695 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 696 ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, 697 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 698 699 ppc4xx_dcr_register(dcr, SDRAM_R0BAS, 700 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 701 ppc4xx_dcr_register(dcr, SDRAM_R1BAS, 702 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 703 ppc4xx_dcr_register(dcr, SDRAM_R2BAS, 704 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 705 ppc4xx_dcr_register(dcr, SDRAM_R3BAS, 706 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 707 ppc4xx_dcr_register(dcr, SDRAM_CONF1HB, 708 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 709 ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL, 710 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 711 ppc4xx_dcr_register(dcr, SDRAM_CONF1LL, 712 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 713 ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB, 714 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 715 ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB, 716 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 717 } 718 719 static Property ppc4xx_sdram_ddr2_props[] = { 720 DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION, 721 MemoryRegion *), 722 DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4), 723 DEFINE_PROP_END_OF_LIST(), 724 }; 725 726 static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data) 727 { 728 DeviceClass *dc = DEVICE_CLASS(oc); 729 730 dc->realize = ppc4xx_sdram_ddr2_realize; 731 dc->reset = ppc4xx_sdram_ddr2_reset; 732 /* Reason: only works as function of a ppc4xx SoC */ 733 dc->user_creatable = false; 734 device_class_set_props(dc, ppc4xx_sdram_ddr2_props); 735 } 736 737 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s) 738 { 739 sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21); 740 sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000); 741 } 742 743 static const TypeInfo ppc4xx_sdram_types[] = { 744 { 745 .name = TYPE_PPC4xx_SDRAM_DDR, 746 .parent = TYPE_PPC4xx_DCR_DEVICE, 747 .instance_size = sizeof(Ppc4xxSdramDdrState), 748 .class_init = ppc4xx_sdram_ddr_class_init, 749 }, { 750 .name = TYPE_PPC4xx_SDRAM_DDR2, 751 .parent = TYPE_PPC4xx_DCR_DEVICE, 752 .instance_size = sizeof(Ppc4xxSdramDdr2State), 753 .class_init = ppc4xx_sdram_ddr2_class_init, 754 } 755 }; 756 757 DEFINE_TYPES(ppc4xx_sdram_types) 758