1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, see <http://www.gnu.org/licenses/>. 13 * 14 * Copyright IBM Corp. 2008 15 * 16 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 17 */ 18 19 /* This file implements emulation of the 32-bit PCI controller found in some 20 * 4xx SoCs, such as the 440EP. */ 21 22 #include "qemu/osdep.h" 23 #include "hw/irq.h" 24 #include "hw/ppc/ppc.h" 25 #include "hw/ppc/ppc4xx.h" 26 #include "migration/vmstate.h" 27 #include "qemu/module.h" 28 #include "sysemu/reset.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_host.h" 31 #include "trace.h" 32 #include "qom/object.h" 33 34 struct PCIMasterMap { 35 uint32_t la; 36 uint32_t ma; 37 uint32_t pcila; 38 uint32_t pciha; 39 }; 40 41 struct PCITargetMap { 42 uint32_t ms; 43 uint32_t la; 44 }; 45 46 OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE) 47 48 #define PPC4xx_PCI_NR_PMMS 3 49 #define PPC4xx_PCI_NR_PTMS 2 50 51 struct PPC4xxPCIState { 52 PCIHostState parent_obj; 53 54 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; 55 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; 56 qemu_irq irq[PCI_NUM_PINS]; 57 58 MemoryRegion container; 59 MemoryRegion iomem; 60 }; 61 62 #define PCIC0_CFGADDR 0x0 63 #define PCIC0_CFGDATA 0x4 64 65 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to 66 * PCI accesses. */ 67 #define PCIL0_PMM0LA 0x0 68 #define PCIL0_PMM0MA 0x4 69 #define PCIL0_PMM0PCILA 0x8 70 #define PCIL0_PMM0PCIHA 0xc 71 #define PCIL0_PMM1LA 0x10 72 #define PCIL0_PMM1MA 0x14 73 #define PCIL0_PMM1PCILA 0x18 74 #define PCIL0_PMM1PCIHA 0x1c 75 #define PCIL0_PMM2LA 0x20 76 #define PCIL0_PMM2MA 0x24 77 #define PCIL0_PMM2PCILA 0x28 78 #define PCIL0_PMM2PCIHA 0x2c 79 80 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to 81 * PLB accesses. */ 82 #define PCIL0_PTM1MS 0x30 83 #define PCIL0_PTM1LA 0x34 84 #define PCIL0_PTM2MS 0x38 85 #define PCIL0_PTM2LA 0x3c 86 #define PCI_REG_BASE 0x800000 87 #define PCI_REG_SIZE 0x40 88 89 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE) 90 91 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset, 92 uint64_t value, unsigned size) 93 { 94 struct PPC4xxPCIState *pci = opaque; 95 96 /* We ignore all target attempts at PCI configuration, effectively 97 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ 98 99 switch (offset) { 100 case PCIL0_PMM0LA: 101 pci->pmm[0].la = value; 102 break; 103 case PCIL0_PMM0MA: 104 pci->pmm[0].ma = value; 105 break; 106 case PCIL0_PMM0PCIHA: 107 pci->pmm[0].pciha = value; 108 break; 109 case PCIL0_PMM0PCILA: 110 pci->pmm[0].pcila = value; 111 break; 112 113 case PCIL0_PMM1LA: 114 pci->pmm[1].la = value; 115 break; 116 case PCIL0_PMM1MA: 117 pci->pmm[1].ma = value; 118 break; 119 case PCIL0_PMM1PCIHA: 120 pci->pmm[1].pciha = value; 121 break; 122 case PCIL0_PMM1PCILA: 123 pci->pmm[1].pcila = value; 124 break; 125 126 case PCIL0_PMM2LA: 127 pci->pmm[2].la = value; 128 break; 129 case PCIL0_PMM2MA: 130 pci->pmm[2].ma = value; 131 break; 132 case PCIL0_PMM2PCIHA: 133 pci->pmm[2].pciha = value; 134 break; 135 case PCIL0_PMM2PCILA: 136 pci->pmm[2].pcila = value; 137 break; 138 139 case PCIL0_PTM1MS: 140 pci->ptm[0].ms = value; 141 break; 142 case PCIL0_PTM1LA: 143 pci->ptm[0].la = value; 144 break; 145 case PCIL0_PTM2MS: 146 pci->ptm[1].ms = value; 147 break; 148 case PCIL0_PTM2LA: 149 pci->ptm[1].la = value; 150 break; 151 152 default: 153 printf("%s: unhandled PCI internal register 0x%lx\n", __func__, 154 (unsigned long)offset); 155 break; 156 } 157 } 158 159 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset, 160 unsigned size) 161 { 162 struct PPC4xxPCIState *pci = opaque; 163 uint32_t value; 164 165 switch (offset) { 166 case PCIL0_PMM0LA: 167 value = pci->pmm[0].la; 168 break; 169 case PCIL0_PMM0MA: 170 value = pci->pmm[0].ma; 171 break; 172 case PCIL0_PMM0PCIHA: 173 value = pci->pmm[0].pciha; 174 break; 175 case PCIL0_PMM0PCILA: 176 value = pci->pmm[0].pcila; 177 break; 178 179 case PCIL0_PMM1LA: 180 value = pci->pmm[1].la; 181 break; 182 case PCIL0_PMM1MA: 183 value = pci->pmm[1].ma; 184 break; 185 case PCIL0_PMM1PCIHA: 186 value = pci->pmm[1].pciha; 187 break; 188 case PCIL0_PMM1PCILA: 189 value = pci->pmm[1].pcila; 190 break; 191 192 case PCIL0_PMM2LA: 193 value = pci->pmm[2].la; 194 break; 195 case PCIL0_PMM2MA: 196 value = pci->pmm[2].ma; 197 break; 198 case PCIL0_PMM2PCIHA: 199 value = pci->pmm[2].pciha; 200 break; 201 case PCIL0_PMM2PCILA: 202 value = pci->pmm[2].pcila; 203 break; 204 205 case PCIL0_PTM1MS: 206 value = pci->ptm[0].ms; 207 break; 208 case PCIL0_PTM1LA: 209 value = pci->ptm[0].la; 210 break; 211 case PCIL0_PTM2MS: 212 value = pci->ptm[1].ms; 213 break; 214 case PCIL0_PTM2LA: 215 value = pci->ptm[1].la; 216 break; 217 218 default: 219 printf("%s: invalid PCI internal register 0x%lx\n", __func__, 220 (unsigned long)offset); 221 value = 0; 222 } 223 224 return value; 225 } 226 227 static const MemoryRegionOps pci_reg_ops = { 228 .read = ppc4xx_pci_reg_read4, 229 .write = ppc4xx_pci_reg_write4, 230 .endianness = DEVICE_LITTLE_ENDIAN, 231 }; 232 233 static void ppc4xx_pci_reset(void *opaque) 234 { 235 struct PPC4xxPCIState *pci = opaque; 236 237 memset(pci->pmm, 0, sizeof(pci->pmm)); 238 memset(pci->ptm, 0, sizeof(pci->ptm)); 239 } 240 241 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This 242 * may need further refactoring for other boards. */ 243 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) 244 { 245 int slot = PCI_SLOT(pci_dev->devfn); 246 247 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot); 248 249 return slot - 1; 250 } 251 252 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) 253 { 254 qemu_irq *pci_irqs = opaque; 255 256 trace_ppc4xx_pci_set_irq(irq_num); 257 assert(irq_num >= 0); 258 qemu_set_irq(pci_irqs[irq_num], level); 259 } 260 261 static const VMStateDescription vmstate_pci_master_map = { 262 .name = "pci_master_map", 263 .version_id = 0, 264 .minimum_version_id = 0, 265 .fields = (VMStateField[]) { 266 VMSTATE_UINT32(la, struct PCIMasterMap), 267 VMSTATE_UINT32(ma, struct PCIMasterMap), 268 VMSTATE_UINT32(pcila, struct PCIMasterMap), 269 VMSTATE_UINT32(pciha, struct PCIMasterMap), 270 VMSTATE_END_OF_LIST() 271 } 272 }; 273 274 static const VMStateDescription vmstate_pci_target_map = { 275 .name = "pci_target_map", 276 .version_id = 0, 277 .minimum_version_id = 0, 278 .fields = (VMStateField[]) { 279 VMSTATE_UINT32(ms, struct PCITargetMap), 280 VMSTATE_UINT32(la, struct PCITargetMap), 281 VMSTATE_END_OF_LIST() 282 } 283 }; 284 285 static const VMStateDescription vmstate_ppc4xx_pci = { 286 .name = "ppc4xx_pci", 287 .version_id = 1, 288 .minimum_version_id = 1, 289 .fields = (VMStateField[]) { 290 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1, 291 vmstate_pci_master_map, 292 struct PCIMasterMap), 293 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1, 294 vmstate_pci_target_map, 295 struct PCITargetMap), 296 VMSTATE_END_OF_LIST() 297 } 298 }; 299 300 /* XXX Interrupt acknowledge cycles not supported. */ 301 static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp) 302 { 303 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 304 PPC4xxPCIState *s; 305 PCIHostState *h; 306 PCIBus *b; 307 int i; 308 309 h = PCI_HOST_BRIDGE(dev); 310 s = PPC4xx_PCI_HOST_BRIDGE(dev); 311 312 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 313 sysbus_init_irq(sbd, &s->irq[i]); 314 } 315 316 b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq, 317 ppc4xx_pci_map_irq, s->irq, get_system_memory(), 318 get_system_io(), 0, ARRAY_SIZE(s->irq), 319 TYPE_PCI_BUS); 320 h->bus = b; 321 322 pci_create_simple(b, 0, "ppc4xx-host-bridge"); 323 324 /* XXX split into 2 memory regions, one for config space, one for regs */ 325 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE); 326 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h, 327 "pci-conf-idx", 4); 328 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h, 329 "pci-conf-data", 4); 330 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s, 331 "pci.reg", PCI_REG_SIZE); 332 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); 333 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); 334 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem); 335 sysbus_init_mmio(sbd, &s->container); 336 qemu_register_reset(ppc4xx_pci_reset, s); 337 } 338 339 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data) 340 { 341 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 342 DeviceClass *dc = DEVICE_CLASS(klass); 343 344 dc->desc = "Host bridge"; 345 k->vendor_id = PCI_VENDOR_ID_IBM; 346 k->device_id = PCI_DEVICE_ID_IBM_440GX; 347 k->class_id = PCI_CLASS_BRIDGE_OTHER; 348 /* 349 * PCI-facing part of the host bridge, not usable without the 350 * host-facing part, which can't be device_add'ed, yet. 351 */ 352 dc->user_creatable = false; 353 } 354 355 static const TypeInfo ppc4xx_host_bridge_info = { 356 .name = "ppc4xx-host-bridge", 357 .parent = TYPE_PCI_DEVICE, 358 .instance_size = sizeof(PCIDevice), 359 .class_init = ppc4xx_host_bridge_class_init, 360 .interfaces = (InterfaceInfo[]) { 361 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 362 { }, 363 }, 364 }; 365 366 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) 367 { 368 DeviceClass *dc = DEVICE_CLASS(klass); 369 370 dc->realize = ppc4xx_pcihost_realize; 371 dc->vmsd = &vmstate_ppc4xx_pci; 372 } 373 374 static const TypeInfo ppc4xx_pcihost_info = { 375 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE, 376 .parent = TYPE_PCI_HOST_BRIDGE, 377 .instance_size = sizeof(PPC4xxPCIState), 378 .class_init = ppc4xx_pcihost_class_init, 379 }; 380 381 static void ppc4xx_pci_register_types(void) 382 { 383 type_register_static(&ppc4xx_pcihost_info); 384 type_register_static(&ppc4xx_host_bridge_info); 385 } 386 387 type_init(ppc4xx_pci_register_types) 388