1 /* 2 * QEMU PowerPC 4xx embedded processors shared devices emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "sysemu/reset.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/ppc/ppc4xx.h" 32 #include "hw/qdev-properties.h" 33 #include "qemu/log.h" 34 #include "exec/address-spaces.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "trace.h" 38 39 /*****************************************************************************/ 40 /* SDRAM controller */ 41 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; 42 struct ppc4xx_sdram_t { 43 uint32_t addr; 44 int nbanks; 45 MemoryRegion containers[4]; /* used for clipping */ 46 MemoryRegion *ram_memories; 47 hwaddr ram_bases[4]; 48 hwaddr ram_sizes[4]; 49 uint32_t besr0; 50 uint32_t besr1; 51 uint32_t bear; 52 uint32_t cfg; 53 uint32_t status; 54 uint32_t rtr; 55 uint32_t pmit; 56 uint32_t bcr[4]; 57 uint32_t tr; 58 uint32_t ecccfg; 59 uint32_t eccesr; 60 qemu_irq irq; 61 }; 62 63 enum { 64 SDRAM0_CFGADDR = 0x010, 65 SDRAM0_CFGDATA = 0x011, 66 }; 67 68 /* XXX: TOFIX: some patches have made this code become inconsistent: 69 * there are type inconsistencies, mixing hwaddr, target_ulong 70 * and uint32_t 71 */ 72 static uint32_t sdram_bcr (hwaddr ram_base, 73 hwaddr ram_size) 74 { 75 uint32_t bcr; 76 77 switch (ram_size) { 78 case 4 * MiB: 79 bcr = 0x00000000; 80 break; 81 case 8 * MiB: 82 bcr = 0x00020000; 83 break; 84 case 16 * MiB: 85 bcr = 0x00040000; 86 break; 87 case 32 * MiB: 88 bcr = 0x00060000; 89 break; 90 case 64 * MiB: 91 bcr = 0x00080000; 92 break; 93 case 128 * MiB: 94 bcr = 0x000A0000; 95 break; 96 case 256 * MiB: 97 bcr = 0x000C0000; 98 break; 99 default: 100 qemu_log_mask(LOG_GUEST_ERROR, 101 "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__, 102 ram_size); 103 return 0x00000000; 104 } 105 bcr |= ram_base & 0xFF800000; 106 bcr |= 1; 107 108 return bcr; 109 } 110 111 static inline hwaddr sdram_base(uint32_t bcr) 112 { 113 return bcr & 0xFF800000; 114 } 115 116 static target_ulong sdram_size (uint32_t bcr) 117 { 118 target_ulong size; 119 int sh; 120 121 sh = (bcr >> 17) & 0x7; 122 if (sh == 7) 123 size = -1; 124 else 125 size = (4 * MiB) << sh; 126 127 return size; 128 } 129 130 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, 131 uint32_t bcr, int enabled) 132 { 133 if (sdram->bcr[i] & 0x00000001) { 134 /* Unmap RAM */ 135 trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]), 136 sdram_size(sdram->bcr[i])); 137 memory_region_del_subregion(get_system_memory(), 138 &sdram->containers[i]); 139 memory_region_del_subregion(&sdram->containers[i], 140 &sdram->ram_memories[i]); 141 object_unparent(OBJECT(&sdram->containers[i])); 142 } 143 sdram->bcr[i] = bcr & 0xFFDEE001; 144 if (enabled && (bcr & 0x00000001)) { 145 trace_ppc4xx_sdram_unmap(sdram_base(bcr), sdram_size(bcr)); 146 memory_region_init(&sdram->containers[i], NULL, "sdram-containers", 147 sdram_size(bcr)); 148 memory_region_add_subregion(&sdram->containers[i], 0, 149 &sdram->ram_memories[i]); 150 memory_region_add_subregion(get_system_memory(), 151 sdram_base(bcr), 152 &sdram->containers[i]); 153 } 154 } 155 156 static void sdram_map_bcr (ppc4xx_sdram_t *sdram) 157 { 158 int i; 159 160 for (i = 0; i < sdram->nbanks; i++) { 161 if (sdram->ram_sizes[i] != 0) { 162 sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i], 163 sdram->ram_sizes[i]), 1); 164 } else { 165 sdram_set_bcr(sdram, i, 0x00000000, 0); 166 } 167 } 168 } 169 170 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) 171 { 172 int i; 173 174 for (i = 0; i < sdram->nbanks; i++) { 175 trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]), 176 sdram_size(sdram->bcr[i])); 177 memory_region_del_subregion(get_system_memory(), 178 &sdram->ram_memories[i]); 179 } 180 } 181 182 static uint32_t dcr_read_sdram (void *opaque, int dcrn) 183 { 184 ppc4xx_sdram_t *sdram; 185 uint32_t ret; 186 187 sdram = opaque; 188 switch (dcrn) { 189 case SDRAM0_CFGADDR: 190 ret = sdram->addr; 191 break; 192 case SDRAM0_CFGDATA: 193 switch (sdram->addr) { 194 case 0x00: /* SDRAM_BESR0 */ 195 ret = sdram->besr0; 196 break; 197 case 0x08: /* SDRAM_BESR1 */ 198 ret = sdram->besr1; 199 break; 200 case 0x10: /* SDRAM_BEAR */ 201 ret = sdram->bear; 202 break; 203 case 0x20: /* SDRAM_CFG */ 204 ret = sdram->cfg; 205 break; 206 case 0x24: /* SDRAM_STATUS */ 207 ret = sdram->status; 208 break; 209 case 0x30: /* SDRAM_RTR */ 210 ret = sdram->rtr; 211 break; 212 case 0x34: /* SDRAM_PMIT */ 213 ret = sdram->pmit; 214 break; 215 case 0x40: /* SDRAM_B0CR */ 216 ret = sdram->bcr[0]; 217 break; 218 case 0x44: /* SDRAM_B1CR */ 219 ret = sdram->bcr[1]; 220 break; 221 case 0x48: /* SDRAM_B2CR */ 222 ret = sdram->bcr[2]; 223 break; 224 case 0x4C: /* SDRAM_B3CR */ 225 ret = sdram->bcr[3]; 226 break; 227 case 0x80: /* SDRAM_TR */ 228 ret = -1; /* ? */ 229 break; 230 case 0x94: /* SDRAM_ECCCFG */ 231 ret = sdram->ecccfg; 232 break; 233 case 0x98: /* SDRAM_ECCESR */ 234 ret = sdram->eccesr; 235 break; 236 default: /* Error */ 237 ret = -1; 238 break; 239 } 240 break; 241 default: 242 /* Avoid gcc warning */ 243 ret = 0x00000000; 244 break; 245 } 246 247 return ret; 248 } 249 250 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) 251 { 252 ppc4xx_sdram_t *sdram; 253 254 sdram = opaque; 255 switch (dcrn) { 256 case SDRAM0_CFGADDR: 257 sdram->addr = val; 258 break; 259 case SDRAM0_CFGDATA: 260 switch (sdram->addr) { 261 case 0x00: /* SDRAM_BESR0 */ 262 sdram->besr0 &= ~val; 263 break; 264 case 0x08: /* SDRAM_BESR1 */ 265 sdram->besr1 &= ~val; 266 break; 267 case 0x10: /* SDRAM_BEAR */ 268 sdram->bear = val; 269 break; 270 case 0x20: /* SDRAM_CFG */ 271 val &= 0xFFE00000; 272 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { 273 trace_ppc4xx_sdram_enable("enable"); 274 /* validate all RAM mappings */ 275 sdram_map_bcr(sdram); 276 sdram->status &= ~0x80000000; 277 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { 278 trace_ppc4xx_sdram_enable("disable"); 279 /* invalidate all RAM mappings */ 280 sdram_unmap_bcr(sdram); 281 sdram->status |= 0x80000000; 282 } 283 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) 284 sdram->status |= 0x40000000; 285 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) 286 sdram->status &= ~0x40000000; 287 sdram->cfg = val; 288 break; 289 case 0x24: /* SDRAM_STATUS */ 290 /* Read-only register */ 291 break; 292 case 0x30: /* SDRAM_RTR */ 293 sdram->rtr = val & 0x3FF80000; 294 break; 295 case 0x34: /* SDRAM_PMIT */ 296 sdram->pmit = (val & 0xF8000000) | 0x07C00000; 297 break; 298 case 0x40: /* SDRAM_B0CR */ 299 sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); 300 break; 301 case 0x44: /* SDRAM_B1CR */ 302 sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); 303 break; 304 case 0x48: /* SDRAM_B2CR */ 305 sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); 306 break; 307 case 0x4C: /* SDRAM_B3CR */ 308 sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); 309 break; 310 case 0x80: /* SDRAM_TR */ 311 sdram->tr = val & 0x018FC01F; 312 break; 313 case 0x94: /* SDRAM_ECCCFG */ 314 sdram->ecccfg = val & 0x00F00000; 315 break; 316 case 0x98: /* SDRAM_ECCESR */ 317 val &= 0xFFF0F000; 318 if (sdram->eccesr == 0 && val != 0) 319 qemu_irq_raise(sdram->irq); 320 else if (sdram->eccesr != 0 && val == 0) 321 qemu_irq_lower(sdram->irq); 322 sdram->eccesr = val; 323 break; 324 default: /* Error */ 325 break; 326 } 327 break; 328 } 329 } 330 331 static void sdram_reset (void *opaque) 332 { 333 ppc4xx_sdram_t *sdram; 334 335 sdram = opaque; 336 sdram->addr = 0x00000000; 337 sdram->bear = 0x00000000; 338 sdram->besr0 = 0x00000000; /* No error */ 339 sdram->besr1 = 0x00000000; /* No error */ 340 sdram->cfg = 0x00000000; 341 sdram->ecccfg = 0x00000000; /* No ECC */ 342 sdram->eccesr = 0x00000000; /* No error */ 343 sdram->pmit = 0x07C00000; 344 sdram->rtr = 0x05F00000; 345 sdram->tr = 0x00854009; 346 /* We pre-initialize RAM banks */ 347 sdram->status = 0x00000000; 348 sdram->cfg = 0x00800000; 349 } 350 351 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, 352 MemoryRegion *ram_memories, 353 hwaddr *ram_bases, 354 hwaddr *ram_sizes, 355 int do_init) 356 { 357 ppc4xx_sdram_t *sdram; 358 359 sdram = g_new0(ppc4xx_sdram_t, 1); 360 sdram->irq = irq; 361 sdram->nbanks = nbanks; 362 sdram->ram_memories = ram_memories; 363 memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr)); 364 memcpy(sdram->ram_bases, ram_bases, 365 nbanks * sizeof(hwaddr)); 366 memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr)); 367 memcpy(sdram->ram_sizes, ram_sizes, 368 nbanks * sizeof(hwaddr)); 369 qemu_register_reset(&sdram_reset, sdram); 370 ppc_dcr_register(env, SDRAM0_CFGADDR, 371 sdram, &dcr_read_sdram, &dcr_write_sdram); 372 ppc_dcr_register(env, SDRAM0_CFGDATA, 373 sdram, &dcr_read_sdram, &dcr_write_sdram); 374 if (do_init) 375 sdram_map_bcr(sdram); 376 } 377 378 /* 379 * Split RAM between SDRAM banks. 380 * 381 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] 382 * and must be 0-terminated. 383 * 384 * The 4xx SDRAM controller supports a small number of banks, and each bank 385 * must be one of a small set of sizes. The number of banks and the supported 386 * sizes varies by SoC. 387 */ 388 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 389 MemoryRegion ram_memories[], 390 hwaddr ram_bases[], hwaddr ram_sizes[], 391 const ram_addr_t sdram_bank_sizes[]) 392 { 393 ram_addr_t size_left = memory_region_size(ram); 394 ram_addr_t base = 0; 395 ram_addr_t bank_size; 396 int i; 397 int j; 398 399 for (i = 0; i < nr_banks; i++) { 400 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 401 bank_size = sdram_bank_sizes[j]; 402 if (bank_size <= size_left) { 403 char name[32]; 404 405 ram_bases[i] = base; 406 ram_sizes[i] = bank_size; 407 base += bank_size; 408 size_left -= bank_size; 409 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 410 memory_region_init_alias(&ram_memories[i], NULL, name, ram, 411 ram_bases[i], ram_sizes[i]); 412 break; 413 } 414 } 415 if (!size_left) { 416 /* No need to use the remaining banks. */ 417 break; 418 } 419 } 420 421 if (size_left) { 422 ram_addr_t used_size = memory_region_size(ram) - size_left; 423 GString *s = g_string_new(NULL); 424 425 for (i = 0; sdram_bank_sizes[i]; i++) { 426 g_string_append_printf(s, "%" PRIi64 "%s", 427 sdram_bank_sizes[i] / MiB, 428 sdram_bank_sizes[i + 1] ? ", " : ""); 429 } 430 error_report("at most %d bank%s of %s MiB each supported", 431 nr_banks, nr_banks == 1 ? "" : "s", s->str); 432 error_printf("Possible valid RAM size: %" PRIi64 " MiB \n", 433 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); 434 435 g_string_free(s, true); 436 exit(EXIT_FAILURE); 437 } 438 } 439 440 /*****************************************************************************/ 441 /* MAL */ 442 443 enum { 444 MAL0_CFG = 0x180, 445 MAL0_ESR = 0x181, 446 MAL0_IER = 0x182, 447 MAL0_TXCASR = 0x184, 448 MAL0_TXCARR = 0x185, 449 MAL0_TXEOBISR = 0x186, 450 MAL0_TXDEIR = 0x187, 451 MAL0_RXCASR = 0x190, 452 MAL0_RXCARR = 0x191, 453 MAL0_RXEOBISR = 0x192, 454 MAL0_RXDEIR = 0x193, 455 MAL0_TXCTP0R = 0x1A0, 456 MAL0_RXCTP0R = 0x1C0, 457 MAL0_RCBS0 = 0x1E0, 458 MAL0_RCBS1 = 0x1E1, 459 }; 460 461 static void ppc4xx_mal_reset(DeviceState *dev) 462 { 463 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 464 465 mal->cfg = 0x0007C000; 466 mal->esr = 0x00000000; 467 mal->ier = 0x00000000; 468 mal->rxcasr = 0x00000000; 469 mal->rxdeir = 0x00000000; 470 mal->rxeobisr = 0x00000000; 471 mal->txcasr = 0x00000000; 472 mal->txdeir = 0x00000000; 473 mal->txeobisr = 0x00000000; 474 } 475 476 static uint32_t dcr_read_mal(void *opaque, int dcrn) 477 { 478 Ppc4xxMalState *mal = opaque; 479 uint32_t ret; 480 481 switch (dcrn) { 482 case MAL0_CFG: 483 ret = mal->cfg; 484 break; 485 case MAL0_ESR: 486 ret = mal->esr; 487 break; 488 case MAL0_IER: 489 ret = mal->ier; 490 break; 491 case MAL0_TXCASR: 492 ret = mal->txcasr; 493 break; 494 case MAL0_TXCARR: 495 ret = mal->txcarr; 496 break; 497 case MAL0_TXEOBISR: 498 ret = mal->txeobisr; 499 break; 500 case MAL0_TXDEIR: 501 ret = mal->txdeir; 502 break; 503 case MAL0_RXCASR: 504 ret = mal->rxcasr; 505 break; 506 case MAL0_RXCARR: 507 ret = mal->rxcarr; 508 break; 509 case MAL0_RXEOBISR: 510 ret = mal->rxeobisr; 511 break; 512 case MAL0_RXDEIR: 513 ret = mal->rxdeir; 514 break; 515 default: 516 ret = 0; 517 break; 518 } 519 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 520 ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; 521 } 522 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 523 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; 524 } 525 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 526 ret = mal->rcbs[dcrn - MAL0_RCBS0]; 527 } 528 529 return ret; 530 } 531 532 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) 533 { 534 Ppc4xxMalState *mal = opaque; 535 536 switch (dcrn) { 537 case MAL0_CFG: 538 if (val & 0x80000000) { 539 ppc4xx_mal_reset(DEVICE(mal)); 540 } 541 mal->cfg = val & 0x00FFC087; 542 break; 543 case MAL0_ESR: 544 /* Read/clear */ 545 mal->esr &= ~val; 546 break; 547 case MAL0_IER: 548 mal->ier = val & 0x0000001F; 549 break; 550 case MAL0_TXCASR: 551 mal->txcasr = val & 0xF0000000; 552 break; 553 case MAL0_TXCARR: 554 mal->txcarr = val & 0xF0000000; 555 break; 556 case MAL0_TXEOBISR: 557 /* Read/clear */ 558 mal->txeobisr &= ~val; 559 break; 560 case MAL0_TXDEIR: 561 /* Read/clear */ 562 mal->txdeir &= ~val; 563 break; 564 case MAL0_RXCASR: 565 mal->rxcasr = val & 0xC0000000; 566 break; 567 case MAL0_RXCARR: 568 mal->rxcarr = val & 0xC0000000; 569 break; 570 case MAL0_RXEOBISR: 571 /* Read/clear */ 572 mal->rxeobisr &= ~val; 573 break; 574 case MAL0_RXDEIR: 575 /* Read/clear */ 576 mal->rxdeir &= ~val; 577 break; 578 } 579 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 580 mal->txctpr[dcrn - MAL0_TXCTP0R] = val; 581 } 582 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 583 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; 584 } 585 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 586 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; 587 } 588 } 589 590 static void ppc4xx_mal_realize(DeviceState *dev, Error **errp) 591 { 592 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 593 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 594 int i; 595 596 if (mal->txcnum > 32 || mal->rxcnum > 32) { 597 error_setg(errp, "invalid TXC/RXC number"); 598 return; 599 } 600 601 mal->txctpr = g_new0(uint32_t, mal->txcnum); 602 mal->rxctpr = g_new0(uint32_t, mal->rxcnum); 603 mal->rcbs = g_new0(uint32_t, mal->rxcnum); 604 605 for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) { 606 sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]); 607 } 608 609 ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); 610 ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal); 611 ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal); 612 ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal); 613 ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal); 614 ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 615 ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 616 ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal); 617 ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal); 618 ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 619 ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 620 for (i = 0; i < mal->txcnum; i++) { 621 ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i, 622 mal, &dcr_read_mal, &dcr_write_mal); 623 } 624 for (i = 0; i < mal->rxcnum; i++) { 625 ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i, 626 mal, &dcr_read_mal, &dcr_write_mal); 627 } 628 for (i = 0; i < mal->rxcnum; i++) { 629 ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i, 630 mal, &dcr_read_mal, &dcr_write_mal); 631 } 632 } 633 634 static void ppc4xx_mal_finalize(Object *obj) 635 { 636 Ppc4xxMalState *mal = PPC4xx_MAL(obj); 637 638 g_free(mal->rcbs); 639 g_free(mal->rxctpr); 640 g_free(mal->txctpr); 641 } 642 643 static Property ppc4xx_mal_properties[] = { 644 DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), 645 DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), 646 DEFINE_PROP_END_OF_LIST(), 647 }; 648 649 static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) 650 { 651 DeviceClass *dc = DEVICE_CLASS(oc); 652 653 dc->realize = ppc4xx_mal_realize; 654 dc->reset = ppc4xx_mal_reset; 655 /* Reason: only works as function of a ppc4xx SoC */ 656 dc->user_creatable = false; 657 device_class_set_props(dc, ppc4xx_mal_properties); 658 } 659 660 /*****************************************************************************/ 661 /* Peripheral local bus arbitrer */ 662 enum { 663 PLB3A0_ACR = 0x077, 664 PLB4A0_ACR = 0x081, 665 PLB0_BESR = 0x084, 666 PLB0_BEAR = 0x086, 667 PLB0_ACR = 0x087, 668 PLB4A1_ACR = 0x089, 669 }; 670 671 static uint32_t dcr_read_plb(void *opaque, int dcrn) 672 { 673 Ppc4xxPlbState *plb = opaque; 674 uint32_t ret; 675 676 switch (dcrn) { 677 case PLB0_ACR: 678 ret = plb->acr; 679 break; 680 case PLB0_BEAR: 681 ret = plb->bear; 682 break; 683 case PLB0_BESR: 684 ret = plb->besr; 685 break; 686 default: 687 /* Avoid gcc warning */ 688 ret = 0; 689 break; 690 } 691 692 return ret; 693 } 694 695 static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) 696 { 697 Ppc4xxPlbState *plb = opaque; 698 699 switch (dcrn) { 700 case PLB0_ACR: 701 /* 702 * We don't care about the actual parameters written as 703 * we don't manage any priorities on the bus 704 */ 705 plb->acr = val & 0xF8000000; 706 break; 707 case PLB0_BEAR: 708 /* Read only */ 709 break; 710 case PLB0_BESR: 711 /* Write-clear */ 712 plb->besr &= ~val; 713 break; 714 } 715 } 716 717 static void ppc405_plb_reset(DeviceState *dev) 718 { 719 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 720 721 plb->acr = 0x00000000; 722 plb->bear = 0x00000000; 723 plb->besr = 0x00000000; 724 } 725 726 static void ppc405_plb_realize(DeviceState *dev, Error **errp) 727 { 728 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 729 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 730 731 ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 732 ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 733 ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 734 ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 735 ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 736 ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 737 } 738 739 static void ppc405_plb_class_init(ObjectClass *oc, void *data) 740 { 741 DeviceClass *dc = DEVICE_CLASS(oc); 742 743 dc->realize = ppc405_plb_realize; 744 dc->reset = ppc405_plb_reset; 745 /* Reason: only works as function of a ppc4xx SoC */ 746 dc->user_creatable = false; 747 } 748 749 /*****************************************************************************/ 750 /* Peripheral controller */ 751 enum { 752 EBC0_CFGADDR = 0x012, 753 EBC0_CFGDATA = 0x013, 754 }; 755 756 static uint32_t dcr_read_ebc(void *opaque, int dcrn) 757 { 758 Ppc4xxEbcState *ebc = opaque; 759 uint32_t ret; 760 761 switch (dcrn) { 762 case EBC0_CFGADDR: 763 ret = ebc->addr; 764 break; 765 case EBC0_CFGDATA: 766 switch (ebc->addr) { 767 case 0x00: /* B0CR */ 768 ret = ebc->bcr[0]; 769 break; 770 case 0x01: /* B1CR */ 771 ret = ebc->bcr[1]; 772 break; 773 case 0x02: /* B2CR */ 774 ret = ebc->bcr[2]; 775 break; 776 case 0x03: /* B3CR */ 777 ret = ebc->bcr[3]; 778 break; 779 case 0x04: /* B4CR */ 780 ret = ebc->bcr[4]; 781 break; 782 case 0x05: /* B5CR */ 783 ret = ebc->bcr[5]; 784 break; 785 case 0x06: /* B6CR */ 786 ret = ebc->bcr[6]; 787 break; 788 case 0x07: /* B7CR */ 789 ret = ebc->bcr[7]; 790 break; 791 case 0x10: /* B0AP */ 792 ret = ebc->bap[0]; 793 break; 794 case 0x11: /* B1AP */ 795 ret = ebc->bap[1]; 796 break; 797 case 0x12: /* B2AP */ 798 ret = ebc->bap[2]; 799 break; 800 case 0x13: /* B3AP */ 801 ret = ebc->bap[3]; 802 break; 803 case 0x14: /* B4AP */ 804 ret = ebc->bap[4]; 805 break; 806 case 0x15: /* B5AP */ 807 ret = ebc->bap[5]; 808 break; 809 case 0x16: /* B6AP */ 810 ret = ebc->bap[6]; 811 break; 812 case 0x17: /* B7AP */ 813 ret = ebc->bap[7]; 814 break; 815 case 0x20: /* BEAR */ 816 ret = ebc->bear; 817 break; 818 case 0x21: /* BESR0 */ 819 ret = ebc->besr0; 820 break; 821 case 0x22: /* BESR1 */ 822 ret = ebc->besr1; 823 break; 824 case 0x23: /* CFG */ 825 ret = ebc->cfg; 826 break; 827 default: 828 ret = 0x00000000; 829 break; 830 } 831 break; 832 default: 833 ret = 0x00000000; 834 break; 835 } 836 837 return ret; 838 } 839 840 static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) 841 { 842 Ppc4xxEbcState *ebc = opaque; 843 844 switch (dcrn) { 845 case EBC0_CFGADDR: 846 ebc->addr = val; 847 break; 848 case EBC0_CFGDATA: 849 switch (ebc->addr) { 850 case 0x00: /* B0CR */ 851 break; 852 case 0x01: /* B1CR */ 853 break; 854 case 0x02: /* B2CR */ 855 break; 856 case 0x03: /* B3CR */ 857 break; 858 case 0x04: /* B4CR */ 859 break; 860 case 0x05: /* B5CR */ 861 break; 862 case 0x06: /* B6CR */ 863 break; 864 case 0x07: /* B7CR */ 865 break; 866 case 0x10: /* B0AP */ 867 break; 868 case 0x11: /* B1AP */ 869 break; 870 case 0x12: /* B2AP */ 871 break; 872 case 0x13: /* B3AP */ 873 break; 874 case 0x14: /* B4AP */ 875 break; 876 case 0x15: /* B5AP */ 877 break; 878 case 0x16: /* B6AP */ 879 break; 880 case 0x17: /* B7AP */ 881 break; 882 case 0x20: /* BEAR */ 883 break; 884 case 0x21: /* BESR0 */ 885 break; 886 case 0x22: /* BESR1 */ 887 break; 888 case 0x23: /* CFG */ 889 break; 890 default: 891 break; 892 } 893 break; 894 default: 895 break; 896 } 897 } 898 899 static void ppc405_ebc_reset(DeviceState *dev) 900 { 901 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 902 int i; 903 904 ebc->addr = 0x00000000; 905 ebc->bap[0] = 0x7F8FFE80; 906 ebc->bcr[0] = 0xFFE28000; 907 for (i = 0; i < 8; i++) { 908 ebc->bap[i] = 0x00000000; 909 ebc->bcr[i] = 0x00000000; 910 } 911 ebc->besr0 = 0x00000000; 912 ebc->besr1 = 0x00000000; 913 ebc->cfg = 0x80400000; 914 } 915 916 static void ppc405_ebc_realize(DeviceState *dev, Error **errp) 917 { 918 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 919 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 920 921 ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); 922 ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc); 923 } 924 925 static void ppc405_ebc_class_init(ObjectClass *oc, void *data) 926 { 927 DeviceClass *dc = DEVICE_CLASS(oc); 928 929 dc->realize = ppc405_ebc_realize; 930 dc->reset = ppc405_ebc_reset; 931 /* Reason: only works as function of a ppc4xx SoC */ 932 dc->user_creatable = false; 933 } 934 935 /* PPC4xx_DCR_DEVICE */ 936 937 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 938 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 939 { 940 assert(dev->cpu); 941 ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write); 942 } 943 944 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 945 Error **errp) 946 { 947 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 948 return sysbus_realize(SYS_BUS_DEVICE(dev), errp); 949 } 950 951 static Property ppc4xx_dcr_properties[] = { 952 DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU, 953 PowerPCCPU *), 954 DEFINE_PROP_END_OF_LIST(), 955 }; 956 957 static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data) 958 { 959 DeviceClass *dc = DEVICE_CLASS(oc); 960 961 device_class_set_props(dc, ppc4xx_dcr_properties); 962 } 963 964 static const TypeInfo ppc4xx_types[] = { 965 { 966 .name = TYPE_PPC4xx_MAL, 967 .parent = TYPE_PPC4xx_DCR_DEVICE, 968 .instance_size = sizeof(Ppc4xxMalState), 969 .instance_finalize = ppc4xx_mal_finalize, 970 .class_init = ppc4xx_mal_class_init, 971 }, { 972 .name = TYPE_PPC4xx_PLB, 973 .parent = TYPE_PPC4xx_DCR_DEVICE, 974 .instance_size = sizeof(Ppc4xxPlbState), 975 .class_init = ppc405_plb_class_init, 976 }, { 977 .name = TYPE_PPC4xx_EBC, 978 .parent = TYPE_PPC4xx_DCR_DEVICE, 979 .instance_size = sizeof(Ppc4xxEbcState), 980 .class_init = ppc405_ebc_class_init, 981 }, { 982 .name = TYPE_PPC4xx_DCR_DEVICE, 983 .parent = TYPE_SYS_BUS_DEVICE, 984 .instance_size = sizeof(Ppc4xxDcrDeviceState), 985 .class_init = ppc4xx_dcr_class_init, 986 .abstract = true, 987 } 988 }; 989 990 DEFINE_TYPES(ppc4xx_types) 991