1 /* 2 * QEMU PowerPC 4xx embedded processors shared devices emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "sysemu/reset.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/ppc/ppc4xx.h" 32 #include "hw/qdev-properties.h" 33 #include "qemu/log.h" 34 #include "exec/address-spaces.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "trace.h" 38 39 /*****************************************************************************/ 40 /* SDRAM controller */ 41 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; 42 struct ppc4xx_sdram_t { 43 uint32_t addr; 44 int nbanks; 45 Ppc4xxSdramBank bank[4]; 46 uint32_t besr0; 47 uint32_t besr1; 48 uint32_t bear; 49 uint32_t cfg; 50 uint32_t status; 51 uint32_t rtr; 52 uint32_t pmit; 53 uint32_t tr; 54 uint32_t ecccfg; 55 uint32_t eccesr; 56 qemu_irq irq; 57 }; 58 59 enum { 60 SDRAM0_CFGADDR = 0x010, 61 SDRAM0_CFGDATA = 0x011, 62 }; 63 64 /* 65 * XXX: TOFIX: some patches have made this code become inconsistent: 66 * there are type inconsistencies, mixing hwaddr, target_ulong 67 * and uint32_t 68 */ 69 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) 70 { 71 uint32_t bcr; 72 73 switch (ram_size) { 74 case 4 * MiB: 75 bcr = 0x00000000; 76 break; 77 case 8 * MiB: 78 bcr = 0x00020000; 79 break; 80 case 16 * MiB: 81 bcr = 0x00040000; 82 break; 83 case 32 * MiB: 84 bcr = 0x00060000; 85 break; 86 case 64 * MiB: 87 bcr = 0x00080000; 88 break; 89 case 128 * MiB: 90 bcr = 0x000A0000; 91 break; 92 case 256 * MiB: 93 bcr = 0x000C0000; 94 break; 95 default: 96 qemu_log_mask(LOG_GUEST_ERROR, 97 "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__, 98 ram_size); 99 return 0x00000000; 100 } 101 bcr |= ram_base & 0xFF800000; 102 bcr |= 1; 103 104 return bcr; 105 } 106 107 static inline hwaddr sdram_base(uint32_t bcr) 108 { 109 return bcr & 0xFF800000; 110 } 111 112 static target_ulong sdram_size(uint32_t bcr) 113 { 114 target_ulong size; 115 int sh; 116 117 sh = (bcr >> 17) & 0x7; 118 if (sh == 7) { 119 size = -1; 120 } else { 121 size = (4 * MiB) << sh; 122 } 123 124 return size; 125 } 126 127 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, 128 uint32_t bcr, int enabled) 129 { 130 if (sdram->bank[i].bcr & 0x00000001) { 131 /* Unmap RAM */ 132 trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), 133 sdram_size(sdram->bank[i].bcr)); 134 memory_region_del_subregion(get_system_memory(), 135 &sdram->bank[i].container); 136 memory_region_del_subregion(&sdram->bank[i].container, 137 &sdram->bank[i].ram); 138 object_unparent(OBJECT(&sdram->bank[i].container)); 139 } 140 sdram->bank[i].bcr = bcr & 0xFFDEE001; 141 if (enabled && (bcr & 0x00000001)) { 142 trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); 143 memory_region_init(&sdram->bank[i].container, NULL, "sdram-container", 144 sdram_size(bcr)); 145 memory_region_add_subregion(&sdram->bank[i].container, 0, 146 &sdram->bank[i].ram); 147 memory_region_add_subregion(get_system_memory(), 148 sdram_base(bcr), 149 &sdram->bank[i].container); 150 } 151 } 152 153 static void sdram_map_bcr(ppc4xx_sdram_t *sdram) 154 { 155 int i; 156 157 for (i = 0; i < sdram->nbanks; i++) { 158 if (sdram->bank[i].size != 0) { 159 sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, 160 sdram->bank[i].size), 1); 161 } else { 162 sdram_set_bcr(sdram, i, 0x00000000, 0); 163 } 164 } 165 } 166 167 static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) 168 { 169 int i; 170 171 for (i = 0; i < sdram->nbanks; i++) { 172 trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), 173 sdram_size(sdram->bank[i].bcr)); 174 memory_region_del_subregion(get_system_memory(), 175 &sdram->bank[i].ram); 176 } 177 } 178 179 static uint32_t dcr_read_sdram(void *opaque, int dcrn) 180 { 181 ppc4xx_sdram_t *sdram; 182 uint32_t ret; 183 184 sdram = opaque; 185 switch (dcrn) { 186 case SDRAM0_CFGADDR: 187 ret = sdram->addr; 188 break; 189 case SDRAM0_CFGDATA: 190 switch (sdram->addr) { 191 case 0x00: /* SDRAM_BESR0 */ 192 ret = sdram->besr0; 193 break; 194 case 0x08: /* SDRAM_BESR1 */ 195 ret = sdram->besr1; 196 break; 197 case 0x10: /* SDRAM_BEAR */ 198 ret = sdram->bear; 199 break; 200 case 0x20: /* SDRAM_CFG */ 201 ret = sdram->cfg; 202 break; 203 case 0x24: /* SDRAM_STATUS */ 204 ret = sdram->status; 205 break; 206 case 0x30: /* SDRAM_RTR */ 207 ret = sdram->rtr; 208 break; 209 case 0x34: /* SDRAM_PMIT */ 210 ret = sdram->pmit; 211 break; 212 case 0x40: /* SDRAM_B0CR */ 213 ret = sdram->bank[0].bcr; 214 break; 215 case 0x44: /* SDRAM_B1CR */ 216 ret = sdram->bank[1].bcr; 217 break; 218 case 0x48: /* SDRAM_B2CR */ 219 ret = sdram->bank[2].bcr; 220 break; 221 case 0x4C: /* SDRAM_B3CR */ 222 ret = sdram->bank[3].bcr; 223 break; 224 case 0x80: /* SDRAM_TR */ 225 ret = -1; /* ? */ 226 break; 227 case 0x94: /* SDRAM_ECCCFG */ 228 ret = sdram->ecccfg; 229 break; 230 case 0x98: /* SDRAM_ECCESR */ 231 ret = sdram->eccesr; 232 break; 233 default: /* Error */ 234 ret = -1; 235 break; 236 } 237 break; 238 default: 239 /* Avoid gcc warning */ 240 ret = 0x00000000; 241 break; 242 } 243 244 return ret; 245 } 246 247 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) 248 { 249 ppc4xx_sdram_t *sdram; 250 251 sdram = opaque; 252 switch (dcrn) { 253 case SDRAM0_CFGADDR: 254 sdram->addr = val; 255 break; 256 case SDRAM0_CFGDATA: 257 switch (sdram->addr) { 258 case 0x00: /* SDRAM_BESR0 */ 259 sdram->besr0 &= ~val; 260 break; 261 case 0x08: /* SDRAM_BESR1 */ 262 sdram->besr1 &= ~val; 263 break; 264 case 0x10: /* SDRAM_BEAR */ 265 sdram->bear = val; 266 break; 267 case 0x20: /* SDRAM_CFG */ 268 val &= 0xFFE00000; 269 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { 270 trace_ppc4xx_sdram_enable("enable"); 271 /* validate all RAM mappings */ 272 sdram_map_bcr(sdram); 273 sdram->status &= ~0x80000000; 274 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { 275 trace_ppc4xx_sdram_enable("disable"); 276 /* invalidate all RAM mappings */ 277 sdram_unmap_bcr(sdram); 278 sdram->status |= 0x80000000; 279 } 280 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { 281 sdram->status |= 0x40000000; 282 } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { 283 sdram->status &= ~0x40000000; 284 } 285 sdram->cfg = val; 286 break; 287 case 0x24: /* SDRAM_STATUS */ 288 /* Read-only register */ 289 break; 290 case 0x30: /* SDRAM_RTR */ 291 sdram->rtr = val & 0x3FF80000; 292 break; 293 case 0x34: /* SDRAM_PMIT */ 294 sdram->pmit = (val & 0xF8000000) | 0x07C00000; 295 break; 296 case 0x40: /* SDRAM_B0CR */ 297 sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); 298 break; 299 case 0x44: /* SDRAM_B1CR */ 300 sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); 301 break; 302 case 0x48: /* SDRAM_B2CR */ 303 sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); 304 break; 305 case 0x4C: /* SDRAM_B3CR */ 306 sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); 307 break; 308 case 0x80: /* SDRAM_TR */ 309 sdram->tr = val & 0x018FC01F; 310 break; 311 case 0x94: /* SDRAM_ECCCFG */ 312 sdram->ecccfg = val & 0x00F00000; 313 break; 314 case 0x98: /* SDRAM_ECCESR */ 315 val &= 0xFFF0F000; 316 if (sdram->eccesr == 0 && val != 0) { 317 qemu_irq_raise(sdram->irq); 318 } else if (sdram->eccesr != 0 && val == 0) { 319 qemu_irq_lower(sdram->irq); 320 } 321 sdram->eccesr = val; 322 break; 323 default: /* Error */ 324 break; 325 } 326 break; 327 } 328 } 329 330 static void sdram_reset(void *opaque) 331 { 332 ppc4xx_sdram_t *sdram; 333 334 sdram = opaque; 335 sdram->addr = 0x00000000; 336 sdram->bear = 0x00000000; 337 sdram->besr0 = 0x00000000; /* No error */ 338 sdram->besr1 = 0x00000000; /* No error */ 339 sdram->cfg = 0x00000000; 340 sdram->ecccfg = 0x00000000; /* No ECC */ 341 sdram->eccesr = 0x00000000; /* No error */ 342 sdram->pmit = 0x07C00000; 343 sdram->rtr = 0x05F00000; 344 sdram->tr = 0x00854009; 345 /* We pre-initialize RAM banks */ 346 sdram->status = 0x00000000; 347 sdram->cfg = 0x00800000; 348 } 349 350 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, 351 Ppc4xxSdramBank *ram_banks) 352 { 353 ppc4xx_sdram_t *sdram; 354 int i; 355 356 sdram = g_new0(ppc4xx_sdram_t, 1); 357 sdram->irq = irq; 358 sdram->nbanks = nbanks; 359 for (i = 0; i < nbanks; i++) { 360 sdram->bank[i].ram = ram_banks[i].ram; 361 sdram->bank[i].base = ram_banks[i].base; 362 sdram->bank[i].size = ram_banks[i].size; 363 } 364 qemu_register_reset(&sdram_reset, sdram); 365 ppc_dcr_register(env, SDRAM0_CFGADDR, 366 sdram, &dcr_read_sdram, &dcr_write_sdram); 367 ppc_dcr_register(env, SDRAM0_CFGDATA, 368 sdram, &dcr_read_sdram, &dcr_write_sdram); 369 } 370 371 void ppc4xx_sdram_enable(CPUPPCState *env) 372 { 373 ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20); 374 ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000); 375 } 376 377 /* 378 * Split RAM between SDRAM banks. 379 * 380 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] 381 * and must be 0-terminated. 382 * 383 * The 4xx SDRAM controller supports a small number of banks, and each bank 384 * must be one of a small set of sizes. The number of banks and the supported 385 * sizes varies by SoC. 386 */ 387 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 388 Ppc4xxSdramBank ram_banks[], 389 const ram_addr_t sdram_bank_sizes[]) 390 { 391 ram_addr_t size_left = memory_region_size(ram); 392 ram_addr_t base = 0; 393 ram_addr_t bank_size; 394 int i; 395 int j; 396 397 for (i = 0; i < nr_banks; i++) { 398 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 399 bank_size = sdram_bank_sizes[j]; 400 if (bank_size <= size_left) { 401 char name[32]; 402 403 ram_banks[i].base = base; 404 ram_banks[i].size = bank_size; 405 base += bank_size; 406 size_left -= bank_size; 407 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 408 memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram, 409 ram_banks[i].base, ram_banks[i].size); 410 break; 411 } 412 } 413 if (!size_left) { 414 /* No need to use the remaining banks. */ 415 break; 416 } 417 } 418 419 if (size_left) { 420 ram_addr_t used_size = memory_region_size(ram) - size_left; 421 GString *s = g_string_new(NULL); 422 423 for (i = 0; sdram_bank_sizes[i]; i++) { 424 g_string_append_printf(s, "%" PRIi64 "%s", 425 sdram_bank_sizes[i] / MiB, 426 sdram_bank_sizes[i + 1] ? ", " : ""); 427 } 428 error_report("at most %d bank%s of %s MiB each supported", 429 nr_banks, nr_banks == 1 ? "" : "s", s->str); 430 error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", 431 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); 432 433 g_string_free(s, true); 434 exit(EXIT_FAILURE); 435 } 436 } 437 438 /*****************************************************************************/ 439 /* MAL */ 440 441 enum { 442 MAL0_CFG = 0x180, 443 MAL0_ESR = 0x181, 444 MAL0_IER = 0x182, 445 MAL0_TXCASR = 0x184, 446 MAL0_TXCARR = 0x185, 447 MAL0_TXEOBISR = 0x186, 448 MAL0_TXDEIR = 0x187, 449 MAL0_RXCASR = 0x190, 450 MAL0_RXCARR = 0x191, 451 MAL0_RXEOBISR = 0x192, 452 MAL0_RXDEIR = 0x193, 453 MAL0_TXCTP0R = 0x1A0, 454 MAL0_RXCTP0R = 0x1C0, 455 MAL0_RCBS0 = 0x1E0, 456 MAL0_RCBS1 = 0x1E1, 457 }; 458 459 static void ppc4xx_mal_reset(DeviceState *dev) 460 { 461 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 462 463 mal->cfg = 0x0007C000; 464 mal->esr = 0x00000000; 465 mal->ier = 0x00000000; 466 mal->rxcasr = 0x00000000; 467 mal->rxdeir = 0x00000000; 468 mal->rxeobisr = 0x00000000; 469 mal->txcasr = 0x00000000; 470 mal->txdeir = 0x00000000; 471 mal->txeobisr = 0x00000000; 472 } 473 474 static uint32_t dcr_read_mal(void *opaque, int dcrn) 475 { 476 Ppc4xxMalState *mal = opaque; 477 uint32_t ret; 478 479 switch (dcrn) { 480 case MAL0_CFG: 481 ret = mal->cfg; 482 break; 483 case MAL0_ESR: 484 ret = mal->esr; 485 break; 486 case MAL0_IER: 487 ret = mal->ier; 488 break; 489 case MAL0_TXCASR: 490 ret = mal->txcasr; 491 break; 492 case MAL0_TXCARR: 493 ret = mal->txcarr; 494 break; 495 case MAL0_TXEOBISR: 496 ret = mal->txeobisr; 497 break; 498 case MAL0_TXDEIR: 499 ret = mal->txdeir; 500 break; 501 case MAL0_RXCASR: 502 ret = mal->rxcasr; 503 break; 504 case MAL0_RXCARR: 505 ret = mal->rxcarr; 506 break; 507 case MAL0_RXEOBISR: 508 ret = mal->rxeobisr; 509 break; 510 case MAL0_RXDEIR: 511 ret = mal->rxdeir; 512 break; 513 default: 514 ret = 0; 515 break; 516 } 517 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 518 ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; 519 } 520 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 521 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; 522 } 523 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 524 ret = mal->rcbs[dcrn - MAL0_RCBS0]; 525 } 526 527 return ret; 528 } 529 530 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) 531 { 532 Ppc4xxMalState *mal = opaque; 533 534 switch (dcrn) { 535 case MAL0_CFG: 536 if (val & 0x80000000) { 537 ppc4xx_mal_reset(DEVICE(mal)); 538 } 539 mal->cfg = val & 0x00FFC087; 540 break; 541 case MAL0_ESR: 542 /* Read/clear */ 543 mal->esr &= ~val; 544 break; 545 case MAL0_IER: 546 mal->ier = val & 0x0000001F; 547 break; 548 case MAL0_TXCASR: 549 mal->txcasr = val & 0xF0000000; 550 break; 551 case MAL0_TXCARR: 552 mal->txcarr = val & 0xF0000000; 553 break; 554 case MAL0_TXEOBISR: 555 /* Read/clear */ 556 mal->txeobisr &= ~val; 557 break; 558 case MAL0_TXDEIR: 559 /* Read/clear */ 560 mal->txdeir &= ~val; 561 break; 562 case MAL0_RXCASR: 563 mal->rxcasr = val & 0xC0000000; 564 break; 565 case MAL0_RXCARR: 566 mal->rxcarr = val & 0xC0000000; 567 break; 568 case MAL0_RXEOBISR: 569 /* Read/clear */ 570 mal->rxeobisr &= ~val; 571 break; 572 case MAL0_RXDEIR: 573 /* Read/clear */ 574 mal->rxdeir &= ~val; 575 break; 576 } 577 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 578 mal->txctpr[dcrn - MAL0_TXCTP0R] = val; 579 } 580 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 581 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; 582 } 583 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 584 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; 585 } 586 } 587 588 static void ppc4xx_mal_realize(DeviceState *dev, Error **errp) 589 { 590 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 591 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 592 int i; 593 594 if (mal->txcnum > 32 || mal->rxcnum > 32) { 595 error_setg(errp, "invalid TXC/RXC number"); 596 return; 597 } 598 599 mal->txctpr = g_new0(uint32_t, mal->txcnum); 600 mal->rxctpr = g_new0(uint32_t, mal->rxcnum); 601 mal->rcbs = g_new0(uint32_t, mal->rxcnum); 602 603 for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) { 604 sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]); 605 } 606 607 ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); 608 ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal); 609 ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal); 610 ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal); 611 ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal); 612 ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 613 ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 614 ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal); 615 ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal); 616 ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 617 ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 618 for (i = 0; i < mal->txcnum; i++) { 619 ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i, 620 mal, &dcr_read_mal, &dcr_write_mal); 621 } 622 for (i = 0; i < mal->rxcnum; i++) { 623 ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i, 624 mal, &dcr_read_mal, &dcr_write_mal); 625 } 626 for (i = 0; i < mal->rxcnum; i++) { 627 ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i, 628 mal, &dcr_read_mal, &dcr_write_mal); 629 } 630 } 631 632 static void ppc4xx_mal_finalize(Object *obj) 633 { 634 Ppc4xxMalState *mal = PPC4xx_MAL(obj); 635 636 g_free(mal->rcbs); 637 g_free(mal->rxctpr); 638 g_free(mal->txctpr); 639 } 640 641 static Property ppc4xx_mal_properties[] = { 642 DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), 643 DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), 644 DEFINE_PROP_END_OF_LIST(), 645 }; 646 647 static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) 648 { 649 DeviceClass *dc = DEVICE_CLASS(oc); 650 651 dc->realize = ppc4xx_mal_realize; 652 dc->reset = ppc4xx_mal_reset; 653 /* Reason: only works as function of a ppc4xx SoC */ 654 dc->user_creatable = false; 655 device_class_set_props(dc, ppc4xx_mal_properties); 656 } 657 658 /*****************************************************************************/ 659 /* Peripheral local bus arbitrer */ 660 enum { 661 PLB3A0_ACR = 0x077, 662 PLB4A0_ACR = 0x081, 663 PLB0_BESR = 0x084, 664 PLB0_BEAR = 0x086, 665 PLB0_ACR = 0x087, 666 PLB4A1_ACR = 0x089, 667 }; 668 669 static uint32_t dcr_read_plb(void *opaque, int dcrn) 670 { 671 Ppc4xxPlbState *plb = opaque; 672 uint32_t ret; 673 674 switch (dcrn) { 675 case PLB0_ACR: 676 ret = plb->acr; 677 break; 678 case PLB0_BEAR: 679 ret = plb->bear; 680 break; 681 case PLB0_BESR: 682 ret = plb->besr; 683 break; 684 default: 685 /* Avoid gcc warning */ 686 ret = 0; 687 break; 688 } 689 690 return ret; 691 } 692 693 static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) 694 { 695 Ppc4xxPlbState *plb = opaque; 696 697 switch (dcrn) { 698 case PLB0_ACR: 699 /* 700 * We don't care about the actual parameters written as 701 * we don't manage any priorities on the bus 702 */ 703 plb->acr = val & 0xF8000000; 704 break; 705 case PLB0_BEAR: 706 /* Read only */ 707 break; 708 case PLB0_BESR: 709 /* Write-clear */ 710 plb->besr &= ~val; 711 break; 712 } 713 } 714 715 static void ppc405_plb_reset(DeviceState *dev) 716 { 717 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 718 719 plb->acr = 0x00000000; 720 plb->bear = 0x00000000; 721 plb->besr = 0x00000000; 722 } 723 724 static void ppc405_plb_realize(DeviceState *dev, Error **errp) 725 { 726 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 727 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 728 729 ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 730 ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 731 ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 732 ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 733 ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 734 ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 735 } 736 737 static void ppc405_plb_class_init(ObjectClass *oc, void *data) 738 { 739 DeviceClass *dc = DEVICE_CLASS(oc); 740 741 dc->realize = ppc405_plb_realize; 742 dc->reset = ppc405_plb_reset; 743 /* Reason: only works as function of a ppc4xx SoC */ 744 dc->user_creatable = false; 745 } 746 747 /*****************************************************************************/ 748 /* Peripheral controller */ 749 enum { 750 EBC0_CFGADDR = 0x012, 751 EBC0_CFGDATA = 0x013, 752 }; 753 754 static uint32_t dcr_read_ebc(void *opaque, int dcrn) 755 { 756 Ppc4xxEbcState *ebc = opaque; 757 uint32_t ret; 758 759 switch (dcrn) { 760 case EBC0_CFGADDR: 761 ret = ebc->addr; 762 break; 763 case EBC0_CFGDATA: 764 switch (ebc->addr) { 765 case 0x00: /* B0CR */ 766 ret = ebc->bcr[0]; 767 break; 768 case 0x01: /* B1CR */ 769 ret = ebc->bcr[1]; 770 break; 771 case 0x02: /* B2CR */ 772 ret = ebc->bcr[2]; 773 break; 774 case 0x03: /* B3CR */ 775 ret = ebc->bcr[3]; 776 break; 777 case 0x04: /* B4CR */ 778 ret = ebc->bcr[4]; 779 break; 780 case 0x05: /* B5CR */ 781 ret = ebc->bcr[5]; 782 break; 783 case 0x06: /* B6CR */ 784 ret = ebc->bcr[6]; 785 break; 786 case 0x07: /* B7CR */ 787 ret = ebc->bcr[7]; 788 break; 789 case 0x10: /* B0AP */ 790 ret = ebc->bap[0]; 791 break; 792 case 0x11: /* B1AP */ 793 ret = ebc->bap[1]; 794 break; 795 case 0x12: /* B2AP */ 796 ret = ebc->bap[2]; 797 break; 798 case 0x13: /* B3AP */ 799 ret = ebc->bap[3]; 800 break; 801 case 0x14: /* B4AP */ 802 ret = ebc->bap[4]; 803 break; 804 case 0x15: /* B5AP */ 805 ret = ebc->bap[5]; 806 break; 807 case 0x16: /* B6AP */ 808 ret = ebc->bap[6]; 809 break; 810 case 0x17: /* B7AP */ 811 ret = ebc->bap[7]; 812 break; 813 case 0x20: /* BEAR */ 814 ret = ebc->bear; 815 break; 816 case 0x21: /* BESR0 */ 817 ret = ebc->besr0; 818 break; 819 case 0x22: /* BESR1 */ 820 ret = ebc->besr1; 821 break; 822 case 0x23: /* CFG */ 823 ret = ebc->cfg; 824 break; 825 default: 826 ret = 0x00000000; 827 break; 828 } 829 break; 830 default: 831 ret = 0x00000000; 832 break; 833 } 834 835 return ret; 836 } 837 838 static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) 839 { 840 Ppc4xxEbcState *ebc = opaque; 841 842 switch (dcrn) { 843 case EBC0_CFGADDR: 844 ebc->addr = val; 845 break; 846 case EBC0_CFGDATA: 847 switch (ebc->addr) { 848 case 0x00: /* B0CR */ 849 break; 850 case 0x01: /* B1CR */ 851 break; 852 case 0x02: /* B2CR */ 853 break; 854 case 0x03: /* B3CR */ 855 break; 856 case 0x04: /* B4CR */ 857 break; 858 case 0x05: /* B5CR */ 859 break; 860 case 0x06: /* B6CR */ 861 break; 862 case 0x07: /* B7CR */ 863 break; 864 case 0x10: /* B0AP */ 865 break; 866 case 0x11: /* B1AP */ 867 break; 868 case 0x12: /* B2AP */ 869 break; 870 case 0x13: /* B3AP */ 871 break; 872 case 0x14: /* B4AP */ 873 break; 874 case 0x15: /* B5AP */ 875 break; 876 case 0x16: /* B6AP */ 877 break; 878 case 0x17: /* B7AP */ 879 break; 880 case 0x20: /* BEAR */ 881 break; 882 case 0x21: /* BESR0 */ 883 break; 884 case 0x22: /* BESR1 */ 885 break; 886 case 0x23: /* CFG */ 887 break; 888 default: 889 break; 890 } 891 break; 892 default: 893 break; 894 } 895 } 896 897 static void ppc405_ebc_reset(DeviceState *dev) 898 { 899 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 900 int i; 901 902 ebc->addr = 0x00000000; 903 ebc->bap[0] = 0x7F8FFE80; 904 ebc->bcr[0] = 0xFFE28000; 905 for (i = 0; i < 8; i++) { 906 ebc->bap[i] = 0x00000000; 907 ebc->bcr[i] = 0x00000000; 908 } 909 ebc->besr0 = 0x00000000; 910 ebc->besr1 = 0x00000000; 911 ebc->cfg = 0x80400000; 912 } 913 914 static void ppc405_ebc_realize(DeviceState *dev, Error **errp) 915 { 916 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 917 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 918 919 ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); 920 ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc); 921 } 922 923 static void ppc405_ebc_class_init(ObjectClass *oc, void *data) 924 { 925 DeviceClass *dc = DEVICE_CLASS(oc); 926 927 dc->realize = ppc405_ebc_realize; 928 dc->reset = ppc405_ebc_reset; 929 /* Reason: only works as function of a ppc4xx SoC */ 930 dc->user_creatable = false; 931 } 932 933 /* PPC4xx_DCR_DEVICE */ 934 935 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 936 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 937 { 938 assert(dev->cpu); 939 ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write); 940 } 941 942 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 943 Error **errp) 944 { 945 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 946 return sysbus_realize(SYS_BUS_DEVICE(dev), errp); 947 } 948 949 static Property ppc4xx_dcr_properties[] = { 950 DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU, 951 PowerPCCPU *), 952 DEFINE_PROP_END_OF_LIST(), 953 }; 954 955 static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data) 956 { 957 DeviceClass *dc = DEVICE_CLASS(oc); 958 959 device_class_set_props(dc, ppc4xx_dcr_properties); 960 } 961 962 static const TypeInfo ppc4xx_types[] = { 963 { 964 .name = TYPE_PPC4xx_MAL, 965 .parent = TYPE_PPC4xx_DCR_DEVICE, 966 .instance_size = sizeof(Ppc4xxMalState), 967 .instance_finalize = ppc4xx_mal_finalize, 968 .class_init = ppc4xx_mal_class_init, 969 }, { 970 .name = TYPE_PPC4xx_PLB, 971 .parent = TYPE_PPC4xx_DCR_DEVICE, 972 .instance_size = sizeof(Ppc4xxPlbState), 973 .class_init = ppc405_plb_class_init, 974 }, { 975 .name = TYPE_PPC4xx_EBC, 976 .parent = TYPE_PPC4xx_DCR_DEVICE, 977 .instance_size = sizeof(Ppc4xxEbcState), 978 .class_init = ppc405_ebc_class_init, 979 }, { 980 .name = TYPE_PPC4xx_DCR_DEVICE, 981 .parent = TYPE_SYS_BUS_DEVICE, 982 .instance_size = sizeof(Ppc4xxDcrDeviceState), 983 .class_init = ppc4xx_dcr_class_init, 984 .abstract = true, 985 } 986 }; 987 988 DEFINE_TYPES(ppc4xx_types) 989