1 /* 2 * QEMU PowerPC 4xx embedded processors shared devices emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/ppc/ppc4xx.h" 27 #include "hw/boards.h" 28 #include "qemu/log.h" 29 #include "exec/address-spaces.h" 30 31 #define DEBUG_UIC 32 33 34 #ifdef DEBUG_UIC 35 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 36 #else 37 # define LOG_UIC(...) do { } while (0) 38 #endif 39 40 static void ppc4xx_reset(void *opaque) 41 { 42 PowerPCCPU *cpu = opaque; 43 44 cpu_reset(CPU(cpu)); 45 } 46 47 /*****************************************************************************/ 48 /* Generic PowerPC 4xx processor instantiation */ 49 PowerPCCPU *ppc4xx_init(const char *cpu_model, 50 clk_setup_t *cpu_clk, clk_setup_t *tb_clk, 51 uint32_t sysclk) 52 { 53 PowerPCCPU *cpu; 54 CPUPPCState *env; 55 56 /* init CPUs */ 57 cpu = cpu_ppc_init(cpu_model); 58 if (cpu == NULL) { 59 fprintf(stderr, "Unable to find PowerPC %s CPU definition\n", 60 cpu_model); 61 exit(1); 62 } 63 env = &cpu->env; 64 65 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ 66 cpu_clk->opaque = env; 67 /* Set time-base frequency to sysclk */ 68 tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT); 69 tb_clk->opaque = env; 70 ppc_dcr_init(env, NULL, NULL); 71 /* Register qemu callbacks */ 72 qemu_register_reset(ppc4xx_reset, cpu); 73 74 return cpu; 75 } 76 77 /*****************************************************************************/ 78 /* "Universal" Interrupt controller */ 79 enum { 80 DCR_UICSR = 0x000, 81 DCR_UICSRS = 0x001, 82 DCR_UICER = 0x002, 83 DCR_UICCR = 0x003, 84 DCR_UICPR = 0x004, 85 DCR_UICTR = 0x005, 86 DCR_UICMSR = 0x006, 87 DCR_UICVR = 0x007, 88 DCR_UICVCR = 0x008, 89 DCR_UICMAX = 0x009, 90 }; 91 92 #define UIC_MAX_IRQ 32 93 typedef struct ppcuic_t ppcuic_t; 94 struct ppcuic_t { 95 uint32_t dcr_base; 96 int use_vectors; 97 uint32_t level; /* Remembers the state of level-triggered interrupts. */ 98 uint32_t uicsr; /* Status register */ 99 uint32_t uicer; /* Enable register */ 100 uint32_t uiccr; /* Critical register */ 101 uint32_t uicpr; /* Polarity register */ 102 uint32_t uictr; /* Triggering register */ 103 uint32_t uicvcr; /* Vector configuration register */ 104 uint32_t uicvr; 105 qemu_irq *irqs; 106 }; 107 108 static void ppcuic_trigger_irq (ppcuic_t *uic) 109 { 110 uint32_t ir, cr; 111 int start, end, inc, i; 112 113 /* Trigger interrupt if any is pending */ 114 ir = uic->uicsr & uic->uicer & (~uic->uiccr); 115 cr = uic->uicsr & uic->uicer & uic->uiccr; 116 LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 117 " uiccr %08" PRIx32 "\n" 118 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", 119 __func__, uic->uicsr, uic->uicer, uic->uiccr, 120 uic->uicsr & uic->uicer, ir, cr); 121 if (ir != 0x0000000) { 122 LOG_UIC("Raise UIC interrupt\n"); 123 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); 124 } else { 125 LOG_UIC("Lower UIC interrupt\n"); 126 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); 127 } 128 /* Trigger critical interrupt if any is pending and update vector */ 129 if (cr != 0x0000000) { 130 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); 131 if (uic->use_vectors) { 132 /* Compute critical IRQ vector */ 133 if (uic->uicvcr & 1) { 134 start = 31; 135 end = 0; 136 inc = -1; 137 } else { 138 start = 0; 139 end = 31; 140 inc = 1; 141 } 142 uic->uicvr = uic->uicvcr & 0xFFFFFFFC; 143 for (i = start; i <= end; i += inc) { 144 if (cr & (1 << i)) { 145 uic->uicvr += (i - start) * 512 * inc; 146 break; 147 } 148 } 149 } 150 LOG_UIC("Raise UIC critical interrupt - " 151 "vector %08" PRIx32 "\n", uic->uicvr); 152 } else { 153 LOG_UIC("Lower UIC critical interrupt\n"); 154 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); 155 uic->uicvr = 0x00000000; 156 } 157 } 158 159 static void ppcuic_set_irq (void *opaque, int irq_num, int level) 160 { 161 ppcuic_t *uic; 162 uint32_t mask, sr; 163 164 uic = opaque; 165 mask = 1U << (31-irq_num); 166 LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 167 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", 168 __func__, irq_num, level, 169 uic->uicsr, mask, uic->uicsr & mask, level << irq_num); 170 if (irq_num < 0 || irq_num > 31) 171 return; 172 sr = uic->uicsr; 173 174 /* Update status register */ 175 if (uic->uictr & mask) { 176 /* Edge sensitive interrupt */ 177 if (level == 1) 178 uic->uicsr |= mask; 179 } else { 180 /* Level sensitive interrupt */ 181 if (level == 1) { 182 uic->uicsr |= mask; 183 uic->level |= mask; 184 } else { 185 uic->uicsr &= ~mask; 186 uic->level &= ~mask; 187 } 188 } 189 LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " 190 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); 191 if (sr != uic->uicsr) 192 ppcuic_trigger_irq(uic); 193 } 194 195 static uint32_t dcr_read_uic (void *opaque, int dcrn) 196 { 197 ppcuic_t *uic; 198 uint32_t ret; 199 200 uic = opaque; 201 dcrn -= uic->dcr_base; 202 switch (dcrn) { 203 case DCR_UICSR: 204 case DCR_UICSRS: 205 ret = uic->uicsr; 206 break; 207 case DCR_UICER: 208 ret = uic->uicer; 209 break; 210 case DCR_UICCR: 211 ret = uic->uiccr; 212 break; 213 case DCR_UICPR: 214 ret = uic->uicpr; 215 break; 216 case DCR_UICTR: 217 ret = uic->uictr; 218 break; 219 case DCR_UICMSR: 220 ret = uic->uicsr & uic->uicer; 221 break; 222 case DCR_UICVR: 223 if (!uic->use_vectors) 224 goto no_read; 225 ret = uic->uicvr; 226 break; 227 case DCR_UICVCR: 228 if (!uic->use_vectors) 229 goto no_read; 230 ret = uic->uicvcr; 231 break; 232 default: 233 no_read: 234 ret = 0x00000000; 235 break; 236 } 237 238 return ret; 239 } 240 241 static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) 242 { 243 ppcuic_t *uic; 244 245 uic = opaque; 246 dcrn -= uic->dcr_base; 247 LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); 248 switch (dcrn) { 249 case DCR_UICSR: 250 uic->uicsr &= ~val; 251 uic->uicsr |= uic->level; 252 ppcuic_trigger_irq(uic); 253 break; 254 case DCR_UICSRS: 255 uic->uicsr |= val; 256 ppcuic_trigger_irq(uic); 257 break; 258 case DCR_UICER: 259 uic->uicer = val; 260 ppcuic_trigger_irq(uic); 261 break; 262 case DCR_UICCR: 263 uic->uiccr = val; 264 ppcuic_trigger_irq(uic); 265 break; 266 case DCR_UICPR: 267 uic->uicpr = val; 268 break; 269 case DCR_UICTR: 270 uic->uictr = val; 271 ppcuic_trigger_irq(uic); 272 break; 273 case DCR_UICMSR: 274 break; 275 case DCR_UICVR: 276 break; 277 case DCR_UICVCR: 278 uic->uicvcr = val & 0xFFFFFFFD; 279 ppcuic_trigger_irq(uic); 280 break; 281 } 282 } 283 284 static void ppcuic_reset (void *opaque) 285 { 286 ppcuic_t *uic; 287 288 uic = opaque; 289 uic->uiccr = 0x00000000; 290 uic->uicer = 0x00000000; 291 uic->uicpr = 0x00000000; 292 uic->uicsr = 0x00000000; 293 uic->uictr = 0x00000000; 294 if (uic->use_vectors) { 295 uic->uicvcr = 0x00000000; 296 uic->uicvr = 0x0000000; 297 } 298 } 299 300 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, 301 uint32_t dcr_base, int has_ssr, int has_vr) 302 { 303 ppcuic_t *uic; 304 int i; 305 306 uic = g_malloc0(sizeof(ppcuic_t)); 307 uic->dcr_base = dcr_base; 308 uic->irqs = irqs; 309 if (has_vr) 310 uic->use_vectors = 1; 311 for (i = 0; i < DCR_UICMAX; i++) { 312 ppc_dcr_register(env, dcr_base + i, uic, 313 &dcr_read_uic, &dcr_write_uic); 314 } 315 qemu_register_reset(ppcuic_reset, uic); 316 317 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); 318 } 319 320 /*****************************************************************************/ 321 /* SDRAM controller */ 322 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; 323 struct ppc4xx_sdram_t { 324 uint32_t addr; 325 int nbanks; 326 MemoryRegion containers[4]; /* used for clipping */ 327 MemoryRegion *ram_memories; 328 hwaddr ram_bases[4]; 329 hwaddr ram_sizes[4]; 330 uint32_t besr0; 331 uint32_t besr1; 332 uint32_t bear; 333 uint32_t cfg; 334 uint32_t status; 335 uint32_t rtr; 336 uint32_t pmit; 337 uint32_t bcr[4]; 338 uint32_t tr; 339 uint32_t ecccfg; 340 uint32_t eccesr; 341 qemu_irq irq; 342 }; 343 344 enum { 345 SDRAM0_CFGADDR = 0x010, 346 SDRAM0_CFGDATA = 0x011, 347 }; 348 349 /* XXX: TOFIX: some patches have made this code become inconsistent: 350 * there are type inconsistencies, mixing hwaddr, target_ulong 351 * and uint32_t 352 */ 353 static uint32_t sdram_bcr (hwaddr ram_base, 354 hwaddr ram_size) 355 { 356 uint32_t bcr; 357 358 switch (ram_size) { 359 case (4 * 1024 * 1024): 360 bcr = 0x00000000; 361 break; 362 case (8 * 1024 * 1024): 363 bcr = 0x00020000; 364 break; 365 case (16 * 1024 * 1024): 366 bcr = 0x00040000; 367 break; 368 case (32 * 1024 * 1024): 369 bcr = 0x00060000; 370 break; 371 case (64 * 1024 * 1024): 372 bcr = 0x00080000; 373 break; 374 case (128 * 1024 * 1024): 375 bcr = 0x000A0000; 376 break; 377 case (256 * 1024 * 1024): 378 bcr = 0x000C0000; 379 break; 380 default: 381 printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__, 382 ram_size); 383 return 0x00000000; 384 } 385 bcr |= ram_base & 0xFF800000; 386 bcr |= 1; 387 388 return bcr; 389 } 390 391 static inline hwaddr sdram_base(uint32_t bcr) 392 { 393 return bcr & 0xFF800000; 394 } 395 396 static target_ulong sdram_size (uint32_t bcr) 397 { 398 target_ulong size; 399 int sh; 400 401 sh = (bcr >> 17) & 0x7; 402 if (sh == 7) 403 size = -1; 404 else 405 size = (4 * 1024 * 1024) << sh; 406 407 return size; 408 } 409 410 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, 411 uint32_t *bcrp, uint32_t bcr, int enabled) 412 { 413 unsigned n = bcrp - sdram->bcr; 414 415 if (*bcrp & 0x00000001) { 416 /* Unmap RAM */ 417 #ifdef DEBUG_SDRAM 418 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", 419 __func__, sdram_base(*bcrp), sdram_size(*bcrp)); 420 #endif 421 memory_region_del_subregion(get_system_memory(), 422 &sdram->containers[n]); 423 memory_region_del_subregion(&sdram->containers[n], 424 &sdram->ram_memories[n]); 425 object_unparent(OBJECT(&sdram->containers[n])); 426 } 427 *bcrp = bcr & 0xFFDEE001; 428 if (enabled && (bcr & 0x00000001)) { 429 #ifdef DEBUG_SDRAM 430 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", 431 __func__, sdram_base(bcr), sdram_size(bcr)); 432 #endif 433 memory_region_init(&sdram->containers[n], NULL, "sdram-containers", 434 sdram_size(bcr)); 435 memory_region_add_subregion(&sdram->containers[n], 0, 436 &sdram->ram_memories[n]); 437 memory_region_add_subregion(get_system_memory(), 438 sdram_base(bcr), 439 &sdram->containers[n]); 440 } 441 } 442 443 static void sdram_map_bcr (ppc4xx_sdram_t *sdram) 444 { 445 int i; 446 447 for (i = 0; i < sdram->nbanks; i++) { 448 if (sdram->ram_sizes[i] != 0) { 449 sdram_set_bcr(sdram, 450 &sdram->bcr[i], 451 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), 452 1); 453 } else { 454 sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0); 455 } 456 } 457 } 458 459 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) 460 { 461 int i; 462 463 for (i = 0; i < sdram->nbanks; i++) { 464 #ifdef DEBUG_SDRAM 465 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", 466 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); 467 #endif 468 memory_region_del_subregion(get_system_memory(), 469 &sdram->ram_memories[i]); 470 } 471 } 472 473 static uint32_t dcr_read_sdram (void *opaque, int dcrn) 474 { 475 ppc4xx_sdram_t *sdram; 476 uint32_t ret; 477 478 sdram = opaque; 479 switch (dcrn) { 480 case SDRAM0_CFGADDR: 481 ret = sdram->addr; 482 break; 483 case SDRAM0_CFGDATA: 484 switch (sdram->addr) { 485 case 0x00: /* SDRAM_BESR0 */ 486 ret = sdram->besr0; 487 break; 488 case 0x08: /* SDRAM_BESR1 */ 489 ret = sdram->besr1; 490 break; 491 case 0x10: /* SDRAM_BEAR */ 492 ret = sdram->bear; 493 break; 494 case 0x20: /* SDRAM_CFG */ 495 ret = sdram->cfg; 496 break; 497 case 0x24: /* SDRAM_STATUS */ 498 ret = sdram->status; 499 break; 500 case 0x30: /* SDRAM_RTR */ 501 ret = sdram->rtr; 502 break; 503 case 0x34: /* SDRAM_PMIT */ 504 ret = sdram->pmit; 505 break; 506 case 0x40: /* SDRAM_B0CR */ 507 ret = sdram->bcr[0]; 508 break; 509 case 0x44: /* SDRAM_B1CR */ 510 ret = sdram->bcr[1]; 511 break; 512 case 0x48: /* SDRAM_B2CR */ 513 ret = sdram->bcr[2]; 514 break; 515 case 0x4C: /* SDRAM_B3CR */ 516 ret = sdram->bcr[3]; 517 break; 518 case 0x80: /* SDRAM_TR */ 519 ret = -1; /* ? */ 520 break; 521 case 0x94: /* SDRAM_ECCCFG */ 522 ret = sdram->ecccfg; 523 break; 524 case 0x98: /* SDRAM_ECCESR */ 525 ret = sdram->eccesr; 526 break; 527 default: /* Error */ 528 ret = -1; 529 break; 530 } 531 break; 532 default: 533 /* Avoid gcc warning */ 534 ret = 0x00000000; 535 break; 536 } 537 538 return ret; 539 } 540 541 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) 542 { 543 ppc4xx_sdram_t *sdram; 544 545 sdram = opaque; 546 switch (dcrn) { 547 case SDRAM0_CFGADDR: 548 sdram->addr = val; 549 break; 550 case SDRAM0_CFGDATA: 551 switch (sdram->addr) { 552 case 0x00: /* SDRAM_BESR0 */ 553 sdram->besr0 &= ~val; 554 break; 555 case 0x08: /* SDRAM_BESR1 */ 556 sdram->besr1 &= ~val; 557 break; 558 case 0x10: /* SDRAM_BEAR */ 559 sdram->bear = val; 560 break; 561 case 0x20: /* SDRAM_CFG */ 562 val &= 0xFFE00000; 563 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { 564 #ifdef DEBUG_SDRAM 565 printf("%s: enable SDRAM controller\n", __func__); 566 #endif 567 /* validate all RAM mappings */ 568 sdram_map_bcr(sdram); 569 sdram->status &= ~0x80000000; 570 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { 571 #ifdef DEBUG_SDRAM 572 printf("%s: disable SDRAM controller\n", __func__); 573 #endif 574 /* invalidate all RAM mappings */ 575 sdram_unmap_bcr(sdram); 576 sdram->status |= 0x80000000; 577 } 578 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) 579 sdram->status |= 0x40000000; 580 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) 581 sdram->status &= ~0x40000000; 582 sdram->cfg = val; 583 break; 584 case 0x24: /* SDRAM_STATUS */ 585 /* Read-only register */ 586 break; 587 case 0x30: /* SDRAM_RTR */ 588 sdram->rtr = val & 0x3FF80000; 589 break; 590 case 0x34: /* SDRAM_PMIT */ 591 sdram->pmit = (val & 0xF8000000) | 0x07C00000; 592 break; 593 case 0x40: /* SDRAM_B0CR */ 594 sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000); 595 break; 596 case 0x44: /* SDRAM_B1CR */ 597 sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000); 598 break; 599 case 0x48: /* SDRAM_B2CR */ 600 sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000); 601 break; 602 case 0x4C: /* SDRAM_B3CR */ 603 sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000); 604 break; 605 case 0x80: /* SDRAM_TR */ 606 sdram->tr = val & 0x018FC01F; 607 break; 608 case 0x94: /* SDRAM_ECCCFG */ 609 sdram->ecccfg = val & 0x00F00000; 610 break; 611 case 0x98: /* SDRAM_ECCESR */ 612 val &= 0xFFF0F000; 613 if (sdram->eccesr == 0 && val != 0) 614 qemu_irq_raise(sdram->irq); 615 else if (sdram->eccesr != 0 && val == 0) 616 qemu_irq_lower(sdram->irq); 617 sdram->eccesr = val; 618 break; 619 default: /* Error */ 620 break; 621 } 622 break; 623 } 624 } 625 626 static void sdram_reset (void *opaque) 627 { 628 ppc4xx_sdram_t *sdram; 629 630 sdram = opaque; 631 sdram->addr = 0x00000000; 632 sdram->bear = 0x00000000; 633 sdram->besr0 = 0x00000000; /* No error */ 634 sdram->besr1 = 0x00000000; /* No error */ 635 sdram->cfg = 0x00000000; 636 sdram->ecccfg = 0x00000000; /* No ECC */ 637 sdram->eccesr = 0x00000000; /* No error */ 638 sdram->pmit = 0x07C00000; 639 sdram->rtr = 0x05F00000; 640 sdram->tr = 0x00854009; 641 /* We pre-initialize RAM banks */ 642 sdram->status = 0x00000000; 643 sdram->cfg = 0x00800000; 644 } 645 646 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, 647 MemoryRegion *ram_memories, 648 hwaddr *ram_bases, 649 hwaddr *ram_sizes, 650 int do_init) 651 { 652 ppc4xx_sdram_t *sdram; 653 654 sdram = g_malloc0(sizeof(ppc4xx_sdram_t)); 655 sdram->irq = irq; 656 sdram->nbanks = nbanks; 657 sdram->ram_memories = ram_memories; 658 memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr)); 659 memcpy(sdram->ram_bases, ram_bases, 660 nbanks * sizeof(hwaddr)); 661 memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr)); 662 memcpy(sdram->ram_sizes, ram_sizes, 663 nbanks * sizeof(hwaddr)); 664 qemu_register_reset(&sdram_reset, sdram); 665 ppc_dcr_register(env, SDRAM0_CFGADDR, 666 sdram, &dcr_read_sdram, &dcr_write_sdram); 667 ppc_dcr_register(env, SDRAM0_CFGDATA, 668 sdram, &dcr_read_sdram, &dcr_write_sdram); 669 if (do_init) 670 sdram_map_bcr(sdram); 671 } 672 673 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. 674 * 675 * sdram_bank_sizes[] must be 0-terminated. 676 * 677 * The 4xx SDRAM controller supports a small number of banks, and each bank 678 * must be one of a small set of sizes. The number of banks and the supported 679 * sizes varies by SoC. */ 680 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, 681 MemoryRegion ram_memories[], 682 hwaddr ram_bases[], 683 hwaddr ram_sizes[], 684 const unsigned int sdram_bank_sizes[]) 685 { 686 ram_addr_t size_left = ram_size; 687 ram_addr_t base = 0; 688 int i; 689 int j; 690 691 for (i = 0; i < nr_banks; i++) { 692 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 693 unsigned int bank_size = sdram_bank_sizes[j]; 694 695 if (bank_size <= size_left) { 696 char name[32]; 697 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 698 memory_region_allocate_system_memory(&ram_memories[i], NULL, 699 name, bank_size); 700 ram_bases[i] = base; 701 ram_sizes[i] = bank_size; 702 base += bank_size; 703 size_left -= bank_size; 704 break; 705 } 706 } 707 708 if (!size_left) { 709 /* No need to use the remaining banks. */ 710 break; 711 } 712 } 713 714 ram_size -= size_left; 715 if (size_left) 716 printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n", 717 (int)(ram_size >> 20)); 718 719 return ram_size; 720 } 721