1 /* 2 * QEMU PowerPC 4xx embedded processors shared devices emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "cpu.h" 27 #include "hw/hw.h" 28 #include "hw/ppc/ppc.h" 29 #include "hw/ppc/ppc4xx.h" 30 #include "hw/boards.h" 31 #include "qemu/log.h" 32 #include "exec/address-spaces.h" 33 #include "qemu/error-report.h" 34 35 /*#define DEBUG_UIC*/ 36 37 #ifdef DEBUG_UIC 38 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 39 #else 40 # define LOG_UIC(...) do { } while (0) 41 #endif 42 43 static void ppc4xx_reset(void *opaque) 44 { 45 PowerPCCPU *cpu = opaque; 46 47 cpu_reset(CPU(cpu)); 48 } 49 50 /*****************************************************************************/ 51 /* Generic PowerPC 4xx processor instantiation */ 52 PowerPCCPU *ppc4xx_init(const char *cpu_type, 53 clk_setup_t *cpu_clk, clk_setup_t *tb_clk, 54 uint32_t sysclk) 55 { 56 PowerPCCPU *cpu; 57 CPUPPCState *env; 58 59 /* init CPUs */ 60 cpu = POWERPC_CPU(cpu_create(cpu_type)); 61 env = &cpu->env; 62 63 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ 64 cpu_clk->opaque = env; 65 /* Set time-base frequency to sysclk */ 66 tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT); 67 tb_clk->opaque = env; 68 ppc_dcr_init(env, NULL, NULL); 69 /* Register qemu callbacks */ 70 qemu_register_reset(ppc4xx_reset, cpu); 71 72 return cpu; 73 } 74 75 /*****************************************************************************/ 76 /* "Universal" Interrupt controller */ 77 enum { 78 DCR_UICSR = 0x000, 79 DCR_UICSRS = 0x001, 80 DCR_UICER = 0x002, 81 DCR_UICCR = 0x003, 82 DCR_UICPR = 0x004, 83 DCR_UICTR = 0x005, 84 DCR_UICMSR = 0x006, 85 DCR_UICVR = 0x007, 86 DCR_UICVCR = 0x008, 87 DCR_UICMAX = 0x009, 88 }; 89 90 #define UIC_MAX_IRQ 32 91 typedef struct ppcuic_t ppcuic_t; 92 struct ppcuic_t { 93 uint32_t dcr_base; 94 int use_vectors; 95 uint32_t level; /* Remembers the state of level-triggered interrupts. */ 96 uint32_t uicsr; /* Status register */ 97 uint32_t uicer; /* Enable register */ 98 uint32_t uiccr; /* Critical register */ 99 uint32_t uicpr; /* Polarity register */ 100 uint32_t uictr; /* Triggering register */ 101 uint32_t uicvcr; /* Vector configuration register */ 102 uint32_t uicvr; 103 qemu_irq *irqs; 104 }; 105 106 static void ppcuic_trigger_irq (ppcuic_t *uic) 107 { 108 uint32_t ir, cr; 109 int start, end, inc, i; 110 111 /* Trigger interrupt if any is pending */ 112 ir = uic->uicsr & uic->uicer & (~uic->uiccr); 113 cr = uic->uicsr & uic->uicer & uic->uiccr; 114 LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 115 " uiccr %08" PRIx32 "\n" 116 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", 117 __func__, uic->uicsr, uic->uicer, uic->uiccr, 118 uic->uicsr & uic->uicer, ir, cr); 119 if (ir != 0x0000000) { 120 LOG_UIC("Raise UIC interrupt\n"); 121 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); 122 } else { 123 LOG_UIC("Lower UIC interrupt\n"); 124 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); 125 } 126 /* Trigger critical interrupt if any is pending and update vector */ 127 if (cr != 0x0000000) { 128 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); 129 if (uic->use_vectors) { 130 /* Compute critical IRQ vector */ 131 if (uic->uicvcr & 1) { 132 start = 31; 133 end = 0; 134 inc = -1; 135 } else { 136 start = 0; 137 end = 31; 138 inc = 1; 139 } 140 uic->uicvr = uic->uicvcr & 0xFFFFFFFC; 141 for (i = start; i <= end; i += inc) { 142 if (cr & (1 << i)) { 143 uic->uicvr += (i - start) * 512 * inc; 144 break; 145 } 146 } 147 } 148 LOG_UIC("Raise UIC critical interrupt - " 149 "vector %08" PRIx32 "\n", uic->uicvr); 150 } else { 151 LOG_UIC("Lower UIC critical interrupt\n"); 152 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); 153 uic->uicvr = 0x00000000; 154 } 155 } 156 157 static void ppcuic_set_irq (void *opaque, int irq_num, int level) 158 { 159 ppcuic_t *uic; 160 uint32_t mask, sr; 161 162 uic = opaque; 163 mask = 1U << (31-irq_num); 164 LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 165 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", 166 __func__, irq_num, level, 167 uic->uicsr, mask, uic->uicsr & mask, level << irq_num); 168 if (irq_num < 0 || irq_num > 31) 169 return; 170 sr = uic->uicsr; 171 172 /* Update status register */ 173 if (uic->uictr & mask) { 174 /* Edge sensitive interrupt */ 175 if (level == 1) 176 uic->uicsr |= mask; 177 } else { 178 /* Level sensitive interrupt */ 179 if (level == 1) { 180 uic->uicsr |= mask; 181 uic->level |= mask; 182 } else { 183 uic->uicsr &= ~mask; 184 uic->level &= ~mask; 185 } 186 } 187 LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " 188 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); 189 if (sr != uic->uicsr) 190 ppcuic_trigger_irq(uic); 191 } 192 193 static uint32_t dcr_read_uic (void *opaque, int dcrn) 194 { 195 ppcuic_t *uic; 196 uint32_t ret; 197 198 uic = opaque; 199 dcrn -= uic->dcr_base; 200 switch (dcrn) { 201 case DCR_UICSR: 202 case DCR_UICSRS: 203 ret = uic->uicsr; 204 break; 205 case DCR_UICER: 206 ret = uic->uicer; 207 break; 208 case DCR_UICCR: 209 ret = uic->uiccr; 210 break; 211 case DCR_UICPR: 212 ret = uic->uicpr; 213 break; 214 case DCR_UICTR: 215 ret = uic->uictr; 216 break; 217 case DCR_UICMSR: 218 ret = uic->uicsr & uic->uicer; 219 break; 220 case DCR_UICVR: 221 if (!uic->use_vectors) 222 goto no_read; 223 ret = uic->uicvr; 224 break; 225 case DCR_UICVCR: 226 if (!uic->use_vectors) 227 goto no_read; 228 ret = uic->uicvcr; 229 break; 230 default: 231 no_read: 232 ret = 0x00000000; 233 break; 234 } 235 236 return ret; 237 } 238 239 static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) 240 { 241 ppcuic_t *uic; 242 243 uic = opaque; 244 dcrn -= uic->dcr_base; 245 LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); 246 switch (dcrn) { 247 case DCR_UICSR: 248 uic->uicsr &= ~val; 249 uic->uicsr |= uic->level; 250 ppcuic_trigger_irq(uic); 251 break; 252 case DCR_UICSRS: 253 uic->uicsr |= val; 254 ppcuic_trigger_irq(uic); 255 break; 256 case DCR_UICER: 257 uic->uicer = val; 258 ppcuic_trigger_irq(uic); 259 break; 260 case DCR_UICCR: 261 uic->uiccr = val; 262 ppcuic_trigger_irq(uic); 263 break; 264 case DCR_UICPR: 265 uic->uicpr = val; 266 break; 267 case DCR_UICTR: 268 uic->uictr = val; 269 ppcuic_trigger_irq(uic); 270 break; 271 case DCR_UICMSR: 272 break; 273 case DCR_UICVR: 274 break; 275 case DCR_UICVCR: 276 uic->uicvcr = val & 0xFFFFFFFD; 277 ppcuic_trigger_irq(uic); 278 break; 279 } 280 } 281 282 static void ppcuic_reset (void *opaque) 283 { 284 ppcuic_t *uic; 285 286 uic = opaque; 287 uic->uiccr = 0x00000000; 288 uic->uicer = 0x00000000; 289 uic->uicpr = 0x00000000; 290 uic->uicsr = 0x00000000; 291 uic->uictr = 0x00000000; 292 if (uic->use_vectors) { 293 uic->uicvcr = 0x00000000; 294 uic->uicvr = 0x0000000; 295 } 296 } 297 298 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, 299 uint32_t dcr_base, int has_ssr, int has_vr) 300 { 301 ppcuic_t *uic; 302 int i; 303 304 uic = g_malloc0(sizeof(ppcuic_t)); 305 uic->dcr_base = dcr_base; 306 uic->irqs = irqs; 307 if (has_vr) 308 uic->use_vectors = 1; 309 for (i = 0; i < DCR_UICMAX; i++) { 310 ppc_dcr_register(env, dcr_base + i, uic, 311 &dcr_read_uic, &dcr_write_uic); 312 } 313 qemu_register_reset(ppcuic_reset, uic); 314 315 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); 316 } 317 318 /*****************************************************************************/ 319 /* SDRAM controller */ 320 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; 321 struct ppc4xx_sdram_t { 322 uint32_t addr; 323 int nbanks; 324 MemoryRegion containers[4]; /* used for clipping */ 325 MemoryRegion *ram_memories; 326 hwaddr ram_bases[4]; 327 hwaddr ram_sizes[4]; 328 uint32_t besr0; 329 uint32_t besr1; 330 uint32_t bear; 331 uint32_t cfg; 332 uint32_t status; 333 uint32_t rtr; 334 uint32_t pmit; 335 uint32_t bcr[4]; 336 uint32_t tr; 337 uint32_t ecccfg; 338 uint32_t eccesr; 339 qemu_irq irq; 340 }; 341 342 enum { 343 SDRAM0_CFGADDR = 0x010, 344 SDRAM0_CFGDATA = 0x011, 345 }; 346 347 /* XXX: TOFIX: some patches have made this code become inconsistent: 348 * there are type inconsistencies, mixing hwaddr, target_ulong 349 * and uint32_t 350 */ 351 static uint32_t sdram_bcr (hwaddr ram_base, 352 hwaddr ram_size) 353 { 354 uint32_t bcr; 355 356 switch (ram_size) { 357 case 4 * MiB: 358 bcr = 0x00000000; 359 break; 360 case 8 * MiB: 361 bcr = 0x00020000; 362 break; 363 case 16 * MiB: 364 bcr = 0x00040000; 365 break; 366 case 32 * MiB: 367 bcr = 0x00060000; 368 break; 369 case 64 * MiB: 370 bcr = 0x00080000; 371 break; 372 case 128 * MiB: 373 bcr = 0x000A0000; 374 break; 375 case 256 * MiB: 376 bcr = 0x000C0000; 377 break; 378 default: 379 printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__, 380 ram_size); 381 return 0x00000000; 382 } 383 bcr |= ram_base & 0xFF800000; 384 bcr |= 1; 385 386 return bcr; 387 } 388 389 static inline hwaddr sdram_base(uint32_t bcr) 390 { 391 return bcr & 0xFF800000; 392 } 393 394 static target_ulong sdram_size (uint32_t bcr) 395 { 396 target_ulong size; 397 int sh; 398 399 sh = (bcr >> 17) & 0x7; 400 if (sh == 7) 401 size = -1; 402 else 403 size = (4 * MiB) << sh; 404 405 return size; 406 } 407 408 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, 409 uint32_t bcr, int enabled) 410 { 411 if (sdram->bcr[i] & 0x00000001) { 412 /* Unmap RAM */ 413 #ifdef DEBUG_SDRAM 414 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", 415 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); 416 #endif 417 memory_region_del_subregion(get_system_memory(), 418 &sdram->containers[i]); 419 memory_region_del_subregion(&sdram->containers[i], 420 &sdram->ram_memories[i]); 421 object_unparent(OBJECT(&sdram->containers[i])); 422 } 423 sdram->bcr[i] = bcr & 0xFFDEE001; 424 if (enabled && (bcr & 0x00000001)) { 425 #ifdef DEBUG_SDRAM 426 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", 427 __func__, sdram_base(bcr), sdram_size(bcr)); 428 #endif 429 memory_region_init(&sdram->containers[i], NULL, "sdram-containers", 430 sdram_size(bcr)); 431 memory_region_add_subregion(&sdram->containers[i], 0, 432 &sdram->ram_memories[i]); 433 memory_region_add_subregion(get_system_memory(), 434 sdram_base(bcr), 435 &sdram->containers[i]); 436 } 437 } 438 439 static void sdram_map_bcr (ppc4xx_sdram_t *sdram) 440 { 441 int i; 442 443 for (i = 0; i < sdram->nbanks; i++) { 444 if (sdram->ram_sizes[i] != 0) { 445 sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i], 446 sdram->ram_sizes[i]), 1); 447 } else { 448 sdram_set_bcr(sdram, i, 0x00000000, 0); 449 } 450 } 451 } 452 453 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) 454 { 455 int i; 456 457 for (i = 0; i < sdram->nbanks; i++) { 458 #ifdef DEBUG_SDRAM 459 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", 460 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); 461 #endif 462 memory_region_del_subregion(get_system_memory(), 463 &sdram->ram_memories[i]); 464 } 465 } 466 467 static uint32_t dcr_read_sdram (void *opaque, int dcrn) 468 { 469 ppc4xx_sdram_t *sdram; 470 uint32_t ret; 471 472 sdram = opaque; 473 switch (dcrn) { 474 case SDRAM0_CFGADDR: 475 ret = sdram->addr; 476 break; 477 case SDRAM0_CFGDATA: 478 switch (sdram->addr) { 479 case 0x00: /* SDRAM_BESR0 */ 480 ret = sdram->besr0; 481 break; 482 case 0x08: /* SDRAM_BESR1 */ 483 ret = sdram->besr1; 484 break; 485 case 0x10: /* SDRAM_BEAR */ 486 ret = sdram->bear; 487 break; 488 case 0x20: /* SDRAM_CFG */ 489 ret = sdram->cfg; 490 break; 491 case 0x24: /* SDRAM_STATUS */ 492 ret = sdram->status; 493 break; 494 case 0x30: /* SDRAM_RTR */ 495 ret = sdram->rtr; 496 break; 497 case 0x34: /* SDRAM_PMIT */ 498 ret = sdram->pmit; 499 break; 500 case 0x40: /* SDRAM_B0CR */ 501 ret = sdram->bcr[0]; 502 break; 503 case 0x44: /* SDRAM_B1CR */ 504 ret = sdram->bcr[1]; 505 break; 506 case 0x48: /* SDRAM_B2CR */ 507 ret = sdram->bcr[2]; 508 break; 509 case 0x4C: /* SDRAM_B3CR */ 510 ret = sdram->bcr[3]; 511 break; 512 case 0x80: /* SDRAM_TR */ 513 ret = -1; /* ? */ 514 break; 515 case 0x94: /* SDRAM_ECCCFG */ 516 ret = sdram->ecccfg; 517 break; 518 case 0x98: /* SDRAM_ECCESR */ 519 ret = sdram->eccesr; 520 break; 521 default: /* Error */ 522 ret = -1; 523 break; 524 } 525 break; 526 default: 527 /* Avoid gcc warning */ 528 ret = 0x00000000; 529 break; 530 } 531 532 return ret; 533 } 534 535 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) 536 { 537 ppc4xx_sdram_t *sdram; 538 539 sdram = opaque; 540 switch (dcrn) { 541 case SDRAM0_CFGADDR: 542 sdram->addr = val; 543 break; 544 case SDRAM0_CFGDATA: 545 switch (sdram->addr) { 546 case 0x00: /* SDRAM_BESR0 */ 547 sdram->besr0 &= ~val; 548 break; 549 case 0x08: /* SDRAM_BESR1 */ 550 sdram->besr1 &= ~val; 551 break; 552 case 0x10: /* SDRAM_BEAR */ 553 sdram->bear = val; 554 break; 555 case 0x20: /* SDRAM_CFG */ 556 val &= 0xFFE00000; 557 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { 558 #ifdef DEBUG_SDRAM 559 printf("%s: enable SDRAM controller\n", __func__); 560 #endif 561 /* validate all RAM mappings */ 562 sdram_map_bcr(sdram); 563 sdram->status &= ~0x80000000; 564 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { 565 #ifdef DEBUG_SDRAM 566 printf("%s: disable SDRAM controller\n", __func__); 567 #endif 568 /* invalidate all RAM mappings */ 569 sdram_unmap_bcr(sdram); 570 sdram->status |= 0x80000000; 571 } 572 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) 573 sdram->status |= 0x40000000; 574 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) 575 sdram->status &= ~0x40000000; 576 sdram->cfg = val; 577 break; 578 case 0x24: /* SDRAM_STATUS */ 579 /* Read-only register */ 580 break; 581 case 0x30: /* SDRAM_RTR */ 582 sdram->rtr = val & 0x3FF80000; 583 break; 584 case 0x34: /* SDRAM_PMIT */ 585 sdram->pmit = (val & 0xF8000000) | 0x07C00000; 586 break; 587 case 0x40: /* SDRAM_B0CR */ 588 sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); 589 break; 590 case 0x44: /* SDRAM_B1CR */ 591 sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); 592 break; 593 case 0x48: /* SDRAM_B2CR */ 594 sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); 595 break; 596 case 0x4C: /* SDRAM_B3CR */ 597 sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); 598 break; 599 case 0x80: /* SDRAM_TR */ 600 sdram->tr = val & 0x018FC01F; 601 break; 602 case 0x94: /* SDRAM_ECCCFG */ 603 sdram->ecccfg = val & 0x00F00000; 604 break; 605 case 0x98: /* SDRAM_ECCESR */ 606 val &= 0xFFF0F000; 607 if (sdram->eccesr == 0 && val != 0) 608 qemu_irq_raise(sdram->irq); 609 else if (sdram->eccesr != 0 && val == 0) 610 qemu_irq_lower(sdram->irq); 611 sdram->eccesr = val; 612 break; 613 default: /* Error */ 614 break; 615 } 616 break; 617 } 618 } 619 620 static void sdram_reset (void *opaque) 621 { 622 ppc4xx_sdram_t *sdram; 623 624 sdram = opaque; 625 sdram->addr = 0x00000000; 626 sdram->bear = 0x00000000; 627 sdram->besr0 = 0x00000000; /* No error */ 628 sdram->besr1 = 0x00000000; /* No error */ 629 sdram->cfg = 0x00000000; 630 sdram->ecccfg = 0x00000000; /* No ECC */ 631 sdram->eccesr = 0x00000000; /* No error */ 632 sdram->pmit = 0x07C00000; 633 sdram->rtr = 0x05F00000; 634 sdram->tr = 0x00854009; 635 /* We pre-initialize RAM banks */ 636 sdram->status = 0x00000000; 637 sdram->cfg = 0x00800000; 638 } 639 640 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, 641 MemoryRegion *ram_memories, 642 hwaddr *ram_bases, 643 hwaddr *ram_sizes, 644 int do_init) 645 { 646 ppc4xx_sdram_t *sdram; 647 648 sdram = g_malloc0(sizeof(ppc4xx_sdram_t)); 649 sdram->irq = irq; 650 sdram->nbanks = nbanks; 651 sdram->ram_memories = ram_memories; 652 memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr)); 653 memcpy(sdram->ram_bases, ram_bases, 654 nbanks * sizeof(hwaddr)); 655 memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr)); 656 memcpy(sdram->ram_sizes, ram_sizes, 657 nbanks * sizeof(hwaddr)); 658 qemu_register_reset(&sdram_reset, sdram); 659 ppc_dcr_register(env, SDRAM0_CFGADDR, 660 sdram, &dcr_read_sdram, &dcr_write_sdram); 661 ppc_dcr_register(env, SDRAM0_CFGDATA, 662 sdram, &dcr_read_sdram, &dcr_write_sdram); 663 if (do_init) 664 sdram_map_bcr(sdram); 665 } 666 667 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. 668 * 669 * sdram_bank_sizes[] must be 0-terminated. 670 * 671 * The 4xx SDRAM controller supports a small number of banks, and each bank 672 * must be one of a small set of sizes. The number of banks and the supported 673 * sizes varies by SoC. */ 674 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, 675 MemoryRegion ram_memories[], 676 hwaddr ram_bases[], 677 hwaddr ram_sizes[], 678 const ram_addr_t sdram_bank_sizes[]) 679 { 680 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 681 ram_addr_t size_left = ram_size; 682 ram_addr_t base = 0; 683 ram_addr_t bank_size; 684 int i; 685 int j; 686 687 for (i = 0; i < nr_banks; i++) { 688 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 689 bank_size = sdram_bank_sizes[j]; 690 if (bank_size <= size_left) { 691 size_left -= bank_size; 692 } 693 } 694 if (!size_left) { 695 /* No need to use the remaining banks. */ 696 break; 697 } 698 } 699 700 ram_size -= size_left; 701 if (size_left) { 702 error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM" 703 " controller limits", ram_size / MiB); 704 } 705 706 memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size); 707 708 size_left = ram_size; 709 for (i = 0; i < nr_banks && size_left; i++) { 710 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 711 bank_size = sdram_bank_sizes[j]; 712 713 if (bank_size <= size_left) { 714 char name[32]; 715 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 716 memory_region_init_alias(&ram_memories[i], NULL, name, ram, 717 base, bank_size); 718 ram_bases[i] = base; 719 ram_sizes[i] = bank_size; 720 base += bank_size; 721 size_left -= bank_size; 722 break; 723 } 724 } 725 } 726 727 return ram_size; 728 } 729 730 /*****************************************************************************/ 731 /* MAL */ 732 733 enum { 734 MAL0_CFG = 0x180, 735 MAL0_ESR = 0x181, 736 MAL0_IER = 0x182, 737 MAL0_TXCASR = 0x184, 738 MAL0_TXCARR = 0x185, 739 MAL0_TXEOBISR = 0x186, 740 MAL0_TXDEIR = 0x187, 741 MAL0_RXCASR = 0x190, 742 MAL0_RXCARR = 0x191, 743 MAL0_RXEOBISR = 0x192, 744 MAL0_RXDEIR = 0x193, 745 MAL0_TXCTP0R = 0x1A0, 746 MAL0_RXCTP0R = 0x1C0, 747 MAL0_RCBS0 = 0x1E0, 748 MAL0_RCBS1 = 0x1E1, 749 }; 750 751 typedef struct ppc4xx_mal_t ppc4xx_mal_t; 752 struct ppc4xx_mal_t { 753 qemu_irq irqs[4]; 754 uint32_t cfg; 755 uint32_t esr; 756 uint32_t ier; 757 uint32_t txcasr; 758 uint32_t txcarr; 759 uint32_t txeobisr; 760 uint32_t txdeir; 761 uint32_t rxcasr; 762 uint32_t rxcarr; 763 uint32_t rxeobisr; 764 uint32_t rxdeir; 765 uint32_t *txctpr; 766 uint32_t *rxctpr; 767 uint32_t *rcbs; 768 uint8_t txcnum; 769 uint8_t rxcnum; 770 }; 771 772 static void ppc4xx_mal_reset(void *opaque) 773 { 774 ppc4xx_mal_t *mal; 775 776 mal = opaque; 777 mal->cfg = 0x0007C000; 778 mal->esr = 0x00000000; 779 mal->ier = 0x00000000; 780 mal->rxcasr = 0x00000000; 781 mal->rxdeir = 0x00000000; 782 mal->rxeobisr = 0x00000000; 783 mal->txcasr = 0x00000000; 784 mal->txdeir = 0x00000000; 785 mal->txeobisr = 0x00000000; 786 } 787 788 static uint32_t dcr_read_mal(void *opaque, int dcrn) 789 { 790 ppc4xx_mal_t *mal; 791 uint32_t ret; 792 793 mal = opaque; 794 switch (dcrn) { 795 case MAL0_CFG: 796 ret = mal->cfg; 797 break; 798 case MAL0_ESR: 799 ret = mal->esr; 800 break; 801 case MAL0_IER: 802 ret = mal->ier; 803 break; 804 case MAL0_TXCASR: 805 ret = mal->txcasr; 806 break; 807 case MAL0_TXCARR: 808 ret = mal->txcarr; 809 break; 810 case MAL0_TXEOBISR: 811 ret = mal->txeobisr; 812 break; 813 case MAL0_TXDEIR: 814 ret = mal->txdeir; 815 break; 816 case MAL0_RXCASR: 817 ret = mal->rxcasr; 818 break; 819 case MAL0_RXCARR: 820 ret = mal->rxcarr; 821 break; 822 case MAL0_RXEOBISR: 823 ret = mal->rxeobisr; 824 break; 825 case MAL0_RXDEIR: 826 ret = mal->rxdeir; 827 break; 828 default: 829 ret = 0; 830 break; 831 } 832 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 833 ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; 834 } 835 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 836 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; 837 } 838 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 839 ret = mal->rcbs[dcrn - MAL0_RCBS0]; 840 } 841 842 return ret; 843 } 844 845 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) 846 { 847 ppc4xx_mal_t *mal; 848 849 mal = opaque; 850 switch (dcrn) { 851 case MAL0_CFG: 852 if (val & 0x80000000) { 853 ppc4xx_mal_reset(mal); 854 } 855 mal->cfg = val & 0x00FFC087; 856 break; 857 case MAL0_ESR: 858 /* Read/clear */ 859 mal->esr &= ~val; 860 break; 861 case MAL0_IER: 862 mal->ier = val & 0x0000001F; 863 break; 864 case MAL0_TXCASR: 865 mal->txcasr = val & 0xF0000000; 866 break; 867 case MAL0_TXCARR: 868 mal->txcarr = val & 0xF0000000; 869 break; 870 case MAL0_TXEOBISR: 871 /* Read/clear */ 872 mal->txeobisr &= ~val; 873 break; 874 case MAL0_TXDEIR: 875 /* Read/clear */ 876 mal->txdeir &= ~val; 877 break; 878 case MAL0_RXCASR: 879 mal->rxcasr = val & 0xC0000000; 880 break; 881 case MAL0_RXCARR: 882 mal->rxcarr = val & 0xC0000000; 883 break; 884 case MAL0_RXEOBISR: 885 /* Read/clear */ 886 mal->rxeobisr &= ~val; 887 break; 888 case MAL0_RXDEIR: 889 /* Read/clear */ 890 mal->rxdeir &= ~val; 891 break; 892 } 893 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 894 mal->txctpr[dcrn - MAL0_TXCTP0R] = val; 895 } 896 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 897 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; 898 } 899 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 900 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; 901 } 902 } 903 904 void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, 905 qemu_irq irqs[4]) 906 { 907 ppc4xx_mal_t *mal; 908 int i; 909 910 assert(txcnum <= 32 && rxcnum <= 32); 911 mal = g_malloc0(sizeof(*mal)); 912 mal->txcnum = txcnum; 913 mal->rxcnum = rxcnum; 914 mal->txctpr = g_new0(uint32_t, txcnum); 915 mal->rxctpr = g_new0(uint32_t, rxcnum); 916 mal->rcbs = g_new0(uint32_t, rxcnum); 917 for (i = 0; i < 4; i++) { 918 mal->irqs[i] = irqs[i]; 919 } 920 qemu_register_reset(&ppc4xx_mal_reset, mal); 921 ppc_dcr_register(env, MAL0_CFG, 922 mal, &dcr_read_mal, &dcr_write_mal); 923 ppc_dcr_register(env, MAL0_ESR, 924 mal, &dcr_read_mal, &dcr_write_mal); 925 ppc_dcr_register(env, MAL0_IER, 926 mal, &dcr_read_mal, &dcr_write_mal); 927 ppc_dcr_register(env, MAL0_TXCASR, 928 mal, &dcr_read_mal, &dcr_write_mal); 929 ppc_dcr_register(env, MAL0_TXCARR, 930 mal, &dcr_read_mal, &dcr_write_mal); 931 ppc_dcr_register(env, MAL0_TXEOBISR, 932 mal, &dcr_read_mal, &dcr_write_mal); 933 ppc_dcr_register(env, MAL0_TXDEIR, 934 mal, &dcr_read_mal, &dcr_write_mal); 935 ppc_dcr_register(env, MAL0_RXCASR, 936 mal, &dcr_read_mal, &dcr_write_mal); 937 ppc_dcr_register(env, MAL0_RXCARR, 938 mal, &dcr_read_mal, &dcr_write_mal); 939 ppc_dcr_register(env, MAL0_RXEOBISR, 940 mal, &dcr_read_mal, &dcr_write_mal); 941 ppc_dcr_register(env, MAL0_RXDEIR, 942 mal, &dcr_read_mal, &dcr_write_mal); 943 for (i = 0; i < txcnum; i++) { 944 ppc_dcr_register(env, MAL0_TXCTP0R + i, 945 mal, &dcr_read_mal, &dcr_write_mal); 946 } 947 for (i = 0; i < rxcnum; i++) { 948 ppc_dcr_register(env, MAL0_RXCTP0R + i, 949 mal, &dcr_read_mal, &dcr_write_mal); 950 } 951 for (i = 0; i < rxcnum; i++) { 952 ppc_dcr_register(env, MAL0_RCBS0 + i, 953 mal, &dcr_read_mal, &dcr_write_mal); 954 } 955 } 956