1 /* 2 * QEMU PowerPC 440 embedded processors emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This work is licensed under the GNU GPL license version 2 or later. 8 * 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/units.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "hw/irq.h" 18 #include "exec/memory.h" 19 #include "hw/ppc/ppc4xx.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/pci/pci.h" 22 #include "sysemu/block-backend.h" 23 #include "sysemu/reset.h" 24 #include "ppc440.h" 25 #include "qom/object.h" 26 27 /*****************************************************************************/ 28 /* L2 Cache as SRAM */ 29 /* FIXME:fix names */ 30 enum { 31 DCR_L2CACHE_BASE = 0x30, 32 DCR_L2CACHE_CFG = DCR_L2CACHE_BASE, 33 DCR_L2CACHE_CMD, 34 DCR_L2CACHE_ADDR, 35 DCR_L2CACHE_DATA, 36 DCR_L2CACHE_STAT, 37 DCR_L2CACHE_CVER, 38 DCR_L2CACHE_SNP0, 39 DCR_L2CACHE_SNP1, 40 DCR_L2CACHE_END = DCR_L2CACHE_SNP1, 41 }; 42 43 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ 44 enum { 45 DCR_ISRAM0_BASE = 0x20, 46 DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE, 47 DCR_ISRAM0_SB1CR, 48 DCR_ISRAM0_SB2CR, 49 DCR_ISRAM0_SB3CR, 50 DCR_ISRAM0_BEAR, 51 DCR_ISRAM0_BESR0, 52 DCR_ISRAM0_BESR1, 53 DCR_ISRAM0_PMEG, 54 DCR_ISRAM0_CID, 55 DCR_ISRAM0_REVID, 56 DCR_ISRAM0_DPC, 57 DCR_ISRAM0_END = DCR_ISRAM0_DPC 58 }; 59 60 enum { 61 DCR_ISRAM1_BASE = 0xb0, 62 DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE, 63 /* single bank */ 64 DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04, 65 DCR_ISRAM1_BESR0, 66 DCR_ISRAM1_BESR1, 67 DCR_ISRAM1_PMEG, 68 DCR_ISRAM1_CID, 69 DCR_ISRAM1_REVID, 70 DCR_ISRAM1_DPC, 71 DCR_ISRAM1_END = DCR_ISRAM1_DPC 72 }; 73 74 typedef struct ppc4xx_l2sram_t { 75 MemoryRegion bank[4]; 76 uint32_t l2cache[8]; 77 uint32_t isram0[11]; 78 } ppc4xx_l2sram_t; 79 80 #ifdef MAP_L2SRAM 81 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, 82 uint32_t isarc, uint32_t isacntl, 83 uint32_t dsarc, uint32_t dsacntl) 84 { 85 if (l2sram->isarc != isarc || 86 (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 87 if (l2sram->isacntl & 0x80000000) { 88 /* Unmap previously assigned memory region */ 89 memory_region_del_subregion(get_system_memory(), 90 &l2sram->isarc_ram); 91 } 92 if (isacntl & 0x80000000) { 93 /* Map new instruction memory region */ 94 memory_region_add_subregion(get_system_memory(), isarc, 95 &l2sram->isarc_ram); 96 } 97 } 98 if (l2sram->dsarc != dsarc || 99 (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 100 if (l2sram->dsacntl & 0x80000000) { 101 /* Beware not to unmap the region we just mapped */ 102 if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) { 103 /* Unmap previously assigned memory region */ 104 memory_region_del_subregion(get_system_memory(), 105 &l2sram->dsarc_ram); 106 } 107 } 108 if (dsacntl & 0x80000000) { 109 /* Beware not to remap the region we just mapped */ 110 if (!(isacntl & 0x80000000) || dsarc != isarc) { 111 /* Map new data memory region */ 112 memory_region_add_subregion(get_system_memory(), dsarc, 113 &l2sram->dsarc_ram); 114 } 115 } 116 } 117 } 118 #endif 119 120 static uint32_t dcr_read_l2sram(void *opaque, int dcrn) 121 { 122 ppc4xx_l2sram_t *l2sram = opaque; 123 uint32_t ret = 0; 124 125 switch (dcrn) { 126 case DCR_L2CACHE_CFG: 127 case DCR_L2CACHE_CMD: 128 case DCR_L2CACHE_ADDR: 129 case DCR_L2CACHE_DATA: 130 case DCR_L2CACHE_STAT: 131 case DCR_L2CACHE_CVER: 132 case DCR_L2CACHE_SNP0: 133 case DCR_L2CACHE_SNP1: 134 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; 135 break; 136 137 case DCR_ISRAM0_SB0CR: 138 case DCR_ISRAM0_SB1CR: 139 case DCR_ISRAM0_SB2CR: 140 case DCR_ISRAM0_SB3CR: 141 case DCR_ISRAM0_BEAR: 142 case DCR_ISRAM0_BESR0: 143 case DCR_ISRAM0_BESR1: 144 case DCR_ISRAM0_PMEG: 145 case DCR_ISRAM0_CID: 146 case DCR_ISRAM0_REVID: 147 case DCR_ISRAM0_DPC: 148 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; 149 break; 150 151 default: 152 break; 153 } 154 155 return ret; 156 } 157 158 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) 159 { 160 /*ppc4xx_l2sram_t *l2sram = opaque;*/ 161 /* FIXME: Actually handle L2 cache mapping */ 162 163 switch (dcrn) { 164 case DCR_L2CACHE_CFG: 165 case DCR_L2CACHE_CMD: 166 case DCR_L2CACHE_ADDR: 167 case DCR_L2CACHE_DATA: 168 case DCR_L2CACHE_STAT: 169 case DCR_L2CACHE_CVER: 170 case DCR_L2CACHE_SNP0: 171 case DCR_L2CACHE_SNP1: 172 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ 173 break; 174 175 case DCR_ISRAM0_SB0CR: 176 case DCR_ISRAM0_SB1CR: 177 case DCR_ISRAM0_SB2CR: 178 case DCR_ISRAM0_SB3CR: 179 case DCR_ISRAM0_BEAR: 180 case DCR_ISRAM0_BESR0: 181 case DCR_ISRAM0_BESR1: 182 case DCR_ISRAM0_PMEG: 183 case DCR_ISRAM0_CID: 184 case DCR_ISRAM0_REVID: 185 case DCR_ISRAM0_DPC: 186 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ 187 break; 188 189 case DCR_ISRAM1_SB0CR: 190 case DCR_ISRAM1_BEAR: 191 case DCR_ISRAM1_BESR0: 192 case DCR_ISRAM1_BESR1: 193 case DCR_ISRAM1_PMEG: 194 case DCR_ISRAM1_CID: 195 case DCR_ISRAM1_REVID: 196 case DCR_ISRAM1_DPC: 197 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ 198 break; 199 } 200 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 201 } 202 203 static void l2sram_reset(void *opaque) 204 { 205 ppc4xx_l2sram_t *l2sram = opaque; 206 207 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); 208 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; 209 memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); 210 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 211 } 212 213 void ppc4xx_l2sram_init(CPUPPCState *env) 214 { 215 ppc4xx_l2sram_t *l2sram; 216 217 l2sram = g_malloc0(sizeof(*l2sram)); 218 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ 219 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", 220 64 * KiB, &error_abort); 221 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", 222 64 * KiB, &error_abort); 223 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", 224 64 * KiB, &error_abort); 225 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", 226 64 * KiB, &error_abort); 227 qemu_register_reset(&l2sram_reset, l2sram); 228 ppc_dcr_register(env, DCR_L2CACHE_CFG, 229 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 230 ppc_dcr_register(env, DCR_L2CACHE_CMD, 231 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 232 ppc_dcr_register(env, DCR_L2CACHE_ADDR, 233 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 234 ppc_dcr_register(env, DCR_L2CACHE_DATA, 235 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 236 ppc_dcr_register(env, DCR_L2CACHE_STAT, 237 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 238 ppc_dcr_register(env, DCR_L2CACHE_CVER, 239 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 240 ppc_dcr_register(env, DCR_L2CACHE_SNP0, 241 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 242 ppc_dcr_register(env, DCR_L2CACHE_SNP1, 243 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 244 245 ppc_dcr_register(env, DCR_ISRAM0_SB0CR, 246 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 247 ppc_dcr_register(env, DCR_ISRAM0_SB1CR, 248 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 249 ppc_dcr_register(env, DCR_ISRAM0_SB2CR, 250 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 251 ppc_dcr_register(env, DCR_ISRAM0_SB3CR, 252 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 253 ppc_dcr_register(env, DCR_ISRAM0_PMEG, 254 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 255 ppc_dcr_register(env, DCR_ISRAM0_DPC, 256 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 257 258 ppc_dcr_register(env, DCR_ISRAM1_SB0CR, 259 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 260 ppc_dcr_register(env, DCR_ISRAM1_PMEG, 261 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 262 ppc_dcr_register(env, DCR_ISRAM1_DPC, 263 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 264 } 265 266 /*****************************************************************************/ 267 /* Clocking Power on Reset */ 268 enum { 269 CPR0_CFGADDR = 0xC, 270 CPR0_CFGDATA = 0xD, 271 272 CPR0_PLLD = 0x060, 273 CPR0_PLBED = 0x080, 274 CPR0_OPBD = 0x0C0, 275 CPR0_PERD = 0x0E0, 276 CPR0_AHBD = 0x100, 277 }; 278 279 typedef struct ppc4xx_cpr_t { 280 uint32_t addr; 281 } ppc4xx_cpr_t; 282 283 static uint32_t dcr_read_cpr(void *opaque, int dcrn) 284 { 285 ppc4xx_cpr_t *cpr = opaque; 286 uint32_t ret = 0; 287 288 switch (dcrn) { 289 case CPR0_CFGADDR: 290 ret = cpr->addr; 291 break; 292 case CPR0_CFGDATA: 293 switch (cpr->addr) { 294 case CPR0_PLLD: 295 ret = (0xb5 << 24) | (1 << 16) | (9 << 8); 296 break; 297 case CPR0_PLBED: 298 ret = (5 << 24); 299 break; 300 case CPR0_OPBD: 301 ret = (2 << 24); 302 break; 303 case CPR0_PERD: 304 case CPR0_AHBD: 305 ret = (1 << 24); 306 break; 307 default: 308 break; 309 } 310 break; 311 default: 312 break; 313 } 314 315 return ret; 316 } 317 318 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) 319 { 320 ppc4xx_cpr_t *cpr = opaque; 321 322 switch (dcrn) { 323 case CPR0_CFGADDR: 324 cpr->addr = val; 325 break; 326 case CPR0_CFGDATA: 327 break; 328 default: 329 break; 330 } 331 } 332 333 static void ppc4xx_cpr_reset(void *opaque) 334 { 335 ppc4xx_cpr_t *cpr = opaque; 336 337 cpr->addr = 0; 338 } 339 340 void ppc4xx_cpr_init(CPUPPCState *env) 341 { 342 ppc4xx_cpr_t *cpr; 343 344 cpr = g_malloc0(sizeof(*cpr)); 345 ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); 346 ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); 347 qemu_register_reset(ppc4xx_cpr_reset, cpr); 348 } 349 350 /*****************************************************************************/ 351 /* System DCRs */ 352 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; 353 struct ppc4xx_sdr_t { 354 uint32_t addr; 355 }; 356 357 enum { 358 SDR0_CFGADDR = 0x00e, 359 SDR0_CFGDATA, 360 SDR0_STRP0 = 0x020, 361 SDR0_STRP1, 362 SDR0_102 = 0x66, 363 SDR0_103, 364 SDR0_128 = 0x80, 365 SDR0_ECID3 = 0x083, 366 SDR0_DDR0 = 0x0e1, 367 SDR0_USB0 = 0x320, 368 }; 369 370 enum { 371 PESDR0_LOOP = 0x303, 372 PESDR0_RCSSET, 373 PESDR0_RCSSTS, 374 PESDR0_RSTSTA = 0x310, 375 PESDR1_LOOP = 0x343, 376 PESDR1_RCSSET, 377 PESDR1_RCSSTS, 378 PESDR1_RSTSTA = 0x365, 379 }; 380 381 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 382 #define SDR0_DDR0_DDRM_DDR1 0x20000000 383 #define SDR0_DDR0_DDRM_DDR2 0x40000000 384 385 static uint32_t dcr_read_sdr(void *opaque, int dcrn) 386 { 387 ppc4xx_sdr_t *sdr = opaque; 388 uint32_t ret = 0; 389 390 switch (dcrn) { 391 case SDR0_CFGADDR: 392 ret = sdr->addr; 393 break; 394 case SDR0_CFGDATA: 395 switch (sdr->addr) { 396 case SDR0_STRP0: 397 ret = (0xb5 << 8) | (1 << 4) | 9; 398 break; 399 case SDR0_STRP1: 400 ret = (5 << 29) | (2 << 26) | (1 << 24); 401 break; 402 case SDR0_ECID3: 403 ret = 1 << 20; /* No Security/Kasumi support */ 404 break; 405 case SDR0_DDR0: 406 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 407 break; 408 case PESDR0_RCSSET: 409 case PESDR1_RCSSET: 410 ret = (1 << 24) | (1 << 16); 411 break; 412 case PESDR0_RCSSTS: 413 case PESDR1_RCSSTS: 414 ret = (1 << 16) | (1 << 12); 415 break; 416 case PESDR0_RSTSTA: 417 case PESDR1_RSTSTA: 418 ret = 1; 419 break; 420 case PESDR0_LOOP: 421 case PESDR1_LOOP: 422 ret = 1 << 12; 423 break; 424 default: 425 break; 426 } 427 break; 428 default: 429 break; 430 } 431 432 return ret; 433 } 434 435 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) 436 { 437 ppc4xx_sdr_t *sdr = opaque; 438 439 switch (dcrn) { 440 case SDR0_CFGADDR: 441 sdr->addr = val; 442 break; 443 case SDR0_CFGDATA: 444 switch (sdr->addr) { 445 case 0x00: /* B0CR */ 446 break; 447 default: 448 break; 449 } 450 break; 451 default: 452 break; 453 } 454 } 455 456 static void sdr_reset(void *opaque) 457 { 458 ppc4xx_sdr_t *sdr = opaque; 459 460 sdr->addr = 0; 461 } 462 463 void ppc4xx_sdr_init(CPUPPCState *env) 464 { 465 ppc4xx_sdr_t *sdr; 466 467 sdr = g_malloc0(sizeof(*sdr)); 468 qemu_register_reset(&sdr_reset, sdr); 469 ppc_dcr_register(env, SDR0_CFGADDR, 470 sdr, &dcr_read_sdr, &dcr_write_sdr); 471 ppc_dcr_register(env, SDR0_CFGDATA, 472 sdr, &dcr_read_sdr, &dcr_write_sdr); 473 ppc_dcr_register(env, SDR0_102, 474 sdr, &dcr_read_sdr, &dcr_write_sdr); 475 ppc_dcr_register(env, SDR0_103, 476 sdr, &dcr_read_sdr, &dcr_write_sdr); 477 ppc_dcr_register(env, SDR0_128, 478 sdr, &dcr_read_sdr, &dcr_write_sdr); 479 ppc_dcr_register(env, SDR0_USB0, 480 sdr, &dcr_read_sdr, &dcr_write_sdr); 481 } 482 483 /*****************************************************************************/ 484 /* SDRAM controller */ 485 typedef struct ppc440_sdram_t { 486 uint32_t addr; 487 int nbanks; 488 Ppc4xxSdramBank bank[4]; 489 } ppc440_sdram_t; 490 491 enum { 492 SDRAM0_CFGADDR = 0x10, 493 SDRAM0_CFGDATA, 494 SDRAM_R0BAS = 0x40, 495 SDRAM_R1BAS, 496 SDRAM_R2BAS, 497 SDRAM_R3BAS, 498 SDRAM_CONF1HB = 0x45, 499 SDRAM_PLBADDULL = 0x4a, 500 SDRAM_CONF1LL = 0x4b, 501 SDRAM_CONFPATHB = 0x4f, 502 SDRAM_PLBADDUHB = 0x50, 503 }; 504 505 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) 506 { 507 uint32_t bcr; 508 509 switch (ram_size) { 510 case (8 * MiB): 511 bcr = 0xffc0; 512 break; 513 case (16 * MiB): 514 bcr = 0xff80; 515 break; 516 case (32 * MiB): 517 bcr = 0xff00; 518 break; 519 case (64 * MiB): 520 bcr = 0xfe00; 521 break; 522 case (128 * MiB): 523 bcr = 0xfc00; 524 break; 525 case (256 * MiB): 526 bcr = 0xf800; 527 break; 528 case (512 * MiB): 529 bcr = 0xf000; 530 break; 531 case (1 * GiB): 532 bcr = 0xe000; 533 break; 534 case (2 * GiB): 535 bcr = 0xc000; 536 break; 537 case (4 * GiB): 538 bcr = 0x8000; 539 break; 540 default: 541 error_report("invalid RAM size " TARGET_FMT_plx, ram_size); 542 return 0; 543 } 544 bcr |= ram_base >> 2 & 0xffe00000; 545 bcr |= 1; 546 547 return bcr; 548 } 549 550 static inline hwaddr sdram_base(uint32_t bcr) 551 { 552 return (bcr & 0xffe00000) << 2; 553 } 554 555 static uint64_t sdram_size(uint32_t bcr) 556 { 557 uint64_t size; 558 int sh; 559 560 sh = 1024 - ((bcr >> 6) & 0x3ff); 561 size = 8 * MiB * sh; 562 563 return size; 564 } 565 566 static void sdram_set_bcr(ppc440_sdram_t *sdram, int i, 567 uint32_t bcr, int enabled) 568 { 569 if (sdram->bank[i].bcr & 1) { 570 /* First unmap RAM if enabled */ 571 memory_region_del_subregion(get_system_memory(), 572 &sdram->bank[i].container); 573 memory_region_del_subregion(&sdram->bank[i].container, 574 &sdram->bank[i].ram); 575 object_unparent(OBJECT(&sdram->bank[i].container)); 576 } 577 sdram->bank[i].bcr = bcr & 0xffe0ffc1; 578 if (enabled && (bcr & 1)) { 579 memory_region_init(&sdram->bank[i].container, NULL, "sdram-container", 580 sdram_size(bcr)); 581 memory_region_add_subregion(&sdram->bank[i].container, 0, 582 &sdram->bank[i].ram); 583 memory_region_add_subregion(get_system_memory(), 584 sdram_base(bcr), 585 &sdram->bank[i].container); 586 } 587 } 588 589 static void sdram_map_bcr(ppc440_sdram_t *sdram) 590 { 591 int i; 592 593 for (i = 0; i < sdram->nbanks; i++) { 594 if (sdram->bank[i].size != 0) { 595 sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, 596 sdram->bank[i].size), 1); 597 } else { 598 sdram_set_bcr(sdram, i, 0, 0); 599 } 600 } 601 } 602 603 static uint32_t dcr_read_sdram(void *opaque, int dcrn) 604 { 605 ppc440_sdram_t *sdram = opaque; 606 uint32_t ret = 0; 607 608 switch (dcrn) { 609 case SDRAM_R0BAS: 610 case SDRAM_R1BAS: 611 case SDRAM_R2BAS: 612 case SDRAM_R3BAS: 613 if (sdram->bank[dcrn - SDRAM_R0BAS].size) { 614 ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, 615 sdram->bank[dcrn - SDRAM_R0BAS].size); 616 } 617 break; 618 case SDRAM_CONF1HB: 619 case SDRAM_CONF1LL: 620 case SDRAM_CONFPATHB: 621 case SDRAM_PLBADDULL: 622 case SDRAM_PLBADDUHB: 623 break; 624 case SDRAM0_CFGADDR: 625 ret = sdram->addr; 626 break; 627 case SDRAM0_CFGDATA: 628 switch (sdram->addr) { 629 case 0x14: /* SDRAM_MCSTAT (405EX) */ 630 case 0x1F: 631 ret = 0x80000000; 632 break; 633 case 0x21: /* SDRAM_MCOPT2 */ 634 ret = 0x08000000; 635 break; 636 case 0x40: /* SDRAM_MB0CF */ 637 ret = 0x00008001; 638 break; 639 case 0x7A: /* SDRAM_DLCR */ 640 ret = 0x02000000; 641 break; 642 case 0xE1: /* SDR0_DDR0 */ 643 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 644 break; 645 default: 646 break; 647 } 648 break; 649 default: 650 break; 651 } 652 653 return ret; 654 } 655 656 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) 657 { 658 ppc440_sdram_t *sdram = opaque; 659 660 switch (dcrn) { 661 case SDRAM_R0BAS: 662 case SDRAM_R1BAS: 663 case SDRAM_R2BAS: 664 case SDRAM_R3BAS: 665 case SDRAM_CONF1HB: 666 case SDRAM_CONF1LL: 667 case SDRAM_CONFPATHB: 668 case SDRAM_PLBADDULL: 669 case SDRAM_PLBADDUHB: 670 break; 671 case SDRAM0_CFGADDR: 672 sdram->addr = val; 673 break; 674 case SDRAM0_CFGDATA: 675 switch (sdram->addr) { 676 case 0x00: /* B0CR */ 677 break; 678 default: 679 break; 680 } 681 break; 682 default: 683 break; 684 } 685 } 686 687 static void sdram_reset(void *opaque) 688 { 689 ppc440_sdram_t *sdram = opaque; 690 691 sdram->addr = 0; 692 } 693 694 void ppc440_sdram_init(CPUPPCState *env, int nbanks, 695 Ppc4xxSdramBank *ram_banks, 696 int do_init) 697 { 698 ppc440_sdram_t *sdram; 699 int i; 700 701 sdram = g_malloc0(sizeof(*sdram)); 702 sdram->nbanks = nbanks; 703 for (i = 0; i < nbanks; i++) { 704 sdram->bank[i].ram = ram_banks[i].ram; 705 sdram->bank[i].base = ram_banks[i].base; 706 sdram->bank[i].size = ram_banks[i].size; 707 } 708 qemu_register_reset(&sdram_reset, sdram); 709 ppc_dcr_register(env, SDRAM0_CFGADDR, 710 sdram, &dcr_read_sdram, &dcr_write_sdram); 711 ppc_dcr_register(env, SDRAM0_CFGDATA, 712 sdram, &dcr_read_sdram, &dcr_write_sdram); 713 if (do_init) { 714 sdram_map_bcr(sdram); 715 } 716 717 ppc_dcr_register(env, SDRAM_R0BAS, 718 sdram, &dcr_read_sdram, &dcr_write_sdram); 719 ppc_dcr_register(env, SDRAM_R1BAS, 720 sdram, &dcr_read_sdram, &dcr_write_sdram); 721 ppc_dcr_register(env, SDRAM_R2BAS, 722 sdram, &dcr_read_sdram, &dcr_write_sdram); 723 ppc_dcr_register(env, SDRAM_R3BAS, 724 sdram, &dcr_read_sdram, &dcr_write_sdram); 725 ppc_dcr_register(env, SDRAM_CONF1HB, 726 sdram, &dcr_read_sdram, &dcr_write_sdram); 727 ppc_dcr_register(env, SDRAM_PLBADDULL, 728 sdram, &dcr_read_sdram, &dcr_write_sdram); 729 ppc_dcr_register(env, SDRAM_CONF1LL, 730 sdram, &dcr_read_sdram, &dcr_write_sdram); 731 ppc_dcr_register(env, SDRAM_CONFPATHB, 732 sdram, &dcr_read_sdram, &dcr_write_sdram); 733 ppc_dcr_register(env, SDRAM_PLBADDUHB, 734 sdram, &dcr_read_sdram, &dcr_write_sdram); 735 } 736 737 /*****************************************************************************/ 738 /* PLB to AHB bridge */ 739 enum { 740 AHB_TOP = 0xA4, 741 AHB_BOT = 0xA5, 742 }; 743 744 typedef struct ppc4xx_ahb_t { 745 uint32_t top; 746 uint32_t bot; 747 } ppc4xx_ahb_t; 748 749 static uint32_t dcr_read_ahb(void *opaque, int dcrn) 750 { 751 ppc4xx_ahb_t *ahb = opaque; 752 uint32_t ret = 0; 753 754 switch (dcrn) { 755 case AHB_TOP: 756 ret = ahb->top; 757 break; 758 case AHB_BOT: 759 ret = ahb->bot; 760 break; 761 default: 762 break; 763 } 764 765 return ret; 766 } 767 768 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) 769 { 770 ppc4xx_ahb_t *ahb = opaque; 771 772 switch (dcrn) { 773 case AHB_TOP: 774 ahb->top = val; 775 break; 776 case AHB_BOT: 777 ahb->bot = val; 778 break; 779 } 780 } 781 782 static void ppc4xx_ahb_reset(void *opaque) 783 { 784 ppc4xx_ahb_t *ahb = opaque; 785 786 /* No error */ 787 ahb->top = 0; 788 ahb->bot = 0; 789 } 790 791 void ppc4xx_ahb_init(CPUPPCState *env) 792 { 793 ppc4xx_ahb_t *ahb; 794 795 ahb = g_malloc0(sizeof(*ahb)); 796 ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); 797 ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); 798 qemu_register_reset(ppc4xx_ahb_reset, ahb); 799 } 800 801 /*****************************************************************************/ 802 /* DMA controller */ 803 804 #define DMA0_CR_CE (1 << 31) 805 #define DMA0_CR_PW (1 << 26 | 1 << 25) 806 #define DMA0_CR_DAI (1 << 24) 807 #define DMA0_CR_SAI (1 << 23) 808 #define DMA0_CR_DEC (1 << 2) 809 810 enum { 811 DMA0_CR = 0x00, 812 DMA0_CT, 813 DMA0_SAH, 814 DMA0_SAL, 815 DMA0_DAH, 816 DMA0_DAL, 817 DMA0_SGH, 818 DMA0_SGL, 819 820 DMA0_SR = 0x20, 821 DMA0_SGC = 0x23, 822 DMA0_SLP = 0x25, 823 DMA0_POL = 0x26, 824 }; 825 826 typedef struct { 827 uint32_t cr; 828 uint32_t ct; 829 uint64_t sa; 830 uint64_t da; 831 uint64_t sg; 832 } PPC4xxDmaChnl; 833 834 typedef struct { 835 int base; 836 PPC4xxDmaChnl ch[4]; 837 uint32_t sr; 838 } PPC4xxDmaState; 839 840 static uint32_t dcr_read_dma(void *opaque, int dcrn) 841 { 842 PPC4xxDmaState *dma = opaque; 843 uint32_t val = 0; 844 int addr = dcrn - dma->base; 845 int chnl = addr / 8; 846 847 switch (addr) { 848 case 0x00 ... 0x1f: 849 switch (addr % 8) { 850 case DMA0_CR: 851 val = dma->ch[chnl].cr; 852 break; 853 case DMA0_CT: 854 val = dma->ch[chnl].ct; 855 break; 856 case DMA0_SAH: 857 val = dma->ch[chnl].sa >> 32; 858 break; 859 case DMA0_SAL: 860 val = dma->ch[chnl].sa; 861 break; 862 case DMA0_DAH: 863 val = dma->ch[chnl].da >> 32; 864 break; 865 case DMA0_DAL: 866 val = dma->ch[chnl].da; 867 break; 868 case DMA0_SGH: 869 val = dma->ch[chnl].sg >> 32; 870 break; 871 case DMA0_SGL: 872 val = dma->ch[chnl].sg; 873 break; 874 } 875 break; 876 case DMA0_SR: 877 val = dma->sr; 878 break; 879 default: 880 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 881 __func__, dcrn, chnl, addr); 882 } 883 884 return val; 885 } 886 887 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) 888 { 889 PPC4xxDmaState *dma = opaque; 890 int addr = dcrn - dma->base; 891 int chnl = addr / 8; 892 893 switch (addr) { 894 case 0x00 ... 0x1f: 895 switch (addr % 8) { 896 case DMA0_CR: 897 dma->ch[chnl].cr = val; 898 if (val & DMA0_CR_CE) { 899 int count = dma->ch[chnl].ct & 0xffff; 900 901 if (count) { 902 int width, i, sidx, didx; 903 uint8_t *rptr, *wptr; 904 hwaddr rlen, wlen; 905 hwaddr xferlen; 906 907 sidx = didx = 0; 908 width = 1 << ((val & DMA0_CR_PW) >> 25); 909 xferlen = count * width; 910 wlen = rlen = xferlen; 911 rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 912 false); 913 wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 914 true); 915 if (rptr && rlen == xferlen && wptr && wlen == xferlen) { 916 if (!(val & DMA0_CR_DEC) && 917 val & DMA0_CR_SAI && val & DMA0_CR_DAI) { 918 /* optimise common case */ 919 memmove(wptr, rptr, count * width); 920 sidx = didx = count * width; 921 } else { 922 /* do it the slow way */ 923 for (sidx = didx = i = 0; i < count; i++) { 924 uint64_t v = ldn_le_p(rptr + sidx, width); 925 stn_le_p(wptr + didx, width, v); 926 if (val & DMA0_CR_SAI) { 927 sidx += width; 928 } 929 if (val & DMA0_CR_DAI) { 930 didx += width; 931 } 932 } 933 } 934 } 935 if (wptr) { 936 cpu_physical_memory_unmap(wptr, wlen, 1, didx); 937 } 938 if (rptr) { 939 cpu_physical_memory_unmap(rptr, rlen, 0, sidx); 940 } 941 } 942 } 943 break; 944 case DMA0_CT: 945 dma->ch[chnl].ct = val; 946 break; 947 case DMA0_SAH: 948 dma->ch[chnl].sa &= 0xffffffffULL; 949 dma->ch[chnl].sa |= (uint64_t)val << 32; 950 break; 951 case DMA0_SAL: 952 dma->ch[chnl].sa &= 0xffffffff00000000ULL; 953 dma->ch[chnl].sa |= val; 954 break; 955 case DMA0_DAH: 956 dma->ch[chnl].da &= 0xffffffffULL; 957 dma->ch[chnl].da |= (uint64_t)val << 32; 958 break; 959 case DMA0_DAL: 960 dma->ch[chnl].da &= 0xffffffff00000000ULL; 961 dma->ch[chnl].da |= val; 962 break; 963 case DMA0_SGH: 964 dma->ch[chnl].sg &= 0xffffffffULL; 965 dma->ch[chnl].sg |= (uint64_t)val << 32; 966 break; 967 case DMA0_SGL: 968 dma->ch[chnl].sg &= 0xffffffff00000000ULL; 969 dma->ch[chnl].sg |= val; 970 break; 971 } 972 break; 973 case DMA0_SR: 974 dma->sr &= ~val; 975 break; 976 default: 977 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 978 __func__, dcrn, chnl, addr); 979 } 980 } 981 982 static void ppc4xx_dma_reset(void *opaque) 983 { 984 PPC4xxDmaState *dma = opaque; 985 int dma_base = dma->base; 986 987 memset(dma, 0, sizeof(*dma)); 988 dma->base = dma_base; 989 } 990 991 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) 992 { 993 PPC4xxDmaState *dma; 994 int i; 995 996 dma = g_malloc0(sizeof(*dma)); 997 dma->base = dcr_base; 998 qemu_register_reset(&ppc4xx_dma_reset, dma); 999 for (i = 0; i < 4; i++) { 1000 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR, 1001 dma, &dcr_read_dma, &dcr_write_dma); 1002 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT, 1003 dma, &dcr_read_dma, &dcr_write_dma); 1004 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH, 1005 dma, &dcr_read_dma, &dcr_write_dma); 1006 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL, 1007 dma, &dcr_read_dma, &dcr_write_dma); 1008 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH, 1009 dma, &dcr_read_dma, &dcr_write_dma); 1010 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL, 1011 dma, &dcr_read_dma, &dcr_write_dma); 1012 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH, 1013 dma, &dcr_read_dma, &dcr_write_dma); 1014 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL, 1015 dma, &dcr_read_dma, &dcr_write_dma); 1016 } 1017 ppc_dcr_register(env, dcr_base + DMA0_SR, 1018 dma, &dcr_read_dma, &dcr_write_dma); 1019 ppc_dcr_register(env, dcr_base + DMA0_SGC, 1020 dma, &dcr_read_dma, &dcr_write_dma); 1021 ppc_dcr_register(env, dcr_base + DMA0_SLP, 1022 dma, &dcr_read_dma, &dcr_write_dma); 1023 ppc_dcr_register(env, dcr_base + DMA0_POL, 1024 dma, &dcr_read_dma, &dcr_write_dma); 1025 } 1026 1027 /*****************************************************************************/ 1028 /* PCI Express controller */ 1029 /* 1030 * FIXME: This is not complete and does not work, only implemented partially 1031 * to allow firmware and guests to find an empty bus. Cards should use PCI. 1032 */ 1033 #include "hw/pci/pcie_host.h" 1034 1035 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 1036 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST) 1037 1038 struct PPC460EXPCIEState { 1039 PCIExpressHost host; 1040 1041 MemoryRegion iomem; 1042 qemu_irq irq[4]; 1043 int32_t dcrn_base; 1044 1045 uint64_t cfg_base; 1046 uint32_t cfg_mask; 1047 uint64_t msg_base; 1048 uint32_t msg_mask; 1049 uint64_t omr1_base; 1050 uint64_t omr1_mask; 1051 uint64_t omr2_base; 1052 uint64_t omr2_mask; 1053 uint64_t omr3_base; 1054 uint64_t omr3_mask; 1055 uint64_t reg_base; 1056 uint32_t reg_mask; 1057 uint32_t special; 1058 uint32_t cfg; 1059 }; 1060 1061 #define DCRN_PCIE0_BASE 0x100 1062 #define DCRN_PCIE1_BASE 0x120 1063 1064 enum { 1065 PEGPL_CFGBAH = 0x0, 1066 PEGPL_CFGBAL, 1067 PEGPL_CFGMSK, 1068 PEGPL_MSGBAH, 1069 PEGPL_MSGBAL, 1070 PEGPL_MSGMSK, 1071 PEGPL_OMR1BAH, 1072 PEGPL_OMR1BAL, 1073 PEGPL_OMR1MSKH, 1074 PEGPL_OMR1MSKL, 1075 PEGPL_OMR2BAH, 1076 PEGPL_OMR2BAL, 1077 PEGPL_OMR2MSKH, 1078 PEGPL_OMR2MSKL, 1079 PEGPL_OMR3BAH, 1080 PEGPL_OMR3BAL, 1081 PEGPL_OMR3MSKH, 1082 PEGPL_OMR3MSKL, 1083 PEGPL_REGBAH, 1084 PEGPL_REGBAL, 1085 PEGPL_REGMSK, 1086 PEGPL_SPECIAL, 1087 PEGPL_CFG, 1088 }; 1089 1090 static uint32_t dcr_read_pcie(void *opaque, int dcrn) 1091 { 1092 PPC460EXPCIEState *state = opaque; 1093 uint32_t ret = 0; 1094 1095 switch (dcrn - state->dcrn_base) { 1096 case PEGPL_CFGBAH: 1097 ret = state->cfg_base >> 32; 1098 break; 1099 case PEGPL_CFGBAL: 1100 ret = state->cfg_base; 1101 break; 1102 case PEGPL_CFGMSK: 1103 ret = state->cfg_mask; 1104 break; 1105 case PEGPL_MSGBAH: 1106 ret = state->msg_base >> 32; 1107 break; 1108 case PEGPL_MSGBAL: 1109 ret = state->msg_base; 1110 break; 1111 case PEGPL_MSGMSK: 1112 ret = state->msg_mask; 1113 break; 1114 case PEGPL_OMR1BAH: 1115 ret = state->omr1_base >> 32; 1116 break; 1117 case PEGPL_OMR1BAL: 1118 ret = state->omr1_base; 1119 break; 1120 case PEGPL_OMR1MSKH: 1121 ret = state->omr1_mask >> 32; 1122 break; 1123 case PEGPL_OMR1MSKL: 1124 ret = state->omr1_mask; 1125 break; 1126 case PEGPL_OMR2BAH: 1127 ret = state->omr2_base >> 32; 1128 break; 1129 case PEGPL_OMR2BAL: 1130 ret = state->omr2_base; 1131 break; 1132 case PEGPL_OMR2MSKH: 1133 ret = state->omr2_mask >> 32; 1134 break; 1135 case PEGPL_OMR2MSKL: 1136 ret = state->omr3_mask; 1137 break; 1138 case PEGPL_OMR3BAH: 1139 ret = state->omr3_base >> 32; 1140 break; 1141 case PEGPL_OMR3BAL: 1142 ret = state->omr3_base; 1143 break; 1144 case PEGPL_OMR3MSKH: 1145 ret = state->omr3_mask >> 32; 1146 break; 1147 case PEGPL_OMR3MSKL: 1148 ret = state->omr3_mask; 1149 break; 1150 case PEGPL_REGBAH: 1151 ret = state->reg_base >> 32; 1152 break; 1153 case PEGPL_REGBAL: 1154 ret = state->reg_base; 1155 break; 1156 case PEGPL_REGMSK: 1157 ret = state->reg_mask; 1158 break; 1159 case PEGPL_SPECIAL: 1160 ret = state->special; 1161 break; 1162 case PEGPL_CFG: 1163 ret = state->cfg; 1164 break; 1165 } 1166 1167 return ret; 1168 } 1169 1170 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) 1171 { 1172 PPC460EXPCIEState *s = opaque; 1173 uint64_t size; 1174 1175 switch (dcrn - s->dcrn_base) { 1176 case PEGPL_CFGBAH: 1177 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); 1178 break; 1179 case PEGPL_CFGBAL: 1180 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; 1181 break; 1182 case PEGPL_CFGMSK: 1183 s->cfg_mask = val; 1184 size = ~(val & 0xfffffffe) + 1; 1185 /* 1186 * Firmware sets this register to E0000001. Why we are not sure, 1187 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is 1188 * ignored. 1189 */ 1190 if (size > PCIE_MMCFG_SIZE_MAX) { 1191 size = PCIE_MMCFG_SIZE_MAX; 1192 } 1193 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); 1194 break; 1195 case PEGPL_MSGBAH: 1196 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); 1197 break; 1198 case PEGPL_MSGBAL: 1199 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; 1200 break; 1201 case PEGPL_MSGMSK: 1202 s->msg_mask = val; 1203 break; 1204 case PEGPL_OMR1BAH: 1205 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); 1206 break; 1207 case PEGPL_OMR1BAL: 1208 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; 1209 break; 1210 case PEGPL_OMR1MSKH: 1211 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); 1212 break; 1213 case PEGPL_OMR1MSKL: 1214 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; 1215 break; 1216 case PEGPL_OMR2BAH: 1217 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); 1218 break; 1219 case PEGPL_OMR2BAL: 1220 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; 1221 break; 1222 case PEGPL_OMR2MSKH: 1223 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); 1224 break; 1225 case PEGPL_OMR2MSKL: 1226 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; 1227 break; 1228 case PEGPL_OMR3BAH: 1229 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); 1230 break; 1231 case PEGPL_OMR3BAL: 1232 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; 1233 break; 1234 case PEGPL_OMR3MSKH: 1235 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); 1236 break; 1237 case PEGPL_OMR3MSKL: 1238 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; 1239 break; 1240 case PEGPL_REGBAH: 1241 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); 1242 break; 1243 case PEGPL_REGBAL: 1244 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; 1245 break; 1246 case PEGPL_REGMSK: 1247 s->reg_mask = val; 1248 /* FIXME: how is size encoded? */ 1249 size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); 1250 break; 1251 case PEGPL_SPECIAL: 1252 s->special = val; 1253 break; 1254 case PEGPL_CFG: 1255 s->cfg = val; 1256 break; 1257 } 1258 } 1259 1260 static void ppc460ex_set_irq(void *opaque, int irq_num, int level) 1261 { 1262 PPC460EXPCIEState *s = opaque; 1263 qemu_set_irq(s->irq[irq_num], level); 1264 } 1265 1266 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) 1267 { 1268 PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); 1269 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 1270 int i, id; 1271 char buf[16]; 1272 1273 switch (s->dcrn_base) { 1274 case DCRN_PCIE0_BASE: 1275 id = 0; 1276 break; 1277 case DCRN_PCIE1_BASE: 1278 id = 1; 1279 break; 1280 default: 1281 error_setg(errp, "invalid PCIe DCRN base"); 1282 return; 1283 } 1284 snprintf(buf, sizeof(buf), "pcie%d-io", id); 1285 memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); 1286 for (i = 0; i < 4; i++) { 1287 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1288 } 1289 snprintf(buf, sizeof(buf), "pcie.%d", id); 1290 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, 1291 pci_swizzle_map_irq_fn, s, &s->iomem, 1292 get_system_io(), 0, 4, TYPE_PCIE_BUS); 1293 } 1294 1295 static Property ppc460ex_pcie_props[] = { 1296 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), 1297 DEFINE_PROP_END_OF_LIST(), 1298 }; 1299 1300 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) 1301 { 1302 DeviceClass *dc = DEVICE_CLASS(klass); 1303 1304 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1305 dc->realize = ppc460ex_pcie_realize; 1306 device_class_set_props(dc, ppc460ex_pcie_props); 1307 dc->hotpluggable = false; 1308 } 1309 1310 static const TypeInfo ppc460ex_pcie_host_info = { 1311 .name = TYPE_PPC460EX_PCIE_HOST, 1312 .parent = TYPE_PCIE_HOST_BRIDGE, 1313 .instance_size = sizeof(PPC460EXPCIEState), 1314 .class_init = ppc460ex_pcie_class_init, 1315 }; 1316 1317 static void ppc460ex_pcie_register(void) 1318 { 1319 type_register_static(&ppc460ex_pcie_host_info); 1320 } 1321 1322 type_init(ppc460ex_pcie_register) 1323 1324 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env) 1325 { 1326 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, 1327 &dcr_read_pcie, &dcr_write_pcie); 1328 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, 1329 &dcr_read_pcie, &dcr_write_pcie); 1330 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, 1331 &dcr_read_pcie, &dcr_write_pcie); 1332 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, 1333 &dcr_read_pcie, &dcr_write_pcie); 1334 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, 1335 &dcr_read_pcie, &dcr_write_pcie); 1336 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, 1337 &dcr_read_pcie, &dcr_write_pcie); 1338 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, 1339 &dcr_read_pcie, &dcr_write_pcie); 1340 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, 1341 &dcr_read_pcie, &dcr_write_pcie); 1342 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, 1343 &dcr_read_pcie, &dcr_write_pcie); 1344 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, 1345 &dcr_read_pcie, &dcr_write_pcie); 1346 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, 1347 &dcr_read_pcie, &dcr_write_pcie); 1348 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, 1349 &dcr_read_pcie, &dcr_write_pcie); 1350 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, 1351 &dcr_read_pcie, &dcr_write_pcie); 1352 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, 1353 &dcr_read_pcie, &dcr_write_pcie); 1354 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, 1355 &dcr_read_pcie, &dcr_write_pcie); 1356 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, 1357 &dcr_read_pcie, &dcr_write_pcie); 1358 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, 1359 &dcr_read_pcie, &dcr_write_pcie); 1360 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, 1361 &dcr_read_pcie, &dcr_write_pcie); 1362 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, 1363 &dcr_read_pcie, &dcr_write_pcie); 1364 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, 1365 &dcr_read_pcie, &dcr_write_pcie); 1366 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, 1367 &dcr_read_pcie, &dcr_write_pcie); 1368 ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, 1369 &dcr_read_pcie, &dcr_write_pcie); 1370 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, 1371 &dcr_read_pcie, &dcr_write_pcie); 1372 } 1373 1374 void ppc460ex_pcie_init(CPUPPCState *env) 1375 { 1376 DeviceState *dev; 1377 1378 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1379 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1380 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1381 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1382 1383 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1384 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1385 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1386 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1387 } 1388