1 /* 2 * QEMU PowerPC 440 embedded processors emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This work is licensed under the GNU GPL license version 2 or later. 8 * 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/units.h" 13 #include "qapi/error.h" 14 #include "qemu/log.h" 15 #include "hw/irq.h" 16 #include "hw/ppc/ppc4xx.h" 17 #include "hw/qdev-properties.h" 18 #include "hw/pci/pci.h" 19 #include "sysemu/reset.h" 20 #include "cpu.h" 21 #include "ppc440.h" 22 23 /*****************************************************************************/ 24 /* L2 Cache as SRAM */ 25 /* FIXME:fix names */ 26 enum { 27 DCR_L2CACHE_BASE = 0x30, 28 DCR_L2CACHE_CFG = DCR_L2CACHE_BASE, 29 DCR_L2CACHE_CMD, 30 DCR_L2CACHE_ADDR, 31 DCR_L2CACHE_DATA, 32 DCR_L2CACHE_STAT, 33 DCR_L2CACHE_CVER, 34 DCR_L2CACHE_SNP0, 35 DCR_L2CACHE_SNP1, 36 DCR_L2CACHE_END = DCR_L2CACHE_SNP1, 37 }; 38 39 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ 40 enum { 41 DCR_ISRAM0_BASE = 0x20, 42 DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE, 43 DCR_ISRAM0_SB1CR, 44 DCR_ISRAM0_SB2CR, 45 DCR_ISRAM0_SB3CR, 46 DCR_ISRAM0_BEAR, 47 DCR_ISRAM0_BESR0, 48 DCR_ISRAM0_BESR1, 49 DCR_ISRAM0_PMEG, 50 DCR_ISRAM0_CID, 51 DCR_ISRAM0_REVID, 52 DCR_ISRAM0_DPC, 53 DCR_ISRAM0_END = DCR_ISRAM0_DPC 54 }; 55 56 enum { 57 DCR_ISRAM1_BASE = 0xb0, 58 DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE, 59 /* single bank */ 60 DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04, 61 DCR_ISRAM1_BESR0, 62 DCR_ISRAM1_BESR1, 63 DCR_ISRAM1_PMEG, 64 DCR_ISRAM1_CID, 65 DCR_ISRAM1_REVID, 66 DCR_ISRAM1_DPC, 67 DCR_ISRAM1_END = DCR_ISRAM1_DPC 68 }; 69 70 typedef struct ppc4xx_l2sram_t { 71 MemoryRegion bank[4]; 72 uint32_t l2cache[8]; 73 uint32_t isram0[11]; 74 } ppc4xx_l2sram_t; 75 76 #ifdef MAP_L2SRAM 77 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, 78 uint32_t isarc, uint32_t isacntl, 79 uint32_t dsarc, uint32_t dsacntl) 80 { 81 if (l2sram->isarc != isarc || 82 (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 83 if (l2sram->isacntl & 0x80000000) { 84 /* Unmap previously assigned memory region */ 85 memory_region_del_subregion(get_system_memory(), 86 &l2sram->isarc_ram); 87 } 88 if (isacntl & 0x80000000) { 89 /* Map new instruction memory region */ 90 memory_region_add_subregion(get_system_memory(), isarc, 91 &l2sram->isarc_ram); 92 } 93 } 94 if (l2sram->dsarc != dsarc || 95 (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 96 if (l2sram->dsacntl & 0x80000000) { 97 /* Beware not to unmap the region we just mapped */ 98 if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) { 99 /* Unmap previously assigned memory region */ 100 memory_region_del_subregion(get_system_memory(), 101 &l2sram->dsarc_ram); 102 } 103 } 104 if (dsacntl & 0x80000000) { 105 /* Beware not to remap the region we just mapped */ 106 if (!(isacntl & 0x80000000) || dsarc != isarc) { 107 /* Map new data memory region */ 108 memory_region_add_subregion(get_system_memory(), dsarc, 109 &l2sram->dsarc_ram); 110 } 111 } 112 } 113 } 114 #endif 115 116 static uint32_t dcr_read_l2sram(void *opaque, int dcrn) 117 { 118 ppc4xx_l2sram_t *l2sram = opaque; 119 uint32_t ret = 0; 120 121 switch (dcrn) { 122 case DCR_L2CACHE_CFG: 123 case DCR_L2CACHE_CMD: 124 case DCR_L2CACHE_ADDR: 125 case DCR_L2CACHE_DATA: 126 case DCR_L2CACHE_STAT: 127 case DCR_L2CACHE_CVER: 128 case DCR_L2CACHE_SNP0: 129 case DCR_L2CACHE_SNP1: 130 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; 131 break; 132 133 case DCR_ISRAM0_SB0CR: 134 case DCR_ISRAM0_SB1CR: 135 case DCR_ISRAM0_SB2CR: 136 case DCR_ISRAM0_SB3CR: 137 case DCR_ISRAM0_BEAR: 138 case DCR_ISRAM0_BESR0: 139 case DCR_ISRAM0_BESR1: 140 case DCR_ISRAM0_PMEG: 141 case DCR_ISRAM0_CID: 142 case DCR_ISRAM0_REVID: 143 case DCR_ISRAM0_DPC: 144 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; 145 break; 146 147 default: 148 break; 149 } 150 151 return ret; 152 } 153 154 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) 155 { 156 /*ppc4xx_l2sram_t *l2sram = opaque;*/ 157 /* FIXME: Actually handle L2 cache mapping */ 158 159 switch (dcrn) { 160 case DCR_L2CACHE_CFG: 161 case DCR_L2CACHE_CMD: 162 case DCR_L2CACHE_ADDR: 163 case DCR_L2CACHE_DATA: 164 case DCR_L2CACHE_STAT: 165 case DCR_L2CACHE_CVER: 166 case DCR_L2CACHE_SNP0: 167 case DCR_L2CACHE_SNP1: 168 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ 169 break; 170 171 case DCR_ISRAM0_SB0CR: 172 case DCR_ISRAM0_SB1CR: 173 case DCR_ISRAM0_SB2CR: 174 case DCR_ISRAM0_SB3CR: 175 case DCR_ISRAM0_BEAR: 176 case DCR_ISRAM0_BESR0: 177 case DCR_ISRAM0_BESR1: 178 case DCR_ISRAM0_PMEG: 179 case DCR_ISRAM0_CID: 180 case DCR_ISRAM0_REVID: 181 case DCR_ISRAM0_DPC: 182 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ 183 break; 184 185 case DCR_ISRAM1_SB0CR: 186 case DCR_ISRAM1_BEAR: 187 case DCR_ISRAM1_BESR0: 188 case DCR_ISRAM1_BESR1: 189 case DCR_ISRAM1_PMEG: 190 case DCR_ISRAM1_CID: 191 case DCR_ISRAM1_REVID: 192 case DCR_ISRAM1_DPC: 193 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ 194 break; 195 } 196 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 197 } 198 199 static void l2sram_reset(void *opaque) 200 { 201 ppc4xx_l2sram_t *l2sram = opaque; 202 203 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); 204 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; 205 memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); 206 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 207 } 208 209 void ppc4xx_l2sram_init(CPUPPCState *env) 210 { 211 ppc4xx_l2sram_t *l2sram; 212 213 l2sram = g_malloc0(sizeof(*l2sram)); 214 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ 215 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", 216 64 * KiB, &error_abort); 217 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", 218 64 * KiB, &error_abort); 219 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", 220 64 * KiB, &error_abort); 221 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", 222 64 * KiB, &error_abort); 223 qemu_register_reset(&l2sram_reset, l2sram); 224 ppc_dcr_register(env, DCR_L2CACHE_CFG, 225 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 226 ppc_dcr_register(env, DCR_L2CACHE_CMD, 227 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 228 ppc_dcr_register(env, DCR_L2CACHE_ADDR, 229 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 230 ppc_dcr_register(env, DCR_L2CACHE_DATA, 231 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 232 ppc_dcr_register(env, DCR_L2CACHE_STAT, 233 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 234 ppc_dcr_register(env, DCR_L2CACHE_CVER, 235 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 236 ppc_dcr_register(env, DCR_L2CACHE_SNP0, 237 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 238 ppc_dcr_register(env, DCR_L2CACHE_SNP1, 239 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 240 241 ppc_dcr_register(env, DCR_ISRAM0_SB0CR, 242 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 243 ppc_dcr_register(env, DCR_ISRAM0_SB1CR, 244 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 245 ppc_dcr_register(env, DCR_ISRAM0_SB2CR, 246 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 247 ppc_dcr_register(env, DCR_ISRAM0_SB3CR, 248 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 249 ppc_dcr_register(env, DCR_ISRAM0_PMEG, 250 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 251 ppc_dcr_register(env, DCR_ISRAM0_DPC, 252 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 253 254 ppc_dcr_register(env, DCR_ISRAM1_SB0CR, 255 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 256 ppc_dcr_register(env, DCR_ISRAM1_PMEG, 257 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 258 ppc_dcr_register(env, DCR_ISRAM1_DPC, 259 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 260 } 261 262 /*****************************************************************************/ 263 /* Clocking Power on Reset */ 264 enum { 265 CPR0_CFGADDR = 0xC, 266 CPR0_CFGDATA = 0xD, 267 268 CPR0_PLLD = 0x060, 269 CPR0_PLBED = 0x080, 270 CPR0_OPBD = 0x0C0, 271 CPR0_PERD = 0x0E0, 272 CPR0_AHBD = 0x100, 273 }; 274 275 typedef struct ppc4xx_cpr_t { 276 uint32_t addr; 277 } ppc4xx_cpr_t; 278 279 static uint32_t dcr_read_cpr(void *opaque, int dcrn) 280 { 281 ppc4xx_cpr_t *cpr = opaque; 282 uint32_t ret = 0; 283 284 switch (dcrn) { 285 case CPR0_CFGADDR: 286 ret = cpr->addr; 287 break; 288 case CPR0_CFGDATA: 289 switch (cpr->addr) { 290 case CPR0_PLLD: 291 ret = (0xb5 << 24) | (1 << 16) | (9 << 8); 292 break; 293 case CPR0_PLBED: 294 ret = (5 << 24); 295 break; 296 case CPR0_OPBD: 297 ret = (2 << 24); 298 break; 299 case CPR0_PERD: 300 case CPR0_AHBD: 301 ret = (1 << 24); 302 break; 303 default: 304 break; 305 } 306 break; 307 default: 308 break; 309 } 310 311 return ret; 312 } 313 314 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) 315 { 316 ppc4xx_cpr_t *cpr = opaque; 317 318 switch (dcrn) { 319 case CPR0_CFGADDR: 320 cpr->addr = val; 321 break; 322 case CPR0_CFGDATA: 323 break; 324 default: 325 break; 326 } 327 } 328 329 static void ppc4xx_cpr_reset(void *opaque) 330 { 331 ppc4xx_cpr_t *cpr = opaque; 332 333 cpr->addr = 0; 334 } 335 336 void ppc4xx_cpr_init(CPUPPCState *env) 337 { 338 ppc4xx_cpr_t *cpr; 339 340 cpr = g_malloc0(sizeof(*cpr)); 341 ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); 342 ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); 343 qemu_register_reset(ppc4xx_cpr_reset, cpr); 344 } 345 346 /*****************************************************************************/ 347 /* System DCRs */ 348 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; 349 struct ppc4xx_sdr_t { 350 uint32_t addr; 351 }; 352 353 enum { 354 SDR0_CFGADDR = 0x00e, 355 SDR0_CFGDATA, 356 SDR0_STRP0 = 0x020, 357 SDR0_STRP1, 358 SDR0_102 = 0x66, 359 SDR0_103, 360 SDR0_128 = 0x80, 361 SDR0_ECID3 = 0x083, 362 SDR0_DDR0 = 0x0e1, 363 SDR0_USB0 = 0x320, 364 }; 365 366 enum { 367 PESDR0_LOOP = 0x303, 368 PESDR0_RCSSET, 369 PESDR0_RCSSTS, 370 PESDR0_RSTSTA = 0x310, 371 PESDR1_LOOP = 0x343, 372 PESDR1_RCSSET, 373 PESDR1_RCSSTS, 374 PESDR1_RSTSTA = 0x365, 375 }; 376 377 static uint32_t dcr_read_sdr(void *opaque, int dcrn) 378 { 379 ppc4xx_sdr_t *sdr = opaque; 380 uint32_t ret = 0; 381 382 switch (dcrn) { 383 case SDR0_CFGADDR: 384 ret = sdr->addr; 385 break; 386 case SDR0_CFGDATA: 387 switch (sdr->addr) { 388 case SDR0_STRP0: 389 ret = (0xb5 << 8) | (1 << 4) | 9; 390 break; 391 case SDR0_STRP1: 392 ret = (5 << 29) | (2 << 26) | (1 << 24); 393 break; 394 case SDR0_ECID3: 395 ret = 1 << 20; /* No Security/Kasumi support */ 396 break; 397 case SDR0_DDR0: 398 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 399 break; 400 case PESDR0_RCSSET: 401 case PESDR1_RCSSET: 402 ret = (1 << 24) | (1 << 16); 403 break; 404 case PESDR0_RCSSTS: 405 case PESDR1_RCSSTS: 406 ret = (1 << 16) | (1 << 12); 407 break; 408 case PESDR0_RSTSTA: 409 case PESDR1_RSTSTA: 410 ret = 1; 411 break; 412 case PESDR0_LOOP: 413 case PESDR1_LOOP: 414 ret = 1 << 12; 415 break; 416 default: 417 break; 418 } 419 break; 420 default: 421 break; 422 } 423 424 return ret; 425 } 426 427 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) 428 { 429 ppc4xx_sdr_t *sdr = opaque; 430 431 switch (dcrn) { 432 case SDR0_CFGADDR: 433 sdr->addr = val; 434 break; 435 case SDR0_CFGDATA: 436 switch (sdr->addr) { 437 case 0x00: /* B0CR */ 438 break; 439 default: 440 break; 441 } 442 break; 443 default: 444 break; 445 } 446 } 447 448 static void sdr_reset(void *opaque) 449 { 450 ppc4xx_sdr_t *sdr = opaque; 451 452 sdr->addr = 0; 453 } 454 455 void ppc4xx_sdr_init(CPUPPCState *env) 456 { 457 ppc4xx_sdr_t *sdr; 458 459 sdr = g_malloc0(sizeof(*sdr)); 460 qemu_register_reset(&sdr_reset, sdr); 461 ppc_dcr_register(env, SDR0_CFGADDR, 462 sdr, &dcr_read_sdr, &dcr_write_sdr); 463 ppc_dcr_register(env, SDR0_CFGDATA, 464 sdr, &dcr_read_sdr, &dcr_write_sdr); 465 ppc_dcr_register(env, SDR0_102, 466 sdr, &dcr_read_sdr, &dcr_write_sdr); 467 ppc_dcr_register(env, SDR0_103, 468 sdr, &dcr_read_sdr, &dcr_write_sdr); 469 ppc_dcr_register(env, SDR0_128, 470 sdr, &dcr_read_sdr, &dcr_write_sdr); 471 ppc_dcr_register(env, SDR0_USB0, 472 sdr, &dcr_read_sdr, &dcr_write_sdr); 473 } 474 475 /*****************************************************************************/ 476 /* PLB to AHB bridge */ 477 enum { 478 AHB_TOP = 0xA4, 479 AHB_BOT = 0xA5, 480 }; 481 482 typedef struct ppc4xx_ahb_t { 483 uint32_t top; 484 uint32_t bot; 485 } ppc4xx_ahb_t; 486 487 static uint32_t dcr_read_ahb(void *opaque, int dcrn) 488 { 489 ppc4xx_ahb_t *ahb = opaque; 490 uint32_t ret = 0; 491 492 switch (dcrn) { 493 case AHB_TOP: 494 ret = ahb->top; 495 break; 496 case AHB_BOT: 497 ret = ahb->bot; 498 break; 499 default: 500 break; 501 } 502 503 return ret; 504 } 505 506 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) 507 { 508 ppc4xx_ahb_t *ahb = opaque; 509 510 switch (dcrn) { 511 case AHB_TOP: 512 ahb->top = val; 513 break; 514 case AHB_BOT: 515 ahb->bot = val; 516 break; 517 } 518 } 519 520 static void ppc4xx_ahb_reset(void *opaque) 521 { 522 ppc4xx_ahb_t *ahb = opaque; 523 524 /* No error */ 525 ahb->top = 0; 526 ahb->bot = 0; 527 } 528 529 void ppc4xx_ahb_init(CPUPPCState *env) 530 { 531 ppc4xx_ahb_t *ahb; 532 533 ahb = g_malloc0(sizeof(*ahb)); 534 ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); 535 ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); 536 qemu_register_reset(ppc4xx_ahb_reset, ahb); 537 } 538 539 /*****************************************************************************/ 540 /* DMA controller */ 541 542 #define DMA0_CR_CE (1 << 31) 543 #define DMA0_CR_PW (1 << 26 | 1 << 25) 544 #define DMA0_CR_DAI (1 << 24) 545 #define DMA0_CR_SAI (1 << 23) 546 #define DMA0_CR_DEC (1 << 2) 547 548 enum { 549 DMA0_CR = 0x00, 550 DMA0_CT, 551 DMA0_SAH, 552 DMA0_SAL, 553 DMA0_DAH, 554 DMA0_DAL, 555 DMA0_SGH, 556 DMA0_SGL, 557 558 DMA0_SR = 0x20, 559 DMA0_SGC = 0x23, 560 DMA0_SLP = 0x25, 561 DMA0_POL = 0x26, 562 }; 563 564 typedef struct { 565 uint32_t cr; 566 uint32_t ct; 567 uint64_t sa; 568 uint64_t da; 569 uint64_t sg; 570 } PPC4xxDmaChnl; 571 572 typedef struct { 573 int base; 574 PPC4xxDmaChnl ch[4]; 575 uint32_t sr; 576 } PPC4xxDmaState; 577 578 static uint32_t dcr_read_dma(void *opaque, int dcrn) 579 { 580 PPC4xxDmaState *dma = opaque; 581 uint32_t val = 0; 582 int addr = dcrn - dma->base; 583 int chnl = addr / 8; 584 585 switch (addr) { 586 case 0x00 ... 0x1f: 587 switch (addr % 8) { 588 case DMA0_CR: 589 val = dma->ch[chnl].cr; 590 break; 591 case DMA0_CT: 592 val = dma->ch[chnl].ct; 593 break; 594 case DMA0_SAH: 595 val = dma->ch[chnl].sa >> 32; 596 break; 597 case DMA0_SAL: 598 val = dma->ch[chnl].sa; 599 break; 600 case DMA0_DAH: 601 val = dma->ch[chnl].da >> 32; 602 break; 603 case DMA0_DAL: 604 val = dma->ch[chnl].da; 605 break; 606 case DMA0_SGH: 607 val = dma->ch[chnl].sg >> 32; 608 break; 609 case DMA0_SGL: 610 val = dma->ch[chnl].sg; 611 break; 612 } 613 break; 614 case DMA0_SR: 615 val = dma->sr; 616 break; 617 default: 618 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 619 __func__, dcrn, chnl, addr); 620 } 621 622 return val; 623 } 624 625 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) 626 { 627 PPC4xxDmaState *dma = opaque; 628 int addr = dcrn - dma->base; 629 int chnl = addr / 8; 630 631 switch (addr) { 632 case 0x00 ... 0x1f: 633 switch (addr % 8) { 634 case DMA0_CR: 635 dma->ch[chnl].cr = val; 636 if (val & DMA0_CR_CE) { 637 int count = dma->ch[chnl].ct & 0xffff; 638 639 if (count) { 640 int width, i, sidx, didx; 641 uint8_t *rptr, *wptr; 642 hwaddr rlen, wlen; 643 hwaddr xferlen; 644 645 sidx = didx = 0; 646 width = 1 << ((val & DMA0_CR_PW) >> 25); 647 xferlen = count * width; 648 wlen = rlen = xferlen; 649 rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 650 false); 651 wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 652 true); 653 if (rptr && rlen == xferlen && wptr && wlen == xferlen) { 654 if (!(val & DMA0_CR_DEC) && 655 val & DMA0_CR_SAI && val & DMA0_CR_DAI) { 656 /* optimise common case */ 657 memmove(wptr, rptr, count * width); 658 sidx = didx = count * width; 659 } else { 660 /* do it the slow way */ 661 for (sidx = didx = i = 0; i < count; i++) { 662 uint64_t v = ldn_le_p(rptr + sidx, width); 663 stn_le_p(wptr + didx, width, v); 664 if (val & DMA0_CR_SAI) { 665 sidx += width; 666 } 667 if (val & DMA0_CR_DAI) { 668 didx += width; 669 } 670 } 671 } 672 } 673 if (wptr) { 674 cpu_physical_memory_unmap(wptr, wlen, 1, didx); 675 } 676 if (rptr) { 677 cpu_physical_memory_unmap(rptr, rlen, 0, sidx); 678 } 679 } 680 } 681 break; 682 case DMA0_CT: 683 dma->ch[chnl].ct = val; 684 break; 685 case DMA0_SAH: 686 dma->ch[chnl].sa &= 0xffffffffULL; 687 dma->ch[chnl].sa |= (uint64_t)val << 32; 688 break; 689 case DMA0_SAL: 690 dma->ch[chnl].sa &= 0xffffffff00000000ULL; 691 dma->ch[chnl].sa |= val; 692 break; 693 case DMA0_DAH: 694 dma->ch[chnl].da &= 0xffffffffULL; 695 dma->ch[chnl].da |= (uint64_t)val << 32; 696 break; 697 case DMA0_DAL: 698 dma->ch[chnl].da &= 0xffffffff00000000ULL; 699 dma->ch[chnl].da |= val; 700 break; 701 case DMA0_SGH: 702 dma->ch[chnl].sg &= 0xffffffffULL; 703 dma->ch[chnl].sg |= (uint64_t)val << 32; 704 break; 705 case DMA0_SGL: 706 dma->ch[chnl].sg &= 0xffffffff00000000ULL; 707 dma->ch[chnl].sg |= val; 708 break; 709 } 710 break; 711 case DMA0_SR: 712 dma->sr &= ~val; 713 break; 714 default: 715 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 716 __func__, dcrn, chnl, addr); 717 } 718 } 719 720 static void ppc4xx_dma_reset(void *opaque) 721 { 722 PPC4xxDmaState *dma = opaque; 723 int dma_base = dma->base; 724 725 memset(dma, 0, sizeof(*dma)); 726 dma->base = dma_base; 727 } 728 729 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) 730 { 731 PPC4xxDmaState *dma; 732 int i; 733 734 dma = g_malloc0(sizeof(*dma)); 735 dma->base = dcr_base; 736 qemu_register_reset(&ppc4xx_dma_reset, dma); 737 for (i = 0; i < 4; i++) { 738 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR, 739 dma, &dcr_read_dma, &dcr_write_dma); 740 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT, 741 dma, &dcr_read_dma, &dcr_write_dma); 742 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH, 743 dma, &dcr_read_dma, &dcr_write_dma); 744 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL, 745 dma, &dcr_read_dma, &dcr_write_dma); 746 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH, 747 dma, &dcr_read_dma, &dcr_write_dma); 748 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL, 749 dma, &dcr_read_dma, &dcr_write_dma); 750 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH, 751 dma, &dcr_read_dma, &dcr_write_dma); 752 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL, 753 dma, &dcr_read_dma, &dcr_write_dma); 754 } 755 ppc_dcr_register(env, dcr_base + DMA0_SR, 756 dma, &dcr_read_dma, &dcr_write_dma); 757 ppc_dcr_register(env, dcr_base + DMA0_SGC, 758 dma, &dcr_read_dma, &dcr_write_dma); 759 ppc_dcr_register(env, dcr_base + DMA0_SLP, 760 dma, &dcr_read_dma, &dcr_write_dma); 761 ppc_dcr_register(env, dcr_base + DMA0_POL, 762 dma, &dcr_read_dma, &dcr_write_dma); 763 } 764 765 /*****************************************************************************/ 766 /* PCI Express controller */ 767 /* 768 * FIXME: This is not complete and does not work, only implemented partially 769 * to allow firmware and guests to find an empty bus. Cards should use PCI. 770 */ 771 #include "hw/pci/pcie_host.h" 772 773 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 774 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST) 775 776 struct PPC460EXPCIEState { 777 PCIExpressHost host; 778 779 MemoryRegion iomem; 780 qemu_irq irq[4]; 781 int32_t dcrn_base; 782 783 uint64_t cfg_base; 784 uint32_t cfg_mask; 785 uint64_t msg_base; 786 uint32_t msg_mask; 787 uint64_t omr1_base; 788 uint64_t omr1_mask; 789 uint64_t omr2_base; 790 uint64_t omr2_mask; 791 uint64_t omr3_base; 792 uint64_t omr3_mask; 793 uint64_t reg_base; 794 uint32_t reg_mask; 795 uint32_t special; 796 uint32_t cfg; 797 }; 798 799 #define DCRN_PCIE0_BASE 0x100 800 #define DCRN_PCIE1_BASE 0x120 801 802 enum { 803 PEGPL_CFGBAH = 0x0, 804 PEGPL_CFGBAL, 805 PEGPL_CFGMSK, 806 PEGPL_MSGBAH, 807 PEGPL_MSGBAL, 808 PEGPL_MSGMSK, 809 PEGPL_OMR1BAH, 810 PEGPL_OMR1BAL, 811 PEGPL_OMR1MSKH, 812 PEGPL_OMR1MSKL, 813 PEGPL_OMR2BAH, 814 PEGPL_OMR2BAL, 815 PEGPL_OMR2MSKH, 816 PEGPL_OMR2MSKL, 817 PEGPL_OMR3BAH, 818 PEGPL_OMR3BAL, 819 PEGPL_OMR3MSKH, 820 PEGPL_OMR3MSKL, 821 PEGPL_REGBAH, 822 PEGPL_REGBAL, 823 PEGPL_REGMSK, 824 PEGPL_SPECIAL, 825 PEGPL_CFG, 826 }; 827 828 static uint32_t dcr_read_pcie(void *opaque, int dcrn) 829 { 830 PPC460EXPCIEState *state = opaque; 831 uint32_t ret = 0; 832 833 switch (dcrn - state->dcrn_base) { 834 case PEGPL_CFGBAH: 835 ret = state->cfg_base >> 32; 836 break; 837 case PEGPL_CFGBAL: 838 ret = state->cfg_base; 839 break; 840 case PEGPL_CFGMSK: 841 ret = state->cfg_mask; 842 break; 843 case PEGPL_MSGBAH: 844 ret = state->msg_base >> 32; 845 break; 846 case PEGPL_MSGBAL: 847 ret = state->msg_base; 848 break; 849 case PEGPL_MSGMSK: 850 ret = state->msg_mask; 851 break; 852 case PEGPL_OMR1BAH: 853 ret = state->omr1_base >> 32; 854 break; 855 case PEGPL_OMR1BAL: 856 ret = state->omr1_base; 857 break; 858 case PEGPL_OMR1MSKH: 859 ret = state->omr1_mask >> 32; 860 break; 861 case PEGPL_OMR1MSKL: 862 ret = state->omr1_mask; 863 break; 864 case PEGPL_OMR2BAH: 865 ret = state->omr2_base >> 32; 866 break; 867 case PEGPL_OMR2BAL: 868 ret = state->omr2_base; 869 break; 870 case PEGPL_OMR2MSKH: 871 ret = state->omr2_mask >> 32; 872 break; 873 case PEGPL_OMR2MSKL: 874 ret = state->omr3_mask; 875 break; 876 case PEGPL_OMR3BAH: 877 ret = state->omr3_base >> 32; 878 break; 879 case PEGPL_OMR3BAL: 880 ret = state->omr3_base; 881 break; 882 case PEGPL_OMR3MSKH: 883 ret = state->omr3_mask >> 32; 884 break; 885 case PEGPL_OMR3MSKL: 886 ret = state->omr3_mask; 887 break; 888 case PEGPL_REGBAH: 889 ret = state->reg_base >> 32; 890 break; 891 case PEGPL_REGBAL: 892 ret = state->reg_base; 893 break; 894 case PEGPL_REGMSK: 895 ret = state->reg_mask; 896 break; 897 case PEGPL_SPECIAL: 898 ret = state->special; 899 break; 900 case PEGPL_CFG: 901 ret = state->cfg; 902 break; 903 } 904 905 return ret; 906 } 907 908 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) 909 { 910 PPC460EXPCIEState *s = opaque; 911 uint64_t size; 912 913 switch (dcrn - s->dcrn_base) { 914 case PEGPL_CFGBAH: 915 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); 916 break; 917 case PEGPL_CFGBAL: 918 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; 919 break; 920 case PEGPL_CFGMSK: 921 s->cfg_mask = val; 922 size = ~(val & 0xfffffffe) + 1; 923 /* 924 * Firmware sets this register to E0000001. Why we are not sure, 925 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is 926 * ignored. 927 */ 928 if (size > PCIE_MMCFG_SIZE_MAX) { 929 size = PCIE_MMCFG_SIZE_MAX; 930 } 931 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); 932 break; 933 case PEGPL_MSGBAH: 934 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); 935 break; 936 case PEGPL_MSGBAL: 937 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; 938 break; 939 case PEGPL_MSGMSK: 940 s->msg_mask = val; 941 break; 942 case PEGPL_OMR1BAH: 943 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); 944 break; 945 case PEGPL_OMR1BAL: 946 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; 947 break; 948 case PEGPL_OMR1MSKH: 949 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); 950 break; 951 case PEGPL_OMR1MSKL: 952 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; 953 break; 954 case PEGPL_OMR2BAH: 955 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); 956 break; 957 case PEGPL_OMR2BAL: 958 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; 959 break; 960 case PEGPL_OMR2MSKH: 961 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); 962 break; 963 case PEGPL_OMR2MSKL: 964 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; 965 break; 966 case PEGPL_OMR3BAH: 967 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); 968 break; 969 case PEGPL_OMR3BAL: 970 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; 971 break; 972 case PEGPL_OMR3MSKH: 973 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); 974 break; 975 case PEGPL_OMR3MSKL: 976 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; 977 break; 978 case PEGPL_REGBAH: 979 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); 980 break; 981 case PEGPL_REGBAL: 982 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; 983 break; 984 case PEGPL_REGMSK: 985 s->reg_mask = val; 986 /* FIXME: how is size encoded? */ 987 size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); 988 break; 989 case PEGPL_SPECIAL: 990 s->special = val; 991 break; 992 case PEGPL_CFG: 993 s->cfg = val; 994 break; 995 } 996 } 997 998 static void ppc460ex_set_irq(void *opaque, int irq_num, int level) 999 { 1000 PPC460EXPCIEState *s = opaque; 1001 qemu_set_irq(s->irq[irq_num], level); 1002 } 1003 1004 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) 1005 { 1006 PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); 1007 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 1008 int i, id; 1009 char buf[16]; 1010 1011 switch (s->dcrn_base) { 1012 case DCRN_PCIE0_BASE: 1013 id = 0; 1014 break; 1015 case DCRN_PCIE1_BASE: 1016 id = 1; 1017 break; 1018 default: 1019 error_setg(errp, "invalid PCIe DCRN base"); 1020 return; 1021 } 1022 snprintf(buf, sizeof(buf), "pcie%d-io", id); 1023 memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); 1024 for (i = 0; i < 4; i++) { 1025 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1026 } 1027 snprintf(buf, sizeof(buf), "pcie.%d", id); 1028 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, 1029 pci_swizzle_map_irq_fn, s, &s->iomem, 1030 get_system_io(), 0, 4, TYPE_PCIE_BUS); 1031 } 1032 1033 static Property ppc460ex_pcie_props[] = { 1034 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), 1035 DEFINE_PROP_END_OF_LIST(), 1036 }; 1037 1038 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) 1039 { 1040 DeviceClass *dc = DEVICE_CLASS(klass); 1041 1042 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1043 dc->realize = ppc460ex_pcie_realize; 1044 device_class_set_props(dc, ppc460ex_pcie_props); 1045 dc->hotpluggable = false; 1046 } 1047 1048 static const TypeInfo ppc460ex_pcie_host_info = { 1049 .name = TYPE_PPC460EX_PCIE_HOST, 1050 .parent = TYPE_PCIE_HOST_BRIDGE, 1051 .instance_size = sizeof(PPC460EXPCIEState), 1052 .class_init = ppc460ex_pcie_class_init, 1053 }; 1054 1055 static void ppc460ex_pcie_register(void) 1056 { 1057 type_register_static(&ppc460ex_pcie_host_info); 1058 } 1059 1060 type_init(ppc460ex_pcie_register) 1061 1062 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env) 1063 { 1064 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, 1065 &dcr_read_pcie, &dcr_write_pcie); 1066 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, 1067 &dcr_read_pcie, &dcr_write_pcie); 1068 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, 1069 &dcr_read_pcie, &dcr_write_pcie); 1070 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, 1071 &dcr_read_pcie, &dcr_write_pcie); 1072 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, 1073 &dcr_read_pcie, &dcr_write_pcie); 1074 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, 1075 &dcr_read_pcie, &dcr_write_pcie); 1076 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, 1077 &dcr_read_pcie, &dcr_write_pcie); 1078 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, 1079 &dcr_read_pcie, &dcr_write_pcie); 1080 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, 1081 &dcr_read_pcie, &dcr_write_pcie); 1082 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, 1083 &dcr_read_pcie, &dcr_write_pcie); 1084 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, 1085 &dcr_read_pcie, &dcr_write_pcie); 1086 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, 1087 &dcr_read_pcie, &dcr_write_pcie); 1088 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, 1089 &dcr_read_pcie, &dcr_write_pcie); 1090 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, 1091 &dcr_read_pcie, &dcr_write_pcie); 1092 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, 1093 &dcr_read_pcie, &dcr_write_pcie); 1094 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, 1095 &dcr_read_pcie, &dcr_write_pcie); 1096 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, 1097 &dcr_read_pcie, &dcr_write_pcie); 1098 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, 1099 &dcr_read_pcie, &dcr_write_pcie); 1100 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, 1101 &dcr_read_pcie, &dcr_write_pcie); 1102 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, 1103 &dcr_read_pcie, &dcr_write_pcie); 1104 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, 1105 &dcr_read_pcie, &dcr_write_pcie); 1106 ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, 1107 &dcr_read_pcie, &dcr_write_pcie); 1108 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, 1109 &dcr_read_pcie, &dcr_write_pcie); 1110 } 1111 1112 void ppc460ex_pcie_init(PowerPCCPU *cpu) 1113 { 1114 DeviceState *dev; 1115 1116 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1117 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1118 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1119 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), &cpu->env); 1120 1121 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1122 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1123 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1124 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), &cpu->env); 1125 } 1126