1 /* 2 * QEMU PowerPC 440 embedded processors emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This work is licensed under the GNU GPL license version 2 or later. 8 * 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/units.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "hw/irq.h" 18 #include "exec/memory.h" 19 #include "cpu.h" 20 #include "hw/ppc/ppc4xx.h" 21 #include "hw/qdev-properties.h" 22 #include "hw/pci/pci.h" 23 #include "sysemu/block-backend.h" 24 #include "sysemu/reset.h" 25 #include "ppc440.h" 26 #include "qom/object.h" 27 #include "trace.h" 28 29 /*****************************************************************************/ 30 /* L2 Cache as SRAM */ 31 /* FIXME:fix names */ 32 enum { 33 DCR_L2CACHE_BASE = 0x30, 34 DCR_L2CACHE_CFG = DCR_L2CACHE_BASE, 35 DCR_L2CACHE_CMD, 36 DCR_L2CACHE_ADDR, 37 DCR_L2CACHE_DATA, 38 DCR_L2CACHE_STAT, 39 DCR_L2CACHE_CVER, 40 DCR_L2CACHE_SNP0, 41 DCR_L2CACHE_SNP1, 42 DCR_L2CACHE_END = DCR_L2CACHE_SNP1, 43 }; 44 45 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ 46 enum { 47 DCR_ISRAM0_BASE = 0x20, 48 DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE, 49 DCR_ISRAM0_SB1CR, 50 DCR_ISRAM0_SB2CR, 51 DCR_ISRAM0_SB3CR, 52 DCR_ISRAM0_BEAR, 53 DCR_ISRAM0_BESR0, 54 DCR_ISRAM0_BESR1, 55 DCR_ISRAM0_PMEG, 56 DCR_ISRAM0_CID, 57 DCR_ISRAM0_REVID, 58 DCR_ISRAM0_DPC, 59 DCR_ISRAM0_END = DCR_ISRAM0_DPC 60 }; 61 62 enum { 63 DCR_ISRAM1_BASE = 0xb0, 64 DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE, 65 /* single bank */ 66 DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04, 67 DCR_ISRAM1_BESR0, 68 DCR_ISRAM1_BESR1, 69 DCR_ISRAM1_PMEG, 70 DCR_ISRAM1_CID, 71 DCR_ISRAM1_REVID, 72 DCR_ISRAM1_DPC, 73 DCR_ISRAM1_END = DCR_ISRAM1_DPC 74 }; 75 76 typedef struct ppc4xx_l2sram_t { 77 MemoryRegion bank[4]; 78 uint32_t l2cache[8]; 79 uint32_t isram0[11]; 80 } ppc4xx_l2sram_t; 81 82 #ifdef MAP_L2SRAM 83 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, 84 uint32_t isarc, uint32_t isacntl, 85 uint32_t dsarc, uint32_t dsacntl) 86 { 87 if (l2sram->isarc != isarc || 88 (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 89 if (l2sram->isacntl & 0x80000000) { 90 /* Unmap previously assigned memory region */ 91 memory_region_del_subregion(get_system_memory(), 92 &l2sram->isarc_ram); 93 } 94 if (isacntl & 0x80000000) { 95 /* Map new instruction memory region */ 96 memory_region_add_subregion(get_system_memory(), isarc, 97 &l2sram->isarc_ram); 98 } 99 } 100 if (l2sram->dsarc != dsarc || 101 (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 102 if (l2sram->dsacntl & 0x80000000) { 103 /* Beware not to unmap the region we just mapped */ 104 if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) { 105 /* Unmap previously assigned memory region */ 106 memory_region_del_subregion(get_system_memory(), 107 &l2sram->dsarc_ram); 108 } 109 } 110 if (dsacntl & 0x80000000) { 111 /* Beware not to remap the region we just mapped */ 112 if (!(isacntl & 0x80000000) || dsarc != isarc) { 113 /* Map new data memory region */ 114 memory_region_add_subregion(get_system_memory(), dsarc, 115 &l2sram->dsarc_ram); 116 } 117 } 118 } 119 } 120 #endif 121 122 static uint32_t dcr_read_l2sram(void *opaque, int dcrn) 123 { 124 ppc4xx_l2sram_t *l2sram = opaque; 125 uint32_t ret = 0; 126 127 switch (dcrn) { 128 case DCR_L2CACHE_CFG: 129 case DCR_L2CACHE_CMD: 130 case DCR_L2CACHE_ADDR: 131 case DCR_L2CACHE_DATA: 132 case DCR_L2CACHE_STAT: 133 case DCR_L2CACHE_CVER: 134 case DCR_L2CACHE_SNP0: 135 case DCR_L2CACHE_SNP1: 136 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; 137 break; 138 139 case DCR_ISRAM0_SB0CR: 140 case DCR_ISRAM0_SB1CR: 141 case DCR_ISRAM0_SB2CR: 142 case DCR_ISRAM0_SB3CR: 143 case DCR_ISRAM0_BEAR: 144 case DCR_ISRAM0_BESR0: 145 case DCR_ISRAM0_BESR1: 146 case DCR_ISRAM0_PMEG: 147 case DCR_ISRAM0_CID: 148 case DCR_ISRAM0_REVID: 149 case DCR_ISRAM0_DPC: 150 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; 151 break; 152 153 default: 154 break; 155 } 156 157 return ret; 158 } 159 160 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) 161 { 162 /*ppc4xx_l2sram_t *l2sram = opaque;*/ 163 /* FIXME: Actually handle L2 cache mapping */ 164 165 switch (dcrn) { 166 case DCR_L2CACHE_CFG: 167 case DCR_L2CACHE_CMD: 168 case DCR_L2CACHE_ADDR: 169 case DCR_L2CACHE_DATA: 170 case DCR_L2CACHE_STAT: 171 case DCR_L2CACHE_CVER: 172 case DCR_L2CACHE_SNP0: 173 case DCR_L2CACHE_SNP1: 174 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ 175 break; 176 177 case DCR_ISRAM0_SB0CR: 178 case DCR_ISRAM0_SB1CR: 179 case DCR_ISRAM0_SB2CR: 180 case DCR_ISRAM0_SB3CR: 181 case DCR_ISRAM0_BEAR: 182 case DCR_ISRAM0_BESR0: 183 case DCR_ISRAM0_BESR1: 184 case DCR_ISRAM0_PMEG: 185 case DCR_ISRAM0_CID: 186 case DCR_ISRAM0_REVID: 187 case DCR_ISRAM0_DPC: 188 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ 189 break; 190 191 case DCR_ISRAM1_SB0CR: 192 case DCR_ISRAM1_BEAR: 193 case DCR_ISRAM1_BESR0: 194 case DCR_ISRAM1_BESR1: 195 case DCR_ISRAM1_PMEG: 196 case DCR_ISRAM1_CID: 197 case DCR_ISRAM1_REVID: 198 case DCR_ISRAM1_DPC: 199 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ 200 break; 201 } 202 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 203 } 204 205 static void l2sram_reset(void *opaque) 206 { 207 ppc4xx_l2sram_t *l2sram = opaque; 208 209 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); 210 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; 211 memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); 212 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 213 } 214 215 void ppc4xx_l2sram_init(CPUPPCState *env) 216 { 217 ppc4xx_l2sram_t *l2sram; 218 219 l2sram = g_malloc0(sizeof(*l2sram)); 220 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ 221 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", 222 64 * KiB, &error_abort); 223 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", 224 64 * KiB, &error_abort); 225 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", 226 64 * KiB, &error_abort); 227 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", 228 64 * KiB, &error_abort); 229 qemu_register_reset(&l2sram_reset, l2sram); 230 ppc_dcr_register(env, DCR_L2CACHE_CFG, 231 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 232 ppc_dcr_register(env, DCR_L2CACHE_CMD, 233 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 234 ppc_dcr_register(env, DCR_L2CACHE_ADDR, 235 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 236 ppc_dcr_register(env, DCR_L2CACHE_DATA, 237 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 238 ppc_dcr_register(env, DCR_L2CACHE_STAT, 239 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 240 ppc_dcr_register(env, DCR_L2CACHE_CVER, 241 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 242 ppc_dcr_register(env, DCR_L2CACHE_SNP0, 243 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 244 ppc_dcr_register(env, DCR_L2CACHE_SNP1, 245 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 246 247 ppc_dcr_register(env, DCR_ISRAM0_SB0CR, 248 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 249 ppc_dcr_register(env, DCR_ISRAM0_SB1CR, 250 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 251 ppc_dcr_register(env, DCR_ISRAM0_SB2CR, 252 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 253 ppc_dcr_register(env, DCR_ISRAM0_SB3CR, 254 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 255 ppc_dcr_register(env, DCR_ISRAM0_PMEG, 256 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 257 ppc_dcr_register(env, DCR_ISRAM0_DPC, 258 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 259 260 ppc_dcr_register(env, DCR_ISRAM1_SB0CR, 261 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 262 ppc_dcr_register(env, DCR_ISRAM1_PMEG, 263 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 264 ppc_dcr_register(env, DCR_ISRAM1_DPC, 265 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 266 } 267 268 /*****************************************************************************/ 269 /* Clocking Power on Reset */ 270 enum { 271 CPR0_CFGADDR = 0xC, 272 CPR0_CFGDATA = 0xD, 273 274 CPR0_PLLD = 0x060, 275 CPR0_PLBED = 0x080, 276 CPR0_OPBD = 0x0C0, 277 CPR0_PERD = 0x0E0, 278 CPR0_AHBD = 0x100, 279 }; 280 281 typedef struct ppc4xx_cpr_t { 282 uint32_t addr; 283 } ppc4xx_cpr_t; 284 285 static uint32_t dcr_read_cpr(void *opaque, int dcrn) 286 { 287 ppc4xx_cpr_t *cpr = opaque; 288 uint32_t ret = 0; 289 290 switch (dcrn) { 291 case CPR0_CFGADDR: 292 ret = cpr->addr; 293 break; 294 case CPR0_CFGDATA: 295 switch (cpr->addr) { 296 case CPR0_PLLD: 297 ret = (0xb5 << 24) | (1 << 16) | (9 << 8); 298 break; 299 case CPR0_PLBED: 300 ret = (5 << 24); 301 break; 302 case CPR0_OPBD: 303 ret = (2 << 24); 304 break; 305 case CPR0_PERD: 306 case CPR0_AHBD: 307 ret = (1 << 24); 308 break; 309 default: 310 break; 311 } 312 break; 313 default: 314 break; 315 } 316 317 return ret; 318 } 319 320 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) 321 { 322 ppc4xx_cpr_t *cpr = opaque; 323 324 switch (dcrn) { 325 case CPR0_CFGADDR: 326 cpr->addr = val; 327 break; 328 case CPR0_CFGDATA: 329 break; 330 default: 331 break; 332 } 333 } 334 335 static void ppc4xx_cpr_reset(void *opaque) 336 { 337 ppc4xx_cpr_t *cpr = opaque; 338 339 cpr->addr = 0; 340 } 341 342 void ppc4xx_cpr_init(CPUPPCState *env) 343 { 344 ppc4xx_cpr_t *cpr; 345 346 cpr = g_malloc0(sizeof(*cpr)); 347 ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); 348 ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); 349 qemu_register_reset(ppc4xx_cpr_reset, cpr); 350 } 351 352 /*****************************************************************************/ 353 /* System DCRs */ 354 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; 355 struct ppc4xx_sdr_t { 356 uint32_t addr; 357 }; 358 359 enum { 360 SDR0_CFGADDR = 0x00e, 361 SDR0_CFGDATA, 362 SDR0_STRP0 = 0x020, 363 SDR0_STRP1, 364 SDR0_102 = 0x66, 365 SDR0_103, 366 SDR0_128 = 0x80, 367 SDR0_ECID3 = 0x083, 368 SDR0_DDR0 = 0x0e1, 369 SDR0_USB0 = 0x320, 370 }; 371 372 enum { 373 PESDR0_LOOP = 0x303, 374 PESDR0_RCSSET, 375 PESDR0_RCSSTS, 376 PESDR0_RSTSTA = 0x310, 377 PESDR1_LOOP = 0x343, 378 PESDR1_RCSSET, 379 PESDR1_RCSSTS, 380 PESDR1_RSTSTA = 0x365, 381 }; 382 383 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 384 #define SDR0_DDR0_DDRM_DDR1 0x20000000 385 #define SDR0_DDR0_DDRM_DDR2 0x40000000 386 387 static uint32_t dcr_read_sdr(void *opaque, int dcrn) 388 { 389 ppc4xx_sdr_t *sdr = opaque; 390 uint32_t ret = 0; 391 392 switch (dcrn) { 393 case SDR0_CFGADDR: 394 ret = sdr->addr; 395 break; 396 case SDR0_CFGDATA: 397 switch (sdr->addr) { 398 case SDR0_STRP0: 399 ret = (0xb5 << 8) | (1 << 4) | 9; 400 break; 401 case SDR0_STRP1: 402 ret = (5 << 29) | (2 << 26) | (1 << 24); 403 break; 404 case SDR0_ECID3: 405 ret = 1 << 20; /* No Security/Kasumi support */ 406 break; 407 case SDR0_DDR0: 408 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 409 break; 410 case PESDR0_RCSSET: 411 case PESDR1_RCSSET: 412 ret = (1 << 24) | (1 << 16); 413 break; 414 case PESDR0_RCSSTS: 415 case PESDR1_RCSSTS: 416 ret = (1 << 16) | (1 << 12); 417 break; 418 case PESDR0_RSTSTA: 419 case PESDR1_RSTSTA: 420 ret = 1; 421 break; 422 case PESDR0_LOOP: 423 case PESDR1_LOOP: 424 ret = 1 << 12; 425 break; 426 default: 427 break; 428 } 429 break; 430 default: 431 break; 432 } 433 434 return ret; 435 } 436 437 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) 438 { 439 ppc4xx_sdr_t *sdr = opaque; 440 441 switch (dcrn) { 442 case SDR0_CFGADDR: 443 sdr->addr = val; 444 break; 445 case SDR0_CFGDATA: 446 switch (sdr->addr) { 447 case 0x00: /* B0CR */ 448 break; 449 default: 450 break; 451 } 452 break; 453 default: 454 break; 455 } 456 } 457 458 static void sdr_reset(void *opaque) 459 { 460 ppc4xx_sdr_t *sdr = opaque; 461 462 sdr->addr = 0; 463 } 464 465 void ppc4xx_sdr_init(CPUPPCState *env) 466 { 467 ppc4xx_sdr_t *sdr; 468 469 sdr = g_malloc0(sizeof(*sdr)); 470 qemu_register_reset(&sdr_reset, sdr); 471 ppc_dcr_register(env, SDR0_CFGADDR, 472 sdr, &dcr_read_sdr, &dcr_write_sdr); 473 ppc_dcr_register(env, SDR0_CFGDATA, 474 sdr, &dcr_read_sdr, &dcr_write_sdr); 475 ppc_dcr_register(env, SDR0_102, 476 sdr, &dcr_read_sdr, &dcr_write_sdr); 477 ppc_dcr_register(env, SDR0_103, 478 sdr, &dcr_read_sdr, &dcr_write_sdr); 479 ppc_dcr_register(env, SDR0_128, 480 sdr, &dcr_read_sdr, &dcr_write_sdr); 481 ppc_dcr_register(env, SDR0_USB0, 482 sdr, &dcr_read_sdr, &dcr_write_sdr); 483 } 484 485 /*****************************************************************************/ 486 /* SDRAM controller */ 487 typedef struct ppc440_sdram_t { 488 uint32_t addr; 489 uint32_t mcopt2; 490 int nbanks; 491 Ppc4xxSdramBank bank[4]; 492 } ppc440_sdram_t; 493 494 enum { 495 SDRAM0_CFGADDR = 0x10, 496 SDRAM0_CFGDATA, 497 SDRAM_R0BAS = 0x40, 498 SDRAM_R1BAS, 499 SDRAM_R2BAS, 500 SDRAM_R3BAS, 501 SDRAM_CONF1HB = 0x45, 502 SDRAM_PLBADDULL = 0x4a, 503 SDRAM_CONF1LL = 0x4b, 504 SDRAM_CONFPATHB = 0x4f, 505 SDRAM_PLBADDUHB = 0x50, 506 }; 507 508 static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) 509 { 510 uint32_t bcr; 511 512 switch (ram_size) { 513 case (8 * MiB): 514 bcr = 0xffc0; 515 break; 516 case (16 * MiB): 517 bcr = 0xff80; 518 break; 519 case (32 * MiB): 520 bcr = 0xff00; 521 break; 522 case (64 * MiB): 523 bcr = 0xfe00; 524 break; 525 case (128 * MiB): 526 bcr = 0xfc00; 527 break; 528 case (256 * MiB): 529 bcr = 0xf800; 530 break; 531 case (512 * MiB): 532 bcr = 0xf000; 533 break; 534 case (1 * GiB): 535 bcr = 0xe000; 536 break; 537 case (2 * GiB): 538 bcr = 0xc000; 539 break; 540 case (4 * GiB): 541 bcr = 0x8000; 542 break; 543 default: 544 error_report("invalid RAM size " TARGET_FMT_plx, ram_size); 545 return 0; 546 } 547 bcr |= ram_base >> 2 & 0xffe00000; 548 bcr |= 1; 549 550 return bcr; 551 } 552 553 static inline hwaddr sdram_ddr2_base(uint32_t bcr) 554 { 555 return (bcr & 0xffe00000) << 2; 556 } 557 558 static uint64_t sdram_ddr2_size(uint32_t bcr) 559 { 560 uint64_t size; 561 int sh; 562 563 sh = 1024 - ((bcr >> 6) & 0x3ff); 564 size = 8 * MiB * sh; 565 566 return size; 567 } 568 569 static void sdram_bank_map(Ppc4xxSdramBank *bank) 570 { 571 memory_region_init(&bank->container, NULL, "sdram-container", bank->size); 572 memory_region_add_subregion(&bank->container, 0, &bank->ram); 573 memory_region_add_subregion(get_system_memory(), bank->base, 574 &bank->container); 575 } 576 577 static void sdram_bank_unmap(Ppc4xxSdramBank *bank) 578 { 579 memory_region_del_subregion(get_system_memory(), &bank->container); 580 memory_region_del_subregion(&bank->container, &bank->ram); 581 object_unparent(OBJECT(&bank->container)); 582 } 583 584 static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i, 585 uint32_t bcr, int enabled) 586 { 587 if (sdram->bank[i].bcr & 1) { 588 /* First unmap RAM if enabled */ 589 trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr), 590 sdram_ddr2_size(sdram->bank[i].bcr)); 591 sdram_bank_unmap(&sdram->bank[i]); 592 } 593 sdram->bank[i].bcr = bcr & 0xffe0ffc1; 594 if (enabled && (bcr & 1)) { 595 trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr)); 596 sdram_bank_map(&sdram->bank[i]); 597 } 598 } 599 600 static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram) 601 { 602 int i; 603 604 for (i = 0; i < sdram->nbanks; i++) { 605 if (sdram->bank[i].size) { 606 sdram_ddr2_set_bcr(sdram, i, 607 sdram_ddr2_bcr(sdram->bank[i].base, 608 sdram->bank[i].size), 1); 609 } else { 610 sdram_ddr2_set_bcr(sdram, i, 0, 0); 611 } 612 } 613 } 614 615 static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram) 616 { 617 int i; 618 619 for (i = 0; i < sdram->nbanks; i++) { 620 if (sdram->bank[i].size) { 621 sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); 622 } 623 } 624 } 625 626 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) 627 { 628 ppc440_sdram_t *sdram = opaque; 629 uint32_t ret = 0; 630 631 switch (dcrn) { 632 case SDRAM_R0BAS: 633 case SDRAM_R1BAS: 634 case SDRAM_R2BAS: 635 case SDRAM_R3BAS: 636 if (sdram->bank[dcrn - SDRAM_R0BAS].size) { 637 ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, 638 sdram->bank[dcrn - SDRAM_R0BAS].size); 639 } 640 break; 641 case SDRAM_CONF1HB: 642 case SDRAM_CONF1LL: 643 case SDRAM_CONFPATHB: 644 case SDRAM_PLBADDULL: 645 case SDRAM_PLBADDUHB: 646 break; 647 case SDRAM0_CFGADDR: 648 ret = sdram->addr; 649 break; 650 case SDRAM0_CFGDATA: 651 switch (sdram->addr) { 652 case 0x14: /* SDRAM_MCSTAT (405EX) */ 653 case 0x1F: 654 ret = 0x80000000; 655 break; 656 case 0x21: /* SDRAM_MCOPT2 */ 657 ret = sdram->mcopt2; 658 break; 659 case 0x40: /* SDRAM_MB0CF */ 660 ret = 0x00008001; 661 break; 662 case 0x7A: /* SDRAM_DLCR */ 663 ret = 0x02000000; 664 break; 665 case 0xE1: /* SDR0_DDR0 */ 666 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 667 break; 668 default: 669 break; 670 } 671 break; 672 default: 673 break; 674 } 675 676 return ret; 677 } 678 679 #define SDRAM_DDR2_MCOPT2_DCEN BIT(27) 680 681 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) 682 { 683 ppc440_sdram_t *sdram = opaque; 684 685 switch (dcrn) { 686 case SDRAM_R0BAS: 687 case SDRAM_R1BAS: 688 case SDRAM_R2BAS: 689 case SDRAM_R3BAS: 690 case SDRAM_CONF1HB: 691 case SDRAM_CONF1LL: 692 case SDRAM_CONFPATHB: 693 case SDRAM_PLBADDULL: 694 case SDRAM_PLBADDUHB: 695 break; 696 case SDRAM0_CFGADDR: 697 sdram->addr = val; 698 break; 699 case SDRAM0_CFGDATA: 700 switch (sdram->addr) { 701 case 0x00: /* B0CR */ 702 break; 703 case 0x21: /* SDRAM_MCOPT2 */ 704 if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && 705 (val & SDRAM_DDR2_MCOPT2_DCEN)) { 706 trace_ppc4xx_sdram_enable("enable"); 707 /* validate all RAM mappings */ 708 sdram_ddr2_map_bcr(sdram); 709 sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN; 710 } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && 711 !(val & SDRAM_DDR2_MCOPT2_DCEN)) { 712 trace_ppc4xx_sdram_enable("disable"); 713 /* invalidate all RAM mappings */ 714 sdram_ddr2_unmap_bcr(sdram); 715 sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN; 716 } 717 break; 718 default: 719 break; 720 } 721 break; 722 default: 723 break; 724 } 725 } 726 727 static void sdram_ddr2_reset(void *opaque) 728 { 729 ppc440_sdram_t *sdram = opaque; 730 731 sdram->addr = 0; 732 sdram->mcopt2 = 0; 733 } 734 735 void ppc440_sdram_init(CPUPPCState *env, int nbanks, 736 Ppc4xxSdramBank *ram_banks) 737 { 738 ppc440_sdram_t *s; 739 int i; 740 741 s = g_malloc0(sizeof(*s)); 742 s->nbanks = nbanks; 743 for (i = 0; i < nbanks; i++) { 744 s->bank[i].ram = ram_banks[i].ram; 745 s->bank[i].base = ram_banks[i].base; 746 s->bank[i].size = ram_banks[i].size; 747 } 748 qemu_register_reset(&sdram_ddr2_reset, s); 749 ppc_dcr_register(env, SDRAM0_CFGADDR, 750 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 751 ppc_dcr_register(env, SDRAM0_CFGDATA, 752 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 753 754 ppc_dcr_register(env, SDRAM_R0BAS, 755 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 756 ppc_dcr_register(env, SDRAM_R1BAS, 757 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 758 ppc_dcr_register(env, SDRAM_R2BAS, 759 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 760 ppc_dcr_register(env, SDRAM_R3BAS, 761 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 762 ppc_dcr_register(env, SDRAM_CONF1HB, 763 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 764 ppc_dcr_register(env, SDRAM_PLBADDULL, 765 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 766 ppc_dcr_register(env, SDRAM_CONF1LL, 767 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 768 ppc_dcr_register(env, SDRAM_CONFPATHB, 769 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 770 ppc_dcr_register(env, SDRAM_PLBADDUHB, 771 s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); 772 } 773 774 void ppc4xx_sdram_ddr2_enable(CPUPPCState *env) 775 { 776 ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21); 777 ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000); 778 } 779 780 /*****************************************************************************/ 781 /* PLB to AHB bridge */ 782 enum { 783 AHB_TOP = 0xA4, 784 AHB_BOT = 0xA5, 785 }; 786 787 typedef struct ppc4xx_ahb_t { 788 uint32_t top; 789 uint32_t bot; 790 } ppc4xx_ahb_t; 791 792 static uint32_t dcr_read_ahb(void *opaque, int dcrn) 793 { 794 ppc4xx_ahb_t *ahb = opaque; 795 uint32_t ret = 0; 796 797 switch (dcrn) { 798 case AHB_TOP: 799 ret = ahb->top; 800 break; 801 case AHB_BOT: 802 ret = ahb->bot; 803 break; 804 default: 805 break; 806 } 807 808 return ret; 809 } 810 811 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) 812 { 813 ppc4xx_ahb_t *ahb = opaque; 814 815 switch (dcrn) { 816 case AHB_TOP: 817 ahb->top = val; 818 break; 819 case AHB_BOT: 820 ahb->bot = val; 821 break; 822 } 823 } 824 825 static void ppc4xx_ahb_reset(void *opaque) 826 { 827 ppc4xx_ahb_t *ahb = opaque; 828 829 /* No error */ 830 ahb->top = 0; 831 ahb->bot = 0; 832 } 833 834 void ppc4xx_ahb_init(CPUPPCState *env) 835 { 836 ppc4xx_ahb_t *ahb; 837 838 ahb = g_malloc0(sizeof(*ahb)); 839 ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); 840 ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); 841 qemu_register_reset(ppc4xx_ahb_reset, ahb); 842 } 843 844 /*****************************************************************************/ 845 /* DMA controller */ 846 847 #define DMA0_CR_CE (1 << 31) 848 #define DMA0_CR_PW (1 << 26 | 1 << 25) 849 #define DMA0_CR_DAI (1 << 24) 850 #define DMA0_CR_SAI (1 << 23) 851 #define DMA0_CR_DEC (1 << 2) 852 853 enum { 854 DMA0_CR = 0x00, 855 DMA0_CT, 856 DMA0_SAH, 857 DMA0_SAL, 858 DMA0_DAH, 859 DMA0_DAL, 860 DMA0_SGH, 861 DMA0_SGL, 862 863 DMA0_SR = 0x20, 864 DMA0_SGC = 0x23, 865 DMA0_SLP = 0x25, 866 DMA0_POL = 0x26, 867 }; 868 869 typedef struct { 870 uint32_t cr; 871 uint32_t ct; 872 uint64_t sa; 873 uint64_t da; 874 uint64_t sg; 875 } PPC4xxDmaChnl; 876 877 typedef struct { 878 int base; 879 PPC4xxDmaChnl ch[4]; 880 uint32_t sr; 881 } PPC4xxDmaState; 882 883 static uint32_t dcr_read_dma(void *opaque, int dcrn) 884 { 885 PPC4xxDmaState *dma = opaque; 886 uint32_t val = 0; 887 int addr = dcrn - dma->base; 888 int chnl = addr / 8; 889 890 switch (addr) { 891 case 0x00 ... 0x1f: 892 switch (addr % 8) { 893 case DMA0_CR: 894 val = dma->ch[chnl].cr; 895 break; 896 case DMA0_CT: 897 val = dma->ch[chnl].ct; 898 break; 899 case DMA0_SAH: 900 val = dma->ch[chnl].sa >> 32; 901 break; 902 case DMA0_SAL: 903 val = dma->ch[chnl].sa; 904 break; 905 case DMA0_DAH: 906 val = dma->ch[chnl].da >> 32; 907 break; 908 case DMA0_DAL: 909 val = dma->ch[chnl].da; 910 break; 911 case DMA0_SGH: 912 val = dma->ch[chnl].sg >> 32; 913 break; 914 case DMA0_SGL: 915 val = dma->ch[chnl].sg; 916 break; 917 } 918 break; 919 case DMA0_SR: 920 val = dma->sr; 921 break; 922 default: 923 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 924 __func__, dcrn, chnl, addr); 925 } 926 927 return val; 928 } 929 930 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) 931 { 932 PPC4xxDmaState *dma = opaque; 933 int addr = dcrn - dma->base; 934 int chnl = addr / 8; 935 936 switch (addr) { 937 case 0x00 ... 0x1f: 938 switch (addr % 8) { 939 case DMA0_CR: 940 dma->ch[chnl].cr = val; 941 if (val & DMA0_CR_CE) { 942 int count = dma->ch[chnl].ct & 0xffff; 943 944 if (count) { 945 int width, i, sidx, didx; 946 uint8_t *rptr, *wptr; 947 hwaddr rlen, wlen; 948 hwaddr xferlen; 949 950 sidx = didx = 0; 951 width = 1 << ((val & DMA0_CR_PW) >> 25); 952 xferlen = count * width; 953 wlen = rlen = xferlen; 954 rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 955 false); 956 wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 957 true); 958 if (rptr && rlen == xferlen && wptr && wlen == xferlen) { 959 if (!(val & DMA0_CR_DEC) && 960 val & DMA0_CR_SAI && val & DMA0_CR_DAI) { 961 /* optimise common case */ 962 memmove(wptr, rptr, count * width); 963 sidx = didx = count * width; 964 } else { 965 /* do it the slow way */ 966 for (sidx = didx = i = 0; i < count; i++) { 967 uint64_t v = ldn_le_p(rptr + sidx, width); 968 stn_le_p(wptr + didx, width, v); 969 if (val & DMA0_CR_SAI) { 970 sidx += width; 971 } 972 if (val & DMA0_CR_DAI) { 973 didx += width; 974 } 975 } 976 } 977 } 978 if (wptr) { 979 cpu_physical_memory_unmap(wptr, wlen, 1, didx); 980 } 981 if (rptr) { 982 cpu_physical_memory_unmap(rptr, rlen, 0, sidx); 983 } 984 } 985 } 986 break; 987 case DMA0_CT: 988 dma->ch[chnl].ct = val; 989 break; 990 case DMA0_SAH: 991 dma->ch[chnl].sa &= 0xffffffffULL; 992 dma->ch[chnl].sa |= (uint64_t)val << 32; 993 break; 994 case DMA0_SAL: 995 dma->ch[chnl].sa &= 0xffffffff00000000ULL; 996 dma->ch[chnl].sa |= val; 997 break; 998 case DMA0_DAH: 999 dma->ch[chnl].da &= 0xffffffffULL; 1000 dma->ch[chnl].da |= (uint64_t)val << 32; 1001 break; 1002 case DMA0_DAL: 1003 dma->ch[chnl].da &= 0xffffffff00000000ULL; 1004 dma->ch[chnl].da |= val; 1005 break; 1006 case DMA0_SGH: 1007 dma->ch[chnl].sg &= 0xffffffffULL; 1008 dma->ch[chnl].sg |= (uint64_t)val << 32; 1009 break; 1010 case DMA0_SGL: 1011 dma->ch[chnl].sg &= 0xffffffff00000000ULL; 1012 dma->ch[chnl].sg |= val; 1013 break; 1014 } 1015 break; 1016 case DMA0_SR: 1017 dma->sr &= ~val; 1018 break; 1019 default: 1020 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 1021 __func__, dcrn, chnl, addr); 1022 } 1023 } 1024 1025 static void ppc4xx_dma_reset(void *opaque) 1026 { 1027 PPC4xxDmaState *dma = opaque; 1028 int dma_base = dma->base; 1029 1030 memset(dma, 0, sizeof(*dma)); 1031 dma->base = dma_base; 1032 } 1033 1034 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) 1035 { 1036 PPC4xxDmaState *dma; 1037 int i; 1038 1039 dma = g_malloc0(sizeof(*dma)); 1040 dma->base = dcr_base; 1041 qemu_register_reset(&ppc4xx_dma_reset, dma); 1042 for (i = 0; i < 4; i++) { 1043 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR, 1044 dma, &dcr_read_dma, &dcr_write_dma); 1045 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT, 1046 dma, &dcr_read_dma, &dcr_write_dma); 1047 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH, 1048 dma, &dcr_read_dma, &dcr_write_dma); 1049 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL, 1050 dma, &dcr_read_dma, &dcr_write_dma); 1051 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH, 1052 dma, &dcr_read_dma, &dcr_write_dma); 1053 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL, 1054 dma, &dcr_read_dma, &dcr_write_dma); 1055 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH, 1056 dma, &dcr_read_dma, &dcr_write_dma); 1057 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL, 1058 dma, &dcr_read_dma, &dcr_write_dma); 1059 } 1060 ppc_dcr_register(env, dcr_base + DMA0_SR, 1061 dma, &dcr_read_dma, &dcr_write_dma); 1062 ppc_dcr_register(env, dcr_base + DMA0_SGC, 1063 dma, &dcr_read_dma, &dcr_write_dma); 1064 ppc_dcr_register(env, dcr_base + DMA0_SLP, 1065 dma, &dcr_read_dma, &dcr_write_dma); 1066 ppc_dcr_register(env, dcr_base + DMA0_POL, 1067 dma, &dcr_read_dma, &dcr_write_dma); 1068 } 1069 1070 /*****************************************************************************/ 1071 /* PCI Express controller */ 1072 /* 1073 * FIXME: This is not complete and does not work, only implemented partially 1074 * to allow firmware and guests to find an empty bus. Cards should use PCI. 1075 */ 1076 #include "hw/pci/pcie_host.h" 1077 1078 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 1079 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST) 1080 1081 struct PPC460EXPCIEState { 1082 PCIExpressHost host; 1083 1084 MemoryRegion iomem; 1085 qemu_irq irq[4]; 1086 int32_t dcrn_base; 1087 1088 uint64_t cfg_base; 1089 uint32_t cfg_mask; 1090 uint64_t msg_base; 1091 uint32_t msg_mask; 1092 uint64_t omr1_base; 1093 uint64_t omr1_mask; 1094 uint64_t omr2_base; 1095 uint64_t omr2_mask; 1096 uint64_t omr3_base; 1097 uint64_t omr3_mask; 1098 uint64_t reg_base; 1099 uint32_t reg_mask; 1100 uint32_t special; 1101 uint32_t cfg; 1102 }; 1103 1104 #define DCRN_PCIE0_BASE 0x100 1105 #define DCRN_PCIE1_BASE 0x120 1106 1107 enum { 1108 PEGPL_CFGBAH = 0x0, 1109 PEGPL_CFGBAL, 1110 PEGPL_CFGMSK, 1111 PEGPL_MSGBAH, 1112 PEGPL_MSGBAL, 1113 PEGPL_MSGMSK, 1114 PEGPL_OMR1BAH, 1115 PEGPL_OMR1BAL, 1116 PEGPL_OMR1MSKH, 1117 PEGPL_OMR1MSKL, 1118 PEGPL_OMR2BAH, 1119 PEGPL_OMR2BAL, 1120 PEGPL_OMR2MSKH, 1121 PEGPL_OMR2MSKL, 1122 PEGPL_OMR3BAH, 1123 PEGPL_OMR3BAL, 1124 PEGPL_OMR3MSKH, 1125 PEGPL_OMR3MSKL, 1126 PEGPL_REGBAH, 1127 PEGPL_REGBAL, 1128 PEGPL_REGMSK, 1129 PEGPL_SPECIAL, 1130 PEGPL_CFG, 1131 }; 1132 1133 static uint32_t dcr_read_pcie(void *opaque, int dcrn) 1134 { 1135 PPC460EXPCIEState *state = opaque; 1136 uint32_t ret = 0; 1137 1138 switch (dcrn - state->dcrn_base) { 1139 case PEGPL_CFGBAH: 1140 ret = state->cfg_base >> 32; 1141 break; 1142 case PEGPL_CFGBAL: 1143 ret = state->cfg_base; 1144 break; 1145 case PEGPL_CFGMSK: 1146 ret = state->cfg_mask; 1147 break; 1148 case PEGPL_MSGBAH: 1149 ret = state->msg_base >> 32; 1150 break; 1151 case PEGPL_MSGBAL: 1152 ret = state->msg_base; 1153 break; 1154 case PEGPL_MSGMSK: 1155 ret = state->msg_mask; 1156 break; 1157 case PEGPL_OMR1BAH: 1158 ret = state->omr1_base >> 32; 1159 break; 1160 case PEGPL_OMR1BAL: 1161 ret = state->omr1_base; 1162 break; 1163 case PEGPL_OMR1MSKH: 1164 ret = state->omr1_mask >> 32; 1165 break; 1166 case PEGPL_OMR1MSKL: 1167 ret = state->omr1_mask; 1168 break; 1169 case PEGPL_OMR2BAH: 1170 ret = state->omr2_base >> 32; 1171 break; 1172 case PEGPL_OMR2BAL: 1173 ret = state->omr2_base; 1174 break; 1175 case PEGPL_OMR2MSKH: 1176 ret = state->omr2_mask >> 32; 1177 break; 1178 case PEGPL_OMR2MSKL: 1179 ret = state->omr3_mask; 1180 break; 1181 case PEGPL_OMR3BAH: 1182 ret = state->omr3_base >> 32; 1183 break; 1184 case PEGPL_OMR3BAL: 1185 ret = state->omr3_base; 1186 break; 1187 case PEGPL_OMR3MSKH: 1188 ret = state->omr3_mask >> 32; 1189 break; 1190 case PEGPL_OMR3MSKL: 1191 ret = state->omr3_mask; 1192 break; 1193 case PEGPL_REGBAH: 1194 ret = state->reg_base >> 32; 1195 break; 1196 case PEGPL_REGBAL: 1197 ret = state->reg_base; 1198 break; 1199 case PEGPL_REGMSK: 1200 ret = state->reg_mask; 1201 break; 1202 case PEGPL_SPECIAL: 1203 ret = state->special; 1204 break; 1205 case PEGPL_CFG: 1206 ret = state->cfg; 1207 break; 1208 } 1209 1210 return ret; 1211 } 1212 1213 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) 1214 { 1215 PPC460EXPCIEState *s = opaque; 1216 uint64_t size; 1217 1218 switch (dcrn - s->dcrn_base) { 1219 case PEGPL_CFGBAH: 1220 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); 1221 break; 1222 case PEGPL_CFGBAL: 1223 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; 1224 break; 1225 case PEGPL_CFGMSK: 1226 s->cfg_mask = val; 1227 size = ~(val & 0xfffffffe) + 1; 1228 /* 1229 * Firmware sets this register to E0000001. Why we are not sure, 1230 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is 1231 * ignored. 1232 */ 1233 if (size > PCIE_MMCFG_SIZE_MAX) { 1234 size = PCIE_MMCFG_SIZE_MAX; 1235 } 1236 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); 1237 break; 1238 case PEGPL_MSGBAH: 1239 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); 1240 break; 1241 case PEGPL_MSGBAL: 1242 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; 1243 break; 1244 case PEGPL_MSGMSK: 1245 s->msg_mask = val; 1246 break; 1247 case PEGPL_OMR1BAH: 1248 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); 1249 break; 1250 case PEGPL_OMR1BAL: 1251 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; 1252 break; 1253 case PEGPL_OMR1MSKH: 1254 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); 1255 break; 1256 case PEGPL_OMR1MSKL: 1257 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; 1258 break; 1259 case PEGPL_OMR2BAH: 1260 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); 1261 break; 1262 case PEGPL_OMR2BAL: 1263 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; 1264 break; 1265 case PEGPL_OMR2MSKH: 1266 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); 1267 break; 1268 case PEGPL_OMR2MSKL: 1269 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; 1270 break; 1271 case PEGPL_OMR3BAH: 1272 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); 1273 break; 1274 case PEGPL_OMR3BAL: 1275 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; 1276 break; 1277 case PEGPL_OMR3MSKH: 1278 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); 1279 break; 1280 case PEGPL_OMR3MSKL: 1281 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; 1282 break; 1283 case PEGPL_REGBAH: 1284 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); 1285 break; 1286 case PEGPL_REGBAL: 1287 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; 1288 break; 1289 case PEGPL_REGMSK: 1290 s->reg_mask = val; 1291 /* FIXME: how is size encoded? */ 1292 size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); 1293 break; 1294 case PEGPL_SPECIAL: 1295 s->special = val; 1296 break; 1297 case PEGPL_CFG: 1298 s->cfg = val; 1299 break; 1300 } 1301 } 1302 1303 static void ppc460ex_set_irq(void *opaque, int irq_num, int level) 1304 { 1305 PPC460EXPCIEState *s = opaque; 1306 qemu_set_irq(s->irq[irq_num], level); 1307 } 1308 1309 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) 1310 { 1311 PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); 1312 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 1313 int i, id; 1314 char buf[16]; 1315 1316 switch (s->dcrn_base) { 1317 case DCRN_PCIE0_BASE: 1318 id = 0; 1319 break; 1320 case DCRN_PCIE1_BASE: 1321 id = 1; 1322 break; 1323 default: 1324 error_setg(errp, "invalid PCIe DCRN base"); 1325 return; 1326 } 1327 snprintf(buf, sizeof(buf), "pcie%d-io", id); 1328 memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); 1329 for (i = 0; i < 4; i++) { 1330 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1331 } 1332 snprintf(buf, sizeof(buf), "pcie.%d", id); 1333 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, 1334 pci_swizzle_map_irq_fn, s, &s->iomem, 1335 get_system_io(), 0, 4, TYPE_PCIE_BUS); 1336 } 1337 1338 static Property ppc460ex_pcie_props[] = { 1339 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), 1340 DEFINE_PROP_END_OF_LIST(), 1341 }; 1342 1343 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) 1344 { 1345 DeviceClass *dc = DEVICE_CLASS(klass); 1346 1347 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1348 dc->realize = ppc460ex_pcie_realize; 1349 device_class_set_props(dc, ppc460ex_pcie_props); 1350 dc->hotpluggable = false; 1351 } 1352 1353 static const TypeInfo ppc460ex_pcie_host_info = { 1354 .name = TYPE_PPC460EX_PCIE_HOST, 1355 .parent = TYPE_PCIE_HOST_BRIDGE, 1356 .instance_size = sizeof(PPC460EXPCIEState), 1357 .class_init = ppc460ex_pcie_class_init, 1358 }; 1359 1360 static void ppc460ex_pcie_register(void) 1361 { 1362 type_register_static(&ppc460ex_pcie_host_info); 1363 } 1364 1365 type_init(ppc460ex_pcie_register) 1366 1367 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env) 1368 { 1369 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, 1370 &dcr_read_pcie, &dcr_write_pcie); 1371 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, 1372 &dcr_read_pcie, &dcr_write_pcie); 1373 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, 1374 &dcr_read_pcie, &dcr_write_pcie); 1375 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, 1376 &dcr_read_pcie, &dcr_write_pcie); 1377 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, 1378 &dcr_read_pcie, &dcr_write_pcie); 1379 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, 1380 &dcr_read_pcie, &dcr_write_pcie); 1381 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, 1382 &dcr_read_pcie, &dcr_write_pcie); 1383 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, 1384 &dcr_read_pcie, &dcr_write_pcie); 1385 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, 1386 &dcr_read_pcie, &dcr_write_pcie); 1387 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, 1388 &dcr_read_pcie, &dcr_write_pcie); 1389 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, 1390 &dcr_read_pcie, &dcr_write_pcie); 1391 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, 1392 &dcr_read_pcie, &dcr_write_pcie); 1393 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, 1394 &dcr_read_pcie, &dcr_write_pcie); 1395 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, 1396 &dcr_read_pcie, &dcr_write_pcie); 1397 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, 1398 &dcr_read_pcie, &dcr_write_pcie); 1399 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, 1400 &dcr_read_pcie, &dcr_write_pcie); 1401 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, 1402 &dcr_read_pcie, &dcr_write_pcie); 1403 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, 1404 &dcr_read_pcie, &dcr_write_pcie); 1405 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, 1406 &dcr_read_pcie, &dcr_write_pcie); 1407 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, 1408 &dcr_read_pcie, &dcr_write_pcie); 1409 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, 1410 &dcr_read_pcie, &dcr_write_pcie); 1411 ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, 1412 &dcr_read_pcie, &dcr_write_pcie); 1413 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, 1414 &dcr_read_pcie, &dcr_write_pcie); 1415 } 1416 1417 void ppc460ex_pcie_init(CPUPPCState *env) 1418 { 1419 DeviceState *dev; 1420 1421 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1422 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1423 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1424 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1425 1426 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1427 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1428 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1429 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1430 } 1431