1 /* 2 * QEMU PowerPC 440 Bamboo board emulation 3 * 4 * Copyright 2007 IBM Corporation. 5 * Authors: 6 * Jerone Young <jyoung5@us.ibm.com> 7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 8 * Hollis Blanchard <hollisb@us.ibm.com> 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/error-report.h" 17 #include "qemu-common.h" 18 #include "qemu/error-report.h" 19 #include "net/net.h" 20 #include "hw/pci/pci.h" 21 #include "hw/boards.h" 22 #include "sysemu/kvm.h" 23 #include "kvm_ppc.h" 24 #include "sysemu/device_tree.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "exec/address-spaces.h" 28 #include "hw/char/serial.h" 29 #include "hw/ppc/ppc.h" 30 #include "ppc405.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/qtest.h" 33 #include "sysemu/reset.h" 34 #include "hw/sysbus.h" 35 36 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" 37 38 /* from u-boot */ 39 #define KERNEL_ADDR 0x1000000 40 #define FDT_ADDR 0x1800000 41 #define RAMDISK_ADDR 0x1900000 42 43 #define PPC440EP_PCI_CONFIG 0xeec00000 44 #define PPC440EP_PCI_INTACK 0xeed00000 45 #define PPC440EP_PCI_SPECIAL 0xeed00000 46 #define PPC440EP_PCI_REGS 0xef400000 47 #define PPC440EP_PCI_IO 0xe8000000 48 #define PPC440EP_PCI_IOLEN 0x00010000 49 50 #define PPC440EP_SDRAM_NR_BANKS 4 51 52 static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { 53 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 54 }; 55 56 static hwaddr entry; 57 58 static int bamboo_load_device_tree(hwaddr addr, 59 uint32_t ramsize, 60 hwaddr initrd_base, 61 hwaddr initrd_size, 62 const char *kernel_cmdline) 63 { 64 int ret = -1; 65 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 66 char *filename; 67 int fdt_size; 68 void *fdt; 69 uint32_t tb_freq = 400000000; 70 uint32_t clock_freq = 400000000; 71 72 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 73 if (!filename) { 74 return -1; 75 } 76 fdt = load_device_tree(filename, &fdt_size); 77 g_free(filename); 78 if (fdt == NULL) { 79 return -1; 80 } 81 82 /* Manipulate device tree in memory. */ 83 84 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 85 sizeof(mem_reg_property)); 86 if (ret < 0) 87 fprintf(stderr, "couldn't set /memory/reg\n"); 88 89 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 90 initrd_base); 91 if (ret < 0) 92 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 93 94 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 95 (initrd_base + initrd_size)); 96 if (ret < 0) 97 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 98 99 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 100 kernel_cmdline); 101 if (ret < 0) 102 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 103 104 /* Copy data from the host device tree into the guest. Since the guest can 105 * directly access the timebase without host involvement, we must expose 106 * the correct frequencies. */ 107 if (kvm_enabled()) { 108 tb_freq = kvmppc_get_tbfreq(); 109 clock_freq = kvmppc_get_clockfreq(); 110 } 111 112 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 113 clock_freq); 114 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 115 tb_freq); 116 117 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 118 g_free(fdt); 119 return 0; 120 } 121 122 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 123 static void mmubooke_create_initial_mapping(CPUPPCState *env, 124 target_ulong va, 125 hwaddr pa) 126 { 127 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 128 129 tlb->attr = 0; 130 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 131 tlb->size = 1U << 31; /* up to 0x80000000 */ 132 tlb->EPN = va & TARGET_PAGE_MASK; 133 tlb->RPN = pa & TARGET_PAGE_MASK; 134 tlb->PID = 0; 135 136 tlb = &env->tlb.tlbe[1]; 137 tlb->attr = 0; 138 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 139 tlb->size = 1U << 31; /* up to 0xffffffff */ 140 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 141 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 142 tlb->PID = 0; 143 } 144 145 static void main_cpu_reset(void *opaque) 146 { 147 PowerPCCPU *cpu = opaque; 148 CPUPPCState *env = &cpu->env; 149 150 cpu_reset(CPU(cpu)); 151 env->gpr[1] = (16 * MiB) - 8; 152 env->gpr[3] = FDT_ADDR; 153 env->nip = entry; 154 155 /* Create a mapping for the kernel. */ 156 mmubooke_create_initial_mapping(env, 0, 0); 157 } 158 159 static void bamboo_init(MachineState *machine) 160 { 161 const char *kernel_filename = machine->kernel_filename; 162 const char *kernel_cmdline = machine->kernel_cmdline; 163 const char *initrd_filename = machine->initrd_filename; 164 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; 165 MemoryRegion *address_space_mem = get_system_memory(); 166 MemoryRegion *isa = g_new(MemoryRegion, 1); 167 MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); 168 hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; 169 hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; 170 qemu_irq *pic; 171 qemu_irq *irqs; 172 PCIBus *pcibus; 173 PowerPCCPU *cpu; 174 CPUPPCState *env; 175 uint64_t elf_entry; 176 uint64_t elf_lowaddr; 177 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 178 target_long initrd_size = 0; 179 DeviceState *dev; 180 int success; 181 int i; 182 183 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 184 env = &cpu->env; 185 186 if (env->mmu_model != POWERPC_MMU_BOOKE) { 187 error_report("MMU model %i not supported by this machine", 188 env->mmu_model); 189 exit(1); 190 } 191 192 qemu_register_reset(main_cpu_reset, cpu); 193 ppc_booke_timers_init(cpu, 400000000, 0); 194 ppc_dcr_init(env, NULL, NULL); 195 196 /* interrupt controller */ 197 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 198 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 199 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 200 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 201 202 /* SDRAM controller */ 203 memset(ram_bases, 0, sizeof(ram_bases)); 204 memset(ram_sizes, 0, sizeof(ram_sizes)); 205 ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, 206 ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); 207 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 208 ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, 209 ram_bases, ram_sizes, 1); 210 211 /* PCI */ 212 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, 213 PPC440EP_PCI_CONFIG, 214 pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]], 215 pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]], 216 NULL); 217 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 218 if (!pcibus) { 219 error_report("couldn't create PCI controller"); 220 exit(1); 221 } 222 223 memory_region_init_alias(isa, NULL, "isa_mmio", 224 get_system_io(), 0, PPC440EP_PCI_IOLEN); 225 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); 226 227 if (serial_hd(0) != NULL) { 228 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 229 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 230 DEVICE_BIG_ENDIAN); 231 } 232 if (serial_hd(1) != NULL) { 233 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 234 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 235 DEVICE_BIG_ENDIAN); 236 } 237 238 if (pcibus) { 239 /* Register network interfaces. */ 240 for (i = 0; i < nb_nics; i++) { 241 /* There are no PCI NICs on the Bamboo board, but there are 242 * PCI slots, so we can pick whatever default model we want. */ 243 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); 244 } 245 } 246 247 /* Load kernel. */ 248 if (kernel_filename) { 249 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, 250 NULL, NULL); 251 if (success < 0) { 252 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 253 &elf_lowaddr, NULL, NULL, 1, PPC_ELF_MACHINE, 254 0, 0); 255 entry = elf_entry; 256 loadaddr = elf_lowaddr; 257 } 258 /* XXX try again as binary */ 259 if (success < 0) { 260 error_report("could not load kernel '%s'", kernel_filename); 261 exit(1); 262 } 263 } 264 265 /* Load initrd. */ 266 if (initrd_filename) { 267 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 268 machine->ram_size - RAMDISK_ADDR); 269 270 if (initrd_size < 0) { 271 error_report("could not load ram disk '%s' at %x", 272 initrd_filename, RAMDISK_ADDR); 273 exit(1); 274 } 275 } 276 277 /* If we're loading a kernel directly, we must load the device tree too. */ 278 if (kernel_filename) { 279 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, 280 initrd_size, kernel_cmdline) < 0) { 281 error_report("couldn't load device tree"); 282 exit(1); 283 } 284 } 285 } 286 287 static void bamboo_machine_init(MachineClass *mc) 288 { 289 mc->desc = "bamboo"; 290 mc->init = bamboo_init; 291 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 292 mc->default_ram_id = "ppc4xx.sdram"; 293 } 294 295 DEFINE_MACHINE("bamboo", bamboo_machine_init) 296