1 /* 2 * QEMU PowerPC 440 Bamboo board emulation 3 * 4 * Copyright 2007 IBM Corporation. 5 * Authors: 6 * Jerone Young <jyoung5@us.ibm.com> 7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 8 * Hollis Blanchard <hollisb@us.ibm.com> 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/error-report.h" 17 #include "qemu/datadir.h" 18 #include "qemu/error-report.h" 19 #include "net/net.h" 20 #include "hw/pci/pci.h" 21 #include "hw/boards.h" 22 #include "sysemu/kvm.h" 23 #include "kvm_ppc.h" 24 #include "sysemu/device_tree.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "hw/char/serial.h" 28 #include "hw/ppc/ppc.h" 29 #include "ppc405.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/reset.h" 32 #include "hw/sysbus.h" 33 #include "hw/intc/ppc-uic.h" 34 #include "hw/qdev-properties.h" 35 #include "qapi/error.h" 36 37 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" 38 39 /* from u-boot */ 40 #define KERNEL_ADDR 0x1000000 41 #define FDT_ADDR 0x1800000 42 #define RAMDISK_ADDR 0x1900000 43 44 #define PPC440EP_PCI_CONFIG 0xeec00000 45 #define PPC440EP_PCI_INTACK 0xeed00000 46 #define PPC440EP_PCI_SPECIAL 0xeed00000 47 #define PPC440EP_PCI_REGS 0xef400000 48 #define PPC440EP_PCI_IO 0xe8000000 49 #define PPC440EP_PCI_IOLEN 0x00010000 50 51 static hwaddr entry; 52 53 static int bamboo_load_device_tree(hwaddr addr, 54 uint32_t ramsize, 55 hwaddr initrd_base, 56 hwaddr initrd_size, 57 const char *kernel_cmdline) 58 { 59 int ret = -1; 60 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 61 char *filename; 62 int fdt_size; 63 void *fdt; 64 uint32_t tb_freq = 400000000; 65 uint32_t clock_freq = 400000000; 66 67 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 68 if (!filename) { 69 return -1; 70 } 71 fdt = load_device_tree(filename, &fdt_size); 72 g_free(filename); 73 if (fdt == NULL) { 74 return -1; 75 } 76 77 /* Manipulate device tree in memory. */ 78 79 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 80 sizeof(mem_reg_property)); 81 if (ret < 0) { 82 fprintf(stderr, "couldn't set /memory/reg\n"); 83 } 84 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 85 initrd_base); 86 if (ret < 0) { 87 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 88 } 89 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 90 (initrd_base + initrd_size)); 91 if (ret < 0) { 92 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 93 } 94 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 95 kernel_cmdline); 96 if (ret < 0) { 97 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 98 } 99 100 /* 101 * Copy data from the host device tree into the guest. Since the guest can 102 * directly access the timebase without host involvement, we must expose 103 * the correct frequencies. 104 */ 105 if (kvm_enabled()) { 106 tb_freq = kvmppc_get_tbfreq(); 107 clock_freq = kvmppc_get_clockfreq(); 108 } 109 110 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 111 clock_freq); 112 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 113 tb_freq); 114 115 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 116 g_free(fdt); 117 return 0; 118 } 119 120 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 121 static void mmubooke_create_initial_mapping(CPUPPCState *env, 122 target_ulong va, 123 hwaddr pa) 124 { 125 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 126 127 tlb->attr = 0; 128 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 129 tlb->size = 1U << 31; /* up to 0x80000000 */ 130 tlb->EPN = va & TARGET_PAGE_MASK; 131 tlb->RPN = pa & TARGET_PAGE_MASK; 132 tlb->PID = 0; 133 134 tlb = &env->tlb.tlbe[1]; 135 tlb->attr = 0; 136 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 137 tlb->size = 1U << 31; /* up to 0xffffffff */ 138 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 139 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 140 tlb->PID = 0; 141 } 142 143 static void main_cpu_reset(void *opaque) 144 { 145 PowerPCCPU *cpu = opaque; 146 CPUPPCState *env = &cpu->env; 147 148 cpu_reset(CPU(cpu)); 149 env->gpr[1] = (16 * MiB) - 8; 150 env->gpr[3] = FDT_ADDR; 151 env->nip = entry; 152 153 /* Create a mapping for the kernel. */ 154 mmubooke_create_initial_mapping(env, 0, 0); 155 } 156 157 static void bamboo_init(MachineState *machine) 158 { 159 const char *kernel_filename = machine->kernel_filename; 160 const char *kernel_cmdline = machine->kernel_cmdline; 161 const char *initrd_filename = machine->initrd_filename; 162 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; 163 MemoryRegion *address_space_mem = get_system_memory(); 164 MemoryRegion *isa = g_new(MemoryRegion, 1); 165 PCIBus *pcibus; 166 PowerPCCPU *cpu; 167 CPUPPCState *env; 168 target_long initrd_size = 0; 169 DeviceState *dev; 170 DeviceState *uicdev; 171 SysBusDevice *uicsbd; 172 int success; 173 int i; 174 175 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 176 env = &cpu->env; 177 178 if (env->mmu_model != POWERPC_MMU_BOOKE) { 179 error_report("MMU model %i not supported by this machine", 180 env->mmu_model); 181 exit(1); 182 } 183 184 qemu_register_reset(main_cpu_reset, cpu); 185 ppc_booke_timers_init(cpu, 400000000, 0); 186 ppc_dcr_init(env, NULL, NULL); 187 188 /* interrupt controller */ 189 uicdev = qdev_new(TYPE_PPC_UIC); 190 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal); 191 object_unref(OBJECT(uicdev)); 192 uicsbd = SYS_BUS_DEVICE(uicdev); 193 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 194 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 195 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 196 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 197 198 /* SDRAM controller */ 199 dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR); 200 object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), 201 &error_abort); 202 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 203 object_unref(OBJECT(dev)); 204 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 205 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14)); 206 /* Enable SDRAM memory regions, this should be done by the firmware */ 207 ppc4xx_sdram_ddr_enable(PPC4xx_SDRAM_DDR(dev)); 208 209 /* PCI */ 210 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, 211 PPC440EP_PCI_CONFIG, 212 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), 213 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), 214 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), 215 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), 216 NULL); 217 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 218 if (!pcibus) { 219 error_report("couldn't create PCI controller"); 220 exit(1); 221 } 222 223 memory_region_init_alias(isa, NULL, "isa_mmio", 224 get_system_io(), 0, PPC440EP_PCI_IOLEN); 225 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); 226 227 if (serial_hd(0) != NULL) { 228 serial_mm_init(address_space_mem, 0xef600300, 0, 229 qdev_get_gpio_in(uicdev, 0), 230 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 231 DEVICE_BIG_ENDIAN); 232 } 233 if (serial_hd(1) != NULL) { 234 serial_mm_init(address_space_mem, 0xef600400, 0, 235 qdev_get_gpio_in(uicdev, 1), 236 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 237 DEVICE_BIG_ENDIAN); 238 } 239 240 if (pcibus) { 241 /* Register network interfaces. */ 242 for (i = 0; i < nb_nics; i++) { 243 /* 244 * There are no PCI NICs on the Bamboo board, but there are 245 * PCI slots, so we can pick whatever default model we want. 246 */ 247 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); 248 } 249 } 250 251 /* Load kernel. */ 252 if (kernel_filename) { 253 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 254 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, 255 NULL, NULL); 256 if (success < 0) { 257 uint64_t elf_entry; 258 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 259 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 260 entry = elf_entry; 261 } 262 /* XXX try again as binary */ 263 if (success < 0) { 264 error_report("could not load kernel '%s'", kernel_filename); 265 exit(1); 266 } 267 } 268 269 /* Load initrd. */ 270 if (initrd_filename) { 271 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 272 machine->ram_size - RAMDISK_ADDR); 273 274 if (initrd_size < 0) { 275 error_report("could not load ram disk '%s' at %x", 276 initrd_filename, RAMDISK_ADDR); 277 exit(1); 278 } 279 } 280 281 /* If we're loading a kernel directly, we must load the device tree too. */ 282 if (kernel_filename) { 283 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, 284 initrd_size, kernel_cmdline) < 0) { 285 error_report("couldn't load device tree"); 286 exit(1); 287 } 288 } 289 } 290 291 static void bamboo_machine_init(MachineClass *mc) 292 { 293 mc->desc = "bamboo"; 294 mc->init = bamboo_init; 295 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 296 mc->default_ram_id = "ppc4xx.sdram"; 297 } 298 299 DEFINE_MACHINE("bamboo", bamboo_machine_init) 300