1 /* 2 * QEMU PowerPC 440 Bamboo board emulation 3 * 4 * Copyright 2007 IBM Corporation. 5 * Authors: 6 * Jerone Young <jyoung5@us.ibm.com> 7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 8 * Hollis Blanchard <hollisb@us.ibm.com> 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/error-report.h" 17 #include "qemu/datadir.h" 18 #include "qemu/error-report.h" 19 #include "net/net.h" 20 #include "hw/pci/pci.h" 21 #include "hw/boards.h" 22 #include "sysemu/kvm.h" 23 #include "kvm_ppc.h" 24 #include "sysemu/device_tree.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "hw/char/serial.h" 28 #include "hw/ppc/ppc.h" 29 #include "ppc405.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/reset.h" 32 #include "hw/sysbus.h" 33 #include "hw/intc/ppc-uic.h" 34 #include "hw/qdev-properties.h" 35 #include "qapi/error.h" 36 37 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" 38 39 /* from u-boot */ 40 #define KERNEL_ADDR 0x1000000 41 #define FDT_ADDR 0x1800000 42 #define RAMDISK_ADDR 0x1900000 43 44 #define PPC440EP_PCI_CONFIG 0xeec00000 45 #define PPC440EP_PCI_INTACK 0xeed00000 46 #define PPC440EP_PCI_SPECIAL 0xeed00000 47 #define PPC440EP_PCI_REGS 0xef400000 48 #define PPC440EP_PCI_IO 0xe8000000 49 #define PPC440EP_PCI_IOLEN 0x00010000 50 51 #define PPC440EP_SDRAM_NR_BANKS 4 52 53 static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { 54 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 55 }; 56 57 static hwaddr entry; 58 59 static int bamboo_load_device_tree(hwaddr addr, 60 uint32_t ramsize, 61 hwaddr initrd_base, 62 hwaddr initrd_size, 63 const char *kernel_cmdline) 64 { 65 int ret = -1; 66 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 67 char *filename; 68 int fdt_size; 69 void *fdt; 70 uint32_t tb_freq = 400000000; 71 uint32_t clock_freq = 400000000; 72 73 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 74 if (!filename) { 75 return -1; 76 } 77 fdt = load_device_tree(filename, &fdt_size); 78 g_free(filename); 79 if (fdt == NULL) { 80 return -1; 81 } 82 83 /* Manipulate device tree in memory. */ 84 85 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 86 sizeof(mem_reg_property)); 87 if (ret < 0) { 88 fprintf(stderr, "couldn't set /memory/reg\n"); 89 } 90 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 91 initrd_base); 92 if (ret < 0) { 93 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 94 } 95 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 96 (initrd_base + initrd_size)); 97 if (ret < 0) { 98 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 99 } 100 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 101 kernel_cmdline); 102 if (ret < 0) { 103 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 104 } 105 106 /* 107 * Copy data from the host device tree into the guest. Since the guest can 108 * directly access the timebase without host involvement, we must expose 109 * the correct frequencies. 110 */ 111 if (kvm_enabled()) { 112 tb_freq = kvmppc_get_tbfreq(); 113 clock_freq = kvmppc_get_clockfreq(); 114 } 115 116 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 117 clock_freq); 118 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 119 tb_freq); 120 121 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 122 g_free(fdt); 123 return 0; 124 } 125 126 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 127 static void mmubooke_create_initial_mapping(CPUPPCState *env, 128 target_ulong va, 129 hwaddr pa) 130 { 131 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 132 133 tlb->attr = 0; 134 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 135 tlb->size = 1U << 31; /* up to 0x80000000 */ 136 tlb->EPN = va & TARGET_PAGE_MASK; 137 tlb->RPN = pa & TARGET_PAGE_MASK; 138 tlb->PID = 0; 139 140 tlb = &env->tlb.tlbe[1]; 141 tlb->attr = 0; 142 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 143 tlb->size = 1U << 31; /* up to 0xffffffff */ 144 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 145 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 146 tlb->PID = 0; 147 } 148 149 static void main_cpu_reset(void *opaque) 150 { 151 PowerPCCPU *cpu = opaque; 152 CPUPPCState *env = &cpu->env; 153 154 cpu_reset(CPU(cpu)); 155 env->gpr[1] = (16 * MiB) - 8; 156 env->gpr[3] = FDT_ADDR; 157 env->nip = entry; 158 159 /* Create a mapping for the kernel. */ 160 mmubooke_create_initial_mapping(env, 0, 0); 161 } 162 163 static void bamboo_init(MachineState *machine) 164 { 165 const char *kernel_filename = machine->kernel_filename; 166 const char *kernel_cmdline = machine->kernel_cmdline; 167 const char *initrd_filename = machine->initrd_filename; 168 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; 169 MemoryRegion *address_space_mem = get_system_memory(); 170 MemoryRegion *isa = g_new(MemoryRegion, 1); 171 Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 172 PPC440EP_SDRAM_NR_BANKS); 173 PCIBus *pcibus; 174 PowerPCCPU *cpu; 175 CPUPPCState *env; 176 target_long initrd_size = 0; 177 DeviceState *dev; 178 DeviceState *uicdev; 179 SysBusDevice *uicsbd; 180 int success; 181 int i; 182 183 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 184 env = &cpu->env; 185 186 if (env->mmu_model != POWERPC_MMU_BOOKE) { 187 error_report("MMU model %i not supported by this machine", 188 env->mmu_model); 189 exit(1); 190 } 191 192 qemu_register_reset(main_cpu_reset, cpu); 193 ppc_booke_timers_init(cpu, 400000000, 0); 194 ppc_dcr_init(env, NULL, NULL); 195 196 /* interrupt controller */ 197 uicdev = qdev_new(TYPE_PPC_UIC); 198 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal); 199 object_unref(OBJECT(uicdev)); 200 uicsbd = SYS_BUS_DEVICE(uicdev); 201 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 202 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 203 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 204 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 205 206 /* SDRAM controller */ 207 ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks, 208 ppc440ep_sdram_bank_sizes); 209 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 210 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14), 211 PPC440EP_SDRAM_NR_BANKS, ram_banks); 212 /* Enable SDRAM memory regions, this should be done by the firmware */ 213 ppc4xx_sdram_enable(env); 214 215 /* PCI */ 216 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, 217 PPC440EP_PCI_CONFIG, 218 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), 219 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), 220 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), 221 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), 222 NULL); 223 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 224 if (!pcibus) { 225 error_report("couldn't create PCI controller"); 226 exit(1); 227 } 228 229 memory_region_init_alias(isa, NULL, "isa_mmio", 230 get_system_io(), 0, PPC440EP_PCI_IOLEN); 231 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); 232 233 if (serial_hd(0) != NULL) { 234 serial_mm_init(address_space_mem, 0xef600300, 0, 235 qdev_get_gpio_in(uicdev, 0), 236 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 237 DEVICE_BIG_ENDIAN); 238 } 239 if (serial_hd(1) != NULL) { 240 serial_mm_init(address_space_mem, 0xef600400, 0, 241 qdev_get_gpio_in(uicdev, 1), 242 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 243 DEVICE_BIG_ENDIAN); 244 } 245 246 if (pcibus) { 247 /* Register network interfaces. */ 248 for (i = 0; i < nb_nics; i++) { 249 /* 250 * There are no PCI NICs on the Bamboo board, but there are 251 * PCI slots, so we can pick whatever default model we want. 252 */ 253 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); 254 } 255 } 256 257 /* Load kernel. */ 258 if (kernel_filename) { 259 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 260 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, 261 NULL, NULL); 262 if (success < 0) { 263 uint64_t elf_entry; 264 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 265 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 266 entry = elf_entry; 267 } 268 /* XXX try again as binary */ 269 if (success < 0) { 270 error_report("could not load kernel '%s'", kernel_filename); 271 exit(1); 272 } 273 } 274 275 /* Load initrd. */ 276 if (initrd_filename) { 277 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 278 machine->ram_size - RAMDISK_ADDR); 279 280 if (initrd_size < 0) { 281 error_report("could not load ram disk '%s' at %x", 282 initrd_filename, RAMDISK_ADDR); 283 exit(1); 284 } 285 } 286 287 /* If we're loading a kernel directly, we must load the device tree too. */ 288 if (kernel_filename) { 289 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, 290 initrd_size, kernel_cmdline) < 0) { 291 error_report("couldn't load device tree"); 292 exit(1); 293 } 294 } 295 } 296 297 static void bamboo_machine_init(MachineClass *mc) 298 { 299 mc->desc = "bamboo"; 300 mc->init = bamboo_init; 301 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 302 mc->default_ram_id = "ppc4xx.sdram"; 303 } 304 305 DEFINE_MACHINE("bamboo", bamboo_machine_init) 306