1 /* 2 * QEMU PowerPC 440 Bamboo board emulation 3 * 4 * Copyright 2007 IBM Corporation. 5 * Authors: 6 * Jerone Young <jyoung5@us.ibm.com> 7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 8 * Hollis Blanchard <hollisb@us.ibm.com> 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/error-report.h" 17 #include "qemu-common.h" 18 #include "qemu/datadir.h" 19 #include "qemu/error-report.h" 20 #include "net/net.h" 21 #include "hw/pci/pci.h" 22 #include "hw/boards.h" 23 #include "sysemu/kvm.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/device_tree.h" 26 #include "hw/loader.h" 27 #include "elf.h" 28 #include "exec/address-spaces.h" 29 #include "hw/char/serial.h" 30 #include "hw/ppc/ppc.h" 31 #include "ppc405.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/reset.h" 34 #include "hw/sysbus.h" 35 #include "hw/intc/ppc-uic.h" 36 #include "hw/qdev-properties.h" 37 #include "qapi/error.h" 38 39 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" 40 41 /* from u-boot */ 42 #define KERNEL_ADDR 0x1000000 43 #define FDT_ADDR 0x1800000 44 #define RAMDISK_ADDR 0x1900000 45 46 #define PPC440EP_PCI_CONFIG 0xeec00000 47 #define PPC440EP_PCI_INTACK 0xeed00000 48 #define PPC440EP_PCI_SPECIAL 0xeed00000 49 #define PPC440EP_PCI_REGS 0xef400000 50 #define PPC440EP_PCI_IO 0xe8000000 51 #define PPC440EP_PCI_IOLEN 0x00010000 52 53 #define PPC440EP_SDRAM_NR_BANKS 4 54 55 static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { 56 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 57 }; 58 59 static hwaddr entry; 60 61 static int bamboo_load_device_tree(hwaddr addr, 62 uint32_t ramsize, 63 hwaddr initrd_base, 64 hwaddr initrd_size, 65 const char *kernel_cmdline) 66 { 67 int ret = -1; 68 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 69 char *filename; 70 int fdt_size; 71 void *fdt; 72 uint32_t tb_freq = 400000000; 73 uint32_t clock_freq = 400000000; 74 75 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 76 if (!filename) { 77 return -1; 78 } 79 fdt = load_device_tree(filename, &fdt_size); 80 g_free(filename); 81 if (fdt == NULL) { 82 return -1; 83 } 84 85 /* Manipulate device tree in memory. */ 86 87 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 88 sizeof(mem_reg_property)); 89 if (ret < 0) 90 fprintf(stderr, "couldn't set /memory/reg\n"); 91 92 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 93 initrd_base); 94 if (ret < 0) 95 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 96 97 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 98 (initrd_base + initrd_size)); 99 if (ret < 0) 100 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 101 102 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 103 kernel_cmdline); 104 if (ret < 0) 105 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 106 107 /* Copy data from the host device tree into the guest. Since the guest can 108 * directly access the timebase without host involvement, we must expose 109 * the correct frequencies. */ 110 if (kvm_enabled()) { 111 tb_freq = kvmppc_get_tbfreq(); 112 clock_freq = kvmppc_get_clockfreq(); 113 } 114 115 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 116 clock_freq); 117 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 118 tb_freq); 119 120 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 121 g_free(fdt); 122 return 0; 123 } 124 125 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 126 static void mmubooke_create_initial_mapping(CPUPPCState *env, 127 target_ulong va, 128 hwaddr pa) 129 { 130 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 131 132 tlb->attr = 0; 133 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 134 tlb->size = 1U << 31; /* up to 0x80000000 */ 135 tlb->EPN = va & TARGET_PAGE_MASK; 136 tlb->RPN = pa & TARGET_PAGE_MASK; 137 tlb->PID = 0; 138 139 tlb = &env->tlb.tlbe[1]; 140 tlb->attr = 0; 141 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 142 tlb->size = 1U << 31; /* up to 0xffffffff */ 143 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 144 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 145 tlb->PID = 0; 146 } 147 148 static void main_cpu_reset(void *opaque) 149 { 150 PowerPCCPU *cpu = opaque; 151 CPUPPCState *env = &cpu->env; 152 153 cpu_reset(CPU(cpu)); 154 env->gpr[1] = (16 * MiB) - 8; 155 env->gpr[3] = FDT_ADDR; 156 env->nip = entry; 157 158 /* Create a mapping for the kernel. */ 159 mmubooke_create_initial_mapping(env, 0, 0); 160 } 161 162 static void bamboo_init(MachineState *machine) 163 { 164 const char *kernel_filename = machine->kernel_filename; 165 const char *kernel_cmdline = machine->kernel_cmdline; 166 const char *initrd_filename = machine->initrd_filename; 167 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; 168 MemoryRegion *address_space_mem = get_system_memory(); 169 MemoryRegion *isa = g_new(MemoryRegion, 1); 170 MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); 171 hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; 172 hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; 173 PCIBus *pcibus; 174 PowerPCCPU *cpu; 175 CPUPPCState *env; 176 target_long initrd_size = 0; 177 DeviceState *dev; 178 DeviceState *uicdev; 179 SysBusDevice *uicsbd; 180 int success; 181 int i; 182 183 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 184 env = &cpu->env; 185 186 if (env->mmu_model != POWERPC_MMU_BOOKE) { 187 error_report("MMU model %i not supported by this machine", 188 env->mmu_model); 189 exit(1); 190 } 191 192 qemu_register_reset(main_cpu_reset, cpu); 193 ppc_booke_timers_init(cpu, 400000000, 0); 194 ppc_dcr_init(env, NULL, NULL); 195 196 /* interrupt controller */ 197 uicdev = qdev_new(TYPE_PPC_UIC); 198 uicsbd = SYS_BUS_DEVICE(uicdev); 199 200 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 201 &error_fatal); 202 sysbus_realize_and_unref(uicsbd, &error_fatal); 203 204 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 205 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 206 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 207 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 208 209 /* SDRAM controller */ 210 memset(ram_bases, 0, sizeof(ram_bases)); 211 memset(ram_sizes, 0, sizeof(ram_sizes)); 212 ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, 213 ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); 214 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 215 ppc4xx_sdram_init(env, 216 qdev_get_gpio_in(uicdev, 14), 217 PPC440EP_SDRAM_NR_BANKS, ram_memories, 218 ram_bases, ram_sizes, 1); 219 220 /* PCI */ 221 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, 222 PPC440EP_PCI_CONFIG, 223 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), 224 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), 225 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), 226 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), 227 NULL); 228 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 229 if (!pcibus) { 230 error_report("couldn't create PCI controller"); 231 exit(1); 232 } 233 234 memory_region_init_alias(isa, NULL, "isa_mmio", 235 get_system_io(), 0, PPC440EP_PCI_IOLEN); 236 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); 237 238 if (serial_hd(0) != NULL) { 239 serial_mm_init(address_space_mem, 0xef600300, 0, 240 qdev_get_gpio_in(uicdev, 0), 241 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 242 DEVICE_BIG_ENDIAN); 243 } 244 if (serial_hd(1) != NULL) { 245 serial_mm_init(address_space_mem, 0xef600400, 0, 246 qdev_get_gpio_in(uicdev, 1), 247 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 248 DEVICE_BIG_ENDIAN); 249 } 250 251 if (pcibus) { 252 /* Register network interfaces. */ 253 for (i = 0; i < nb_nics; i++) { 254 /* There are no PCI NICs on the Bamboo board, but there are 255 * PCI slots, so we can pick whatever default model we want. */ 256 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); 257 } 258 } 259 260 /* Load kernel. */ 261 if (kernel_filename) { 262 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 263 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, 264 NULL, NULL); 265 if (success < 0) { 266 uint64_t elf_entry; 267 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 268 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 269 entry = elf_entry; 270 } 271 /* XXX try again as binary */ 272 if (success < 0) { 273 error_report("could not load kernel '%s'", kernel_filename); 274 exit(1); 275 } 276 } 277 278 /* Load initrd. */ 279 if (initrd_filename) { 280 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 281 machine->ram_size - RAMDISK_ADDR); 282 283 if (initrd_size < 0) { 284 error_report("could not load ram disk '%s' at %x", 285 initrd_filename, RAMDISK_ADDR); 286 exit(1); 287 } 288 } 289 290 /* If we're loading a kernel directly, we must load the device tree too. */ 291 if (kernel_filename) { 292 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, 293 initrd_size, kernel_cmdline) < 0) { 294 error_report("couldn't load device tree"); 295 exit(1); 296 } 297 } 298 } 299 300 static void bamboo_machine_init(MachineClass *mc) 301 { 302 mc->desc = "bamboo"; 303 mc->init = bamboo_init; 304 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 305 mc->default_ram_id = "ppc4xx.sdram"; 306 } 307 308 DEFINE_MACHINE("bamboo", bamboo_machine_init) 309