1 /* 2 * QEMU PowerPC 440 Bamboo board emulation 3 * 4 * Copyright 2007 IBM Corporation. 5 * Authors: 6 * Jerone Young <jyoung5@us.ibm.com> 7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 8 * Hollis Blanchard <hollisb@us.ibm.com> 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/datadir.h" 17 #include "qemu/error-report.h" 18 #include "net/net.h" 19 #include "hw/pci/pci.h" 20 #include "hw/boards.h" 21 #include "sysemu/kvm.h" 22 #include "kvm_ppc.h" 23 #include "sysemu/device_tree.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "hw/char/serial.h" 27 #include "hw/ppc/ppc.h" 28 #include "ppc405.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/reset.h" 31 #include "hw/sysbus.h" 32 #include "hw/intc/ppc-uic.h" 33 #include "hw/qdev-properties.h" 34 #include "qapi/error.h" 35 36 #include <libfdt.h> 37 38 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" 39 40 /* from u-boot */ 41 #define KERNEL_ADDR 0x1000000 42 #define FDT_ADDR 0x1800000 43 #define RAMDISK_ADDR 0x1900000 44 45 #define PPC440EP_PCI_CONFIG 0xeec00000 46 #define PPC440EP_PCI_INTACK 0xeed00000 47 #define PPC440EP_PCI_SPECIAL 0xeed00000 48 #define PPC440EP_PCI_REGS 0xef400000 49 #define PPC440EP_PCI_IO 0xe8000000 50 #define PPC440EP_PCI_IOLEN 0x00010000 51 52 static hwaddr entry; 53 54 static int bamboo_load_device_tree(MachineState *machine, 55 hwaddr addr, 56 hwaddr initrd_base, 57 hwaddr initrd_size) 58 { 59 int ret = -1; 60 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; 61 char *filename; 62 int fdt_size; 63 void *fdt; 64 uint32_t tb_freq = 400000000; 65 uint32_t clock_freq = 400000000; 66 67 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 68 if (!filename) { 69 return -1; 70 } 71 fdt = load_device_tree(filename, &fdt_size); 72 g_free(filename); 73 if (fdt == NULL) { 74 return -1; 75 } 76 77 /* Manipulate device tree in memory. */ 78 79 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 80 sizeof(mem_reg_property)); 81 if (ret < 0) { 82 fprintf(stderr, "couldn't set /memory/reg\n"); 83 } 84 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 85 initrd_base); 86 if (ret < 0) { 87 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 88 } 89 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 90 (initrd_base + initrd_size)); 91 if (ret < 0) { 92 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 93 } 94 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 95 machine->kernel_cmdline); 96 if (ret < 0) { 97 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 98 } 99 100 /* 101 * Copy data from the host device tree into the guest. Since the guest can 102 * directly access the timebase without host involvement, we must expose 103 * the correct frequencies. 104 */ 105 if (kvm_enabled()) { 106 tb_freq = kvmppc_get_tbfreq(); 107 clock_freq = kvmppc_get_clockfreq(); 108 } 109 110 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 111 clock_freq); 112 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 113 tb_freq); 114 115 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 116 117 /* Set ms->fdt for 'dumpdtb' QMP/HMP command */ 118 machine->fdt = fdt; 119 120 return 0; 121 } 122 123 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 124 static void mmubooke_create_initial_mapping(CPUPPCState *env, 125 target_ulong va, 126 hwaddr pa) 127 { 128 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 129 130 tlb->attr = 0; 131 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 132 tlb->size = 1U << 31; /* up to 0x80000000 */ 133 tlb->EPN = va & TARGET_PAGE_MASK; 134 tlb->RPN = pa & TARGET_PAGE_MASK; 135 tlb->PID = 0; 136 137 tlb = &env->tlb.tlbe[1]; 138 tlb->attr = 0; 139 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 140 tlb->size = 1U << 31; /* up to 0xffffffff */ 141 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 142 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 143 tlb->PID = 0; 144 } 145 146 static void main_cpu_reset(void *opaque) 147 { 148 PowerPCCPU *cpu = opaque; 149 CPUPPCState *env = &cpu->env; 150 151 cpu_reset(CPU(cpu)); 152 env->gpr[1] = (16 * MiB) - 8; 153 env->gpr[3] = FDT_ADDR; 154 env->nip = entry; 155 156 /* Create a mapping for the kernel. */ 157 mmubooke_create_initial_mapping(env, 0, 0); 158 } 159 160 static void bamboo_init(MachineState *machine) 161 { 162 const char *kernel_filename = machine->kernel_filename; 163 const char *initrd_filename = machine->initrd_filename; 164 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; 165 MemoryRegion *address_space_mem = get_system_memory(); 166 MemoryRegion *isa = g_new(MemoryRegion, 1); 167 PCIBus *pcibus; 168 PowerPCCPU *cpu; 169 CPUPPCState *env; 170 target_long initrd_size = 0; 171 DeviceState *dev; 172 DeviceState *uicdev; 173 SysBusDevice *uicsbd; 174 int success; 175 int i; 176 177 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 178 env = &cpu->env; 179 180 if (env->mmu_model != POWERPC_MMU_BOOKE) { 181 error_report("MMU model %i not supported by this machine", 182 env->mmu_model); 183 exit(1); 184 } 185 186 qemu_register_reset(main_cpu_reset, cpu); 187 ppc_booke_timers_init(cpu, 400000000, 0); 188 ppc_dcr_init(env, NULL, NULL); 189 190 /* interrupt controller */ 191 uicdev = qdev_new(TYPE_PPC_UIC); 192 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal); 193 object_unref(OBJECT(uicdev)); 194 uicsbd = SYS_BUS_DEVICE(uicdev); 195 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 196 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 197 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 198 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 199 200 /* SDRAM controller */ 201 dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR); 202 object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), 203 &error_abort); 204 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 205 object_unref(OBJECT(dev)); 206 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 207 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14)); 208 /* Enable SDRAM memory regions, this should be done by the firmware */ 209 ppc4xx_sdram_ddr_enable(PPC4xx_SDRAM_DDR(dev)); 210 211 /* PCI */ 212 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, 213 PPC440EP_PCI_CONFIG, 214 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), 215 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), 216 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), 217 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), 218 NULL); 219 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 220 if (!pcibus) { 221 error_report("couldn't create PCI controller"); 222 exit(1); 223 } 224 225 memory_region_init_alias(isa, NULL, "isa_mmio", 226 get_system_io(), 0, PPC440EP_PCI_IOLEN); 227 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); 228 229 if (serial_hd(0) != NULL) { 230 serial_mm_init(address_space_mem, 0xef600300, 0, 231 qdev_get_gpio_in(uicdev, 0), 232 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 233 DEVICE_BIG_ENDIAN); 234 } 235 if (serial_hd(1) != NULL) { 236 serial_mm_init(address_space_mem, 0xef600400, 0, 237 qdev_get_gpio_in(uicdev, 1), 238 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 239 DEVICE_BIG_ENDIAN); 240 } 241 242 if (pcibus) { 243 /* Register network interfaces. */ 244 for (i = 0; i < nb_nics; i++) { 245 /* 246 * There are no PCI NICs on the Bamboo board, but there are 247 * PCI slots, so we can pick whatever default model we want. 248 */ 249 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); 250 } 251 } 252 253 /* Load kernel. */ 254 if (kernel_filename) { 255 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 256 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, 257 NULL, NULL); 258 if (success < 0) { 259 uint64_t elf_entry; 260 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 261 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 262 entry = elf_entry; 263 } 264 /* XXX try again as binary */ 265 if (success < 0) { 266 error_report("could not load kernel '%s'", kernel_filename); 267 exit(1); 268 } 269 } 270 271 /* Load initrd. */ 272 if (initrd_filename) { 273 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 274 machine->ram_size - RAMDISK_ADDR); 275 276 if (initrd_size < 0) { 277 error_report("could not load ram disk '%s' at %x", 278 initrd_filename, RAMDISK_ADDR); 279 exit(1); 280 } 281 } 282 283 /* If we're loading a kernel directly, we must load the device tree too. */ 284 if (kernel_filename) { 285 if (bamboo_load_device_tree(machine, FDT_ADDR, 286 RAMDISK_ADDR, initrd_size) < 0) { 287 error_report("couldn't load device tree"); 288 exit(1); 289 } 290 } 291 } 292 293 static void bamboo_machine_init(MachineClass *mc) 294 { 295 mc->desc = "bamboo"; 296 mc->init = bamboo_init; 297 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 298 mc->default_ram_id = "ppc4xx.sdram"; 299 } 300 301 DEFINE_MACHINE("bamboo", bamboo_machine_init) 302