1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "hw/boards.h" 31 #include "hw/i2c/ppc4xx_i2c.h" 32 #include "ppc405.h" 33 #include "hw/char/serial.h" 34 #include "qemu/timer.h" 35 #include "sysemu/sysemu.h" 36 #include "qemu/log.h" 37 #include "exec/address-spaces.h" 38 39 //#define DEBUG_OPBA 40 //#define DEBUG_SDRAM 41 //#define DEBUG_GPIO 42 //#define DEBUG_SERIAL 43 //#define DEBUG_OCM 44 //#define DEBUG_GPT 45 //#define DEBUG_CLOCKS 46 //#define DEBUG_CLOCKS_LL 47 48 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 49 uint32_t flags) 50 { 51 CPUState *cs = CPU(ppc_env_get_cpu(env)); 52 ram_addr_t bdloc; 53 int i, n; 54 55 /* We put the bd structure at the top of memory */ 56 if (bd->bi_memsize >= 0x01000000UL) 57 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 58 else 59 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 60 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 61 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 62 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 63 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 64 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 65 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 66 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 67 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 68 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 69 for (i = 0; i < 6; i++) { 70 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 71 } 72 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 73 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 74 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 75 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 76 for (i = 0; i < 4; i++) { 77 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 78 } 79 for (i = 0; i < 32; i++) { 80 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 81 } 82 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 83 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 84 for (i = 0; i < 6; i++) { 85 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 86 } 87 n = 0x6A; 88 if (flags & 0x00000001) { 89 for (i = 0; i < 6; i++) 90 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 91 } 92 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 93 n += 4; 94 for (i = 0; i < 2; i++) { 95 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 96 n += 4; 97 } 98 99 return bdloc; 100 } 101 102 /*****************************************************************************/ 103 /* Shared peripherals */ 104 105 /*****************************************************************************/ 106 /* Peripheral local bus arbitrer */ 107 enum { 108 PLB3A0_ACR = 0x077, 109 PLB4A0_ACR = 0x081, 110 PLB0_BESR = 0x084, 111 PLB0_BEAR = 0x086, 112 PLB0_ACR = 0x087, 113 PLB4A1_ACR = 0x089, 114 }; 115 116 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 117 struct ppc4xx_plb_t { 118 uint32_t acr; 119 uint32_t bear; 120 uint32_t besr; 121 }; 122 123 static uint32_t dcr_read_plb (void *opaque, int dcrn) 124 { 125 ppc4xx_plb_t *plb; 126 uint32_t ret; 127 128 plb = opaque; 129 switch (dcrn) { 130 case PLB0_ACR: 131 ret = plb->acr; 132 break; 133 case PLB0_BEAR: 134 ret = plb->bear; 135 break; 136 case PLB0_BESR: 137 ret = plb->besr; 138 break; 139 default: 140 /* Avoid gcc warning */ 141 ret = 0; 142 break; 143 } 144 145 return ret; 146 } 147 148 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 149 { 150 ppc4xx_plb_t *plb; 151 152 plb = opaque; 153 switch (dcrn) { 154 case PLB0_ACR: 155 /* We don't care about the actual parameters written as 156 * we don't manage any priorities on the bus 157 */ 158 plb->acr = val & 0xF8000000; 159 break; 160 case PLB0_BEAR: 161 /* Read only */ 162 break; 163 case PLB0_BESR: 164 /* Write-clear */ 165 plb->besr &= ~val; 166 break; 167 } 168 } 169 170 static void ppc4xx_plb_reset (void *opaque) 171 { 172 ppc4xx_plb_t *plb; 173 174 plb = opaque; 175 plb->acr = 0x00000000; 176 plb->bear = 0x00000000; 177 plb->besr = 0x00000000; 178 } 179 180 void ppc4xx_plb_init(CPUPPCState *env) 181 { 182 ppc4xx_plb_t *plb; 183 184 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 185 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 186 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 187 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 188 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 189 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 190 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 191 qemu_register_reset(ppc4xx_plb_reset, plb); 192 } 193 194 /*****************************************************************************/ 195 /* PLB to OPB bridge */ 196 enum { 197 POB0_BESR0 = 0x0A0, 198 POB0_BESR1 = 0x0A2, 199 POB0_BEAR = 0x0A4, 200 }; 201 202 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 203 struct ppc4xx_pob_t { 204 uint32_t bear; 205 uint32_t besr0; 206 uint32_t besr1; 207 }; 208 209 static uint32_t dcr_read_pob (void *opaque, int dcrn) 210 { 211 ppc4xx_pob_t *pob; 212 uint32_t ret; 213 214 pob = opaque; 215 switch (dcrn) { 216 case POB0_BEAR: 217 ret = pob->bear; 218 break; 219 case POB0_BESR0: 220 ret = pob->besr0; 221 break; 222 case POB0_BESR1: 223 ret = pob->besr1; 224 break; 225 default: 226 /* Avoid gcc warning */ 227 ret = 0; 228 break; 229 } 230 231 return ret; 232 } 233 234 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 235 { 236 ppc4xx_pob_t *pob; 237 238 pob = opaque; 239 switch (dcrn) { 240 case POB0_BEAR: 241 /* Read only */ 242 break; 243 case POB0_BESR0: 244 /* Write-clear */ 245 pob->besr0 &= ~val; 246 break; 247 case POB0_BESR1: 248 /* Write-clear */ 249 pob->besr1 &= ~val; 250 break; 251 } 252 } 253 254 static void ppc4xx_pob_reset (void *opaque) 255 { 256 ppc4xx_pob_t *pob; 257 258 pob = opaque; 259 /* No error */ 260 pob->bear = 0x00000000; 261 pob->besr0 = 0x0000000; 262 pob->besr1 = 0x0000000; 263 } 264 265 static void ppc4xx_pob_init(CPUPPCState *env) 266 { 267 ppc4xx_pob_t *pob; 268 269 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 270 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 271 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 272 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 273 qemu_register_reset(ppc4xx_pob_reset, pob); 274 } 275 276 /*****************************************************************************/ 277 /* OPB arbitrer */ 278 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 279 struct ppc4xx_opba_t { 280 MemoryRegion io; 281 uint8_t cr; 282 uint8_t pr; 283 }; 284 285 static uint32_t opba_readb (void *opaque, hwaddr addr) 286 { 287 ppc4xx_opba_t *opba; 288 uint32_t ret; 289 290 #ifdef DEBUG_OPBA 291 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 292 #endif 293 opba = opaque; 294 switch (addr) { 295 case 0x00: 296 ret = opba->cr; 297 break; 298 case 0x01: 299 ret = opba->pr; 300 break; 301 default: 302 ret = 0x00; 303 break; 304 } 305 306 return ret; 307 } 308 309 static void opba_writeb (void *opaque, 310 hwaddr addr, uint32_t value) 311 { 312 ppc4xx_opba_t *opba; 313 314 #ifdef DEBUG_OPBA 315 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 316 value); 317 #endif 318 opba = opaque; 319 switch (addr) { 320 case 0x00: 321 opba->cr = value & 0xF8; 322 break; 323 case 0x01: 324 opba->pr = value & 0xFF; 325 break; 326 default: 327 break; 328 } 329 } 330 331 static uint32_t opba_readw (void *opaque, hwaddr addr) 332 { 333 uint32_t ret; 334 335 #ifdef DEBUG_OPBA 336 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 337 #endif 338 ret = opba_readb(opaque, addr) << 8; 339 ret |= opba_readb(opaque, addr + 1); 340 341 return ret; 342 } 343 344 static void opba_writew (void *opaque, 345 hwaddr addr, uint32_t value) 346 { 347 #ifdef DEBUG_OPBA 348 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 349 value); 350 #endif 351 opba_writeb(opaque, addr, value >> 8); 352 opba_writeb(opaque, addr + 1, value); 353 } 354 355 static uint32_t opba_readl (void *opaque, hwaddr addr) 356 { 357 uint32_t ret; 358 359 #ifdef DEBUG_OPBA 360 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 361 #endif 362 ret = opba_readb(opaque, addr) << 24; 363 ret |= opba_readb(opaque, addr + 1) << 16; 364 365 return ret; 366 } 367 368 static void opba_writel (void *opaque, 369 hwaddr addr, uint32_t value) 370 { 371 #ifdef DEBUG_OPBA 372 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 373 value); 374 #endif 375 opba_writeb(opaque, addr, value >> 24); 376 opba_writeb(opaque, addr + 1, value >> 16); 377 } 378 379 static const MemoryRegionOps opba_ops = { 380 .old_mmio = { 381 .read = { opba_readb, opba_readw, opba_readl, }, 382 .write = { opba_writeb, opba_writew, opba_writel, }, 383 }, 384 .endianness = DEVICE_NATIVE_ENDIAN, 385 }; 386 387 static void ppc4xx_opba_reset (void *opaque) 388 { 389 ppc4xx_opba_t *opba; 390 391 opba = opaque; 392 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 393 opba->pr = 0x11; 394 } 395 396 static void ppc4xx_opba_init(hwaddr base) 397 { 398 ppc4xx_opba_t *opba; 399 400 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 401 #ifdef DEBUG_OPBA 402 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 403 #endif 404 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 405 memory_region_add_subregion(get_system_memory(), base, &opba->io); 406 qemu_register_reset(ppc4xx_opba_reset, opba); 407 } 408 409 /*****************************************************************************/ 410 /* Code decompression controller */ 411 /* XXX: TODO */ 412 413 /*****************************************************************************/ 414 /* Peripheral controller */ 415 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 416 struct ppc4xx_ebc_t { 417 uint32_t addr; 418 uint32_t bcr[8]; 419 uint32_t bap[8]; 420 uint32_t bear; 421 uint32_t besr0; 422 uint32_t besr1; 423 uint32_t cfg; 424 }; 425 426 enum { 427 EBC0_CFGADDR = 0x012, 428 EBC0_CFGDATA = 0x013, 429 }; 430 431 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 432 { 433 ppc4xx_ebc_t *ebc; 434 uint32_t ret; 435 436 ebc = opaque; 437 switch (dcrn) { 438 case EBC0_CFGADDR: 439 ret = ebc->addr; 440 break; 441 case EBC0_CFGDATA: 442 switch (ebc->addr) { 443 case 0x00: /* B0CR */ 444 ret = ebc->bcr[0]; 445 break; 446 case 0x01: /* B1CR */ 447 ret = ebc->bcr[1]; 448 break; 449 case 0x02: /* B2CR */ 450 ret = ebc->bcr[2]; 451 break; 452 case 0x03: /* B3CR */ 453 ret = ebc->bcr[3]; 454 break; 455 case 0x04: /* B4CR */ 456 ret = ebc->bcr[4]; 457 break; 458 case 0x05: /* B5CR */ 459 ret = ebc->bcr[5]; 460 break; 461 case 0x06: /* B6CR */ 462 ret = ebc->bcr[6]; 463 break; 464 case 0x07: /* B7CR */ 465 ret = ebc->bcr[7]; 466 break; 467 case 0x10: /* B0AP */ 468 ret = ebc->bap[0]; 469 break; 470 case 0x11: /* B1AP */ 471 ret = ebc->bap[1]; 472 break; 473 case 0x12: /* B2AP */ 474 ret = ebc->bap[2]; 475 break; 476 case 0x13: /* B3AP */ 477 ret = ebc->bap[3]; 478 break; 479 case 0x14: /* B4AP */ 480 ret = ebc->bap[4]; 481 break; 482 case 0x15: /* B5AP */ 483 ret = ebc->bap[5]; 484 break; 485 case 0x16: /* B6AP */ 486 ret = ebc->bap[6]; 487 break; 488 case 0x17: /* B7AP */ 489 ret = ebc->bap[7]; 490 break; 491 case 0x20: /* BEAR */ 492 ret = ebc->bear; 493 break; 494 case 0x21: /* BESR0 */ 495 ret = ebc->besr0; 496 break; 497 case 0x22: /* BESR1 */ 498 ret = ebc->besr1; 499 break; 500 case 0x23: /* CFG */ 501 ret = ebc->cfg; 502 break; 503 default: 504 ret = 0x00000000; 505 break; 506 } 507 break; 508 default: 509 ret = 0x00000000; 510 break; 511 } 512 513 return ret; 514 } 515 516 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 517 { 518 ppc4xx_ebc_t *ebc; 519 520 ebc = opaque; 521 switch (dcrn) { 522 case EBC0_CFGADDR: 523 ebc->addr = val; 524 break; 525 case EBC0_CFGDATA: 526 switch (ebc->addr) { 527 case 0x00: /* B0CR */ 528 break; 529 case 0x01: /* B1CR */ 530 break; 531 case 0x02: /* B2CR */ 532 break; 533 case 0x03: /* B3CR */ 534 break; 535 case 0x04: /* B4CR */ 536 break; 537 case 0x05: /* B5CR */ 538 break; 539 case 0x06: /* B6CR */ 540 break; 541 case 0x07: /* B7CR */ 542 break; 543 case 0x10: /* B0AP */ 544 break; 545 case 0x11: /* B1AP */ 546 break; 547 case 0x12: /* B2AP */ 548 break; 549 case 0x13: /* B3AP */ 550 break; 551 case 0x14: /* B4AP */ 552 break; 553 case 0x15: /* B5AP */ 554 break; 555 case 0x16: /* B6AP */ 556 break; 557 case 0x17: /* B7AP */ 558 break; 559 case 0x20: /* BEAR */ 560 break; 561 case 0x21: /* BESR0 */ 562 break; 563 case 0x22: /* BESR1 */ 564 break; 565 case 0x23: /* CFG */ 566 break; 567 default: 568 break; 569 } 570 break; 571 default: 572 break; 573 } 574 } 575 576 static void ebc_reset (void *opaque) 577 { 578 ppc4xx_ebc_t *ebc; 579 int i; 580 581 ebc = opaque; 582 ebc->addr = 0x00000000; 583 ebc->bap[0] = 0x7F8FFE80; 584 ebc->bcr[0] = 0xFFE28000; 585 for (i = 0; i < 8; i++) { 586 ebc->bap[i] = 0x00000000; 587 ebc->bcr[i] = 0x00000000; 588 } 589 ebc->besr0 = 0x00000000; 590 ebc->besr1 = 0x00000000; 591 ebc->cfg = 0x80400000; 592 } 593 594 void ppc405_ebc_init(CPUPPCState *env) 595 { 596 ppc4xx_ebc_t *ebc; 597 598 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 599 qemu_register_reset(&ebc_reset, ebc); 600 ppc_dcr_register(env, EBC0_CFGADDR, 601 ebc, &dcr_read_ebc, &dcr_write_ebc); 602 ppc_dcr_register(env, EBC0_CFGDATA, 603 ebc, &dcr_read_ebc, &dcr_write_ebc); 604 } 605 606 /*****************************************************************************/ 607 /* DMA controller */ 608 enum { 609 DMA0_CR0 = 0x100, 610 DMA0_CT0 = 0x101, 611 DMA0_DA0 = 0x102, 612 DMA0_SA0 = 0x103, 613 DMA0_SG0 = 0x104, 614 DMA0_CR1 = 0x108, 615 DMA0_CT1 = 0x109, 616 DMA0_DA1 = 0x10A, 617 DMA0_SA1 = 0x10B, 618 DMA0_SG1 = 0x10C, 619 DMA0_CR2 = 0x110, 620 DMA0_CT2 = 0x111, 621 DMA0_DA2 = 0x112, 622 DMA0_SA2 = 0x113, 623 DMA0_SG2 = 0x114, 624 DMA0_CR3 = 0x118, 625 DMA0_CT3 = 0x119, 626 DMA0_DA3 = 0x11A, 627 DMA0_SA3 = 0x11B, 628 DMA0_SG3 = 0x11C, 629 DMA0_SR = 0x120, 630 DMA0_SGC = 0x123, 631 DMA0_SLP = 0x125, 632 DMA0_POL = 0x126, 633 }; 634 635 typedef struct ppc405_dma_t ppc405_dma_t; 636 struct ppc405_dma_t { 637 qemu_irq irqs[4]; 638 uint32_t cr[4]; 639 uint32_t ct[4]; 640 uint32_t da[4]; 641 uint32_t sa[4]; 642 uint32_t sg[4]; 643 uint32_t sr; 644 uint32_t sgc; 645 uint32_t slp; 646 uint32_t pol; 647 }; 648 649 static uint32_t dcr_read_dma (void *opaque, int dcrn) 650 { 651 return 0; 652 } 653 654 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 655 { 656 } 657 658 static void ppc405_dma_reset (void *opaque) 659 { 660 ppc405_dma_t *dma; 661 int i; 662 663 dma = opaque; 664 for (i = 0; i < 4; i++) { 665 dma->cr[i] = 0x00000000; 666 dma->ct[i] = 0x00000000; 667 dma->da[i] = 0x00000000; 668 dma->sa[i] = 0x00000000; 669 dma->sg[i] = 0x00000000; 670 } 671 dma->sr = 0x00000000; 672 dma->sgc = 0x00000000; 673 dma->slp = 0x7C000000; 674 dma->pol = 0x00000000; 675 } 676 677 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 678 { 679 ppc405_dma_t *dma; 680 681 dma = g_malloc0(sizeof(ppc405_dma_t)); 682 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 683 qemu_register_reset(&ppc405_dma_reset, dma); 684 ppc_dcr_register(env, DMA0_CR0, 685 dma, &dcr_read_dma, &dcr_write_dma); 686 ppc_dcr_register(env, DMA0_CT0, 687 dma, &dcr_read_dma, &dcr_write_dma); 688 ppc_dcr_register(env, DMA0_DA0, 689 dma, &dcr_read_dma, &dcr_write_dma); 690 ppc_dcr_register(env, DMA0_SA0, 691 dma, &dcr_read_dma, &dcr_write_dma); 692 ppc_dcr_register(env, DMA0_SG0, 693 dma, &dcr_read_dma, &dcr_write_dma); 694 ppc_dcr_register(env, DMA0_CR1, 695 dma, &dcr_read_dma, &dcr_write_dma); 696 ppc_dcr_register(env, DMA0_CT1, 697 dma, &dcr_read_dma, &dcr_write_dma); 698 ppc_dcr_register(env, DMA0_DA1, 699 dma, &dcr_read_dma, &dcr_write_dma); 700 ppc_dcr_register(env, DMA0_SA1, 701 dma, &dcr_read_dma, &dcr_write_dma); 702 ppc_dcr_register(env, DMA0_SG1, 703 dma, &dcr_read_dma, &dcr_write_dma); 704 ppc_dcr_register(env, DMA0_CR2, 705 dma, &dcr_read_dma, &dcr_write_dma); 706 ppc_dcr_register(env, DMA0_CT2, 707 dma, &dcr_read_dma, &dcr_write_dma); 708 ppc_dcr_register(env, DMA0_DA2, 709 dma, &dcr_read_dma, &dcr_write_dma); 710 ppc_dcr_register(env, DMA0_SA2, 711 dma, &dcr_read_dma, &dcr_write_dma); 712 ppc_dcr_register(env, DMA0_SG2, 713 dma, &dcr_read_dma, &dcr_write_dma); 714 ppc_dcr_register(env, DMA0_CR3, 715 dma, &dcr_read_dma, &dcr_write_dma); 716 ppc_dcr_register(env, DMA0_CT3, 717 dma, &dcr_read_dma, &dcr_write_dma); 718 ppc_dcr_register(env, DMA0_DA3, 719 dma, &dcr_read_dma, &dcr_write_dma); 720 ppc_dcr_register(env, DMA0_SA3, 721 dma, &dcr_read_dma, &dcr_write_dma); 722 ppc_dcr_register(env, DMA0_SG3, 723 dma, &dcr_read_dma, &dcr_write_dma); 724 ppc_dcr_register(env, DMA0_SR, 725 dma, &dcr_read_dma, &dcr_write_dma); 726 ppc_dcr_register(env, DMA0_SGC, 727 dma, &dcr_read_dma, &dcr_write_dma); 728 ppc_dcr_register(env, DMA0_SLP, 729 dma, &dcr_read_dma, &dcr_write_dma); 730 ppc_dcr_register(env, DMA0_POL, 731 dma, &dcr_read_dma, &dcr_write_dma); 732 } 733 734 /*****************************************************************************/ 735 /* GPIO */ 736 typedef struct ppc405_gpio_t ppc405_gpio_t; 737 struct ppc405_gpio_t { 738 MemoryRegion io; 739 uint32_t or; 740 uint32_t tcr; 741 uint32_t osrh; 742 uint32_t osrl; 743 uint32_t tsrh; 744 uint32_t tsrl; 745 uint32_t odr; 746 uint32_t ir; 747 uint32_t rr1; 748 uint32_t isr1h; 749 uint32_t isr1l; 750 }; 751 752 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr) 753 { 754 #ifdef DEBUG_GPIO 755 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 756 #endif 757 758 return 0; 759 } 760 761 static void ppc405_gpio_writeb (void *opaque, 762 hwaddr addr, uint32_t value) 763 { 764 #ifdef DEBUG_GPIO 765 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 766 value); 767 #endif 768 } 769 770 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr) 771 { 772 #ifdef DEBUG_GPIO 773 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 774 #endif 775 776 return 0; 777 } 778 779 static void ppc405_gpio_writew (void *opaque, 780 hwaddr addr, uint32_t value) 781 { 782 #ifdef DEBUG_GPIO 783 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 784 value); 785 #endif 786 } 787 788 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr) 789 { 790 #ifdef DEBUG_GPIO 791 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 792 #endif 793 794 return 0; 795 } 796 797 static void ppc405_gpio_writel (void *opaque, 798 hwaddr addr, uint32_t value) 799 { 800 #ifdef DEBUG_GPIO 801 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 802 value); 803 #endif 804 } 805 806 static const MemoryRegionOps ppc405_gpio_ops = { 807 .old_mmio = { 808 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, 809 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, 810 }, 811 .endianness = DEVICE_NATIVE_ENDIAN, 812 }; 813 814 static void ppc405_gpio_reset (void *opaque) 815 { 816 } 817 818 static void ppc405_gpio_init(hwaddr base) 819 { 820 ppc405_gpio_t *gpio; 821 822 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 823 #ifdef DEBUG_GPIO 824 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 825 #endif 826 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 827 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 828 qemu_register_reset(&ppc405_gpio_reset, gpio); 829 } 830 831 /*****************************************************************************/ 832 /* On Chip Memory */ 833 enum { 834 OCM0_ISARC = 0x018, 835 OCM0_ISACNTL = 0x019, 836 OCM0_DSARC = 0x01A, 837 OCM0_DSACNTL = 0x01B, 838 }; 839 840 typedef struct ppc405_ocm_t ppc405_ocm_t; 841 struct ppc405_ocm_t { 842 MemoryRegion ram; 843 MemoryRegion isarc_ram; 844 MemoryRegion dsarc_ram; 845 uint32_t isarc; 846 uint32_t isacntl; 847 uint32_t dsarc; 848 uint32_t dsacntl; 849 }; 850 851 static void ocm_update_mappings (ppc405_ocm_t *ocm, 852 uint32_t isarc, uint32_t isacntl, 853 uint32_t dsarc, uint32_t dsacntl) 854 { 855 #ifdef DEBUG_OCM 856 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 857 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 858 " (%08" PRIx32 " %08" PRIx32 ")\n", 859 isarc, isacntl, dsarc, dsacntl, 860 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 861 #endif 862 if (ocm->isarc != isarc || 863 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 864 if (ocm->isacntl & 0x80000000) { 865 /* Unmap previously assigned memory region */ 866 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 867 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 868 } 869 if (isacntl & 0x80000000) { 870 /* Map new instruction memory region */ 871 #ifdef DEBUG_OCM 872 printf("OCM map ISA %08" PRIx32 "\n", isarc); 873 #endif 874 memory_region_add_subregion(get_system_memory(), isarc, 875 &ocm->isarc_ram); 876 } 877 } 878 if (ocm->dsarc != dsarc || 879 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 880 if (ocm->dsacntl & 0x80000000) { 881 /* Beware not to unmap the region we just mapped */ 882 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 883 /* Unmap previously assigned memory region */ 884 #ifdef DEBUG_OCM 885 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 886 #endif 887 memory_region_del_subregion(get_system_memory(), 888 &ocm->dsarc_ram); 889 } 890 } 891 if (dsacntl & 0x80000000) { 892 /* Beware not to remap the region we just mapped */ 893 if (!(isacntl & 0x80000000) || dsarc != isarc) { 894 /* Map new data memory region */ 895 #ifdef DEBUG_OCM 896 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 897 #endif 898 memory_region_add_subregion(get_system_memory(), dsarc, 899 &ocm->dsarc_ram); 900 } 901 } 902 } 903 } 904 905 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 906 { 907 ppc405_ocm_t *ocm; 908 uint32_t ret; 909 910 ocm = opaque; 911 switch (dcrn) { 912 case OCM0_ISARC: 913 ret = ocm->isarc; 914 break; 915 case OCM0_ISACNTL: 916 ret = ocm->isacntl; 917 break; 918 case OCM0_DSARC: 919 ret = ocm->dsarc; 920 break; 921 case OCM0_DSACNTL: 922 ret = ocm->dsacntl; 923 break; 924 default: 925 ret = 0; 926 break; 927 } 928 929 return ret; 930 } 931 932 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 933 { 934 ppc405_ocm_t *ocm; 935 uint32_t isarc, dsarc, isacntl, dsacntl; 936 937 ocm = opaque; 938 isarc = ocm->isarc; 939 dsarc = ocm->dsarc; 940 isacntl = ocm->isacntl; 941 dsacntl = ocm->dsacntl; 942 switch (dcrn) { 943 case OCM0_ISARC: 944 isarc = val & 0xFC000000; 945 break; 946 case OCM0_ISACNTL: 947 isacntl = val & 0xC0000000; 948 break; 949 case OCM0_DSARC: 950 isarc = val & 0xFC000000; 951 break; 952 case OCM0_DSACNTL: 953 isacntl = val & 0xC0000000; 954 break; 955 } 956 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 957 ocm->isarc = isarc; 958 ocm->dsarc = dsarc; 959 ocm->isacntl = isacntl; 960 ocm->dsacntl = dsacntl; 961 } 962 963 static void ocm_reset (void *opaque) 964 { 965 ppc405_ocm_t *ocm; 966 uint32_t isarc, dsarc, isacntl, dsacntl; 967 968 ocm = opaque; 969 isarc = 0x00000000; 970 isacntl = 0x00000000; 971 dsarc = 0x00000000; 972 dsacntl = 0x00000000; 973 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 974 ocm->isarc = isarc; 975 ocm->dsarc = dsarc; 976 ocm->isacntl = isacntl; 977 ocm->dsacntl = dsacntl; 978 } 979 980 static void ppc405_ocm_init(CPUPPCState *env) 981 { 982 ppc405_ocm_t *ocm; 983 984 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 985 /* XXX: Size is 4096 or 0x04000000 */ 986 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096, 987 &error_fatal); 988 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram, 989 0, 4096); 990 qemu_register_reset(&ocm_reset, ocm); 991 ppc_dcr_register(env, OCM0_ISARC, 992 ocm, &dcr_read_ocm, &dcr_write_ocm); 993 ppc_dcr_register(env, OCM0_ISACNTL, 994 ocm, &dcr_read_ocm, &dcr_write_ocm); 995 ppc_dcr_register(env, OCM0_DSARC, 996 ocm, &dcr_read_ocm, &dcr_write_ocm); 997 ppc_dcr_register(env, OCM0_DSACNTL, 998 ocm, &dcr_read_ocm, &dcr_write_ocm); 999 } 1000 1001 /*****************************************************************************/ 1002 /* General purpose timers */ 1003 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 1004 struct ppc4xx_gpt_t { 1005 MemoryRegion iomem; 1006 int64_t tb_offset; 1007 uint32_t tb_freq; 1008 QEMUTimer *timer; 1009 qemu_irq irqs[5]; 1010 uint32_t oe; 1011 uint32_t ol; 1012 uint32_t im; 1013 uint32_t is; 1014 uint32_t ie; 1015 uint32_t comp[5]; 1016 uint32_t mask[5]; 1017 }; 1018 1019 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr) 1020 { 1021 #ifdef DEBUG_GPT 1022 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1023 #endif 1024 /* XXX: generate a bus fault */ 1025 return -1; 1026 } 1027 1028 static void ppc4xx_gpt_writeb (void *opaque, 1029 hwaddr addr, uint32_t value) 1030 { 1031 #ifdef DEBUG_I2C 1032 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1033 value); 1034 #endif 1035 /* XXX: generate a bus fault */ 1036 } 1037 1038 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr) 1039 { 1040 #ifdef DEBUG_GPT 1041 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1042 #endif 1043 /* XXX: generate a bus fault */ 1044 return -1; 1045 } 1046 1047 static void ppc4xx_gpt_writew (void *opaque, 1048 hwaddr addr, uint32_t value) 1049 { 1050 #ifdef DEBUG_I2C 1051 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1052 value); 1053 #endif 1054 /* XXX: generate a bus fault */ 1055 } 1056 1057 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 1058 { 1059 /* XXX: TODO */ 1060 return 0; 1061 } 1062 1063 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 1064 { 1065 /* XXX: TODO */ 1066 } 1067 1068 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 1069 { 1070 uint32_t mask; 1071 int i; 1072 1073 mask = 0x80000000; 1074 for (i = 0; i < 5; i++) { 1075 if (gpt->oe & mask) { 1076 /* Output is enabled */ 1077 if (ppc4xx_gpt_compare(gpt, i)) { 1078 /* Comparison is OK */ 1079 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 1080 } else { 1081 /* Comparison is KO */ 1082 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 1083 } 1084 } 1085 mask = mask >> 1; 1086 } 1087 } 1088 1089 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 1090 { 1091 uint32_t mask; 1092 int i; 1093 1094 mask = 0x00008000; 1095 for (i = 0; i < 5; i++) { 1096 if (gpt->is & gpt->im & mask) 1097 qemu_irq_raise(gpt->irqs[i]); 1098 else 1099 qemu_irq_lower(gpt->irqs[i]); 1100 mask = mask >> 1; 1101 } 1102 } 1103 1104 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 1105 { 1106 /* XXX: TODO */ 1107 } 1108 1109 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) 1110 { 1111 ppc4xx_gpt_t *gpt; 1112 uint32_t ret; 1113 int idx; 1114 1115 #ifdef DEBUG_GPT 1116 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1117 #endif 1118 gpt = opaque; 1119 switch (addr) { 1120 case 0x00: 1121 /* Time base counter */ 1122 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1123 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1124 break; 1125 case 0x10: 1126 /* Output enable */ 1127 ret = gpt->oe; 1128 break; 1129 case 0x14: 1130 /* Output level */ 1131 ret = gpt->ol; 1132 break; 1133 case 0x18: 1134 /* Interrupt mask */ 1135 ret = gpt->im; 1136 break; 1137 case 0x1C: 1138 case 0x20: 1139 /* Interrupt status */ 1140 ret = gpt->is; 1141 break; 1142 case 0x24: 1143 /* Interrupt enable */ 1144 ret = gpt->ie; 1145 break; 1146 case 0x80 ... 0x90: 1147 /* Compare timer */ 1148 idx = (addr - 0x80) >> 2; 1149 ret = gpt->comp[idx]; 1150 break; 1151 case 0xC0 ... 0xD0: 1152 /* Compare mask */ 1153 idx = (addr - 0xC0) >> 2; 1154 ret = gpt->mask[idx]; 1155 break; 1156 default: 1157 ret = -1; 1158 break; 1159 } 1160 1161 return ret; 1162 } 1163 1164 static void ppc4xx_gpt_writel (void *opaque, 1165 hwaddr addr, uint32_t value) 1166 { 1167 ppc4xx_gpt_t *gpt; 1168 int idx; 1169 1170 #ifdef DEBUG_I2C 1171 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1172 value); 1173 #endif 1174 gpt = opaque; 1175 switch (addr) { 1176 case 0x00: 1177 /* Time base counter */ 1178 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1179 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1180 ppc4xx_gpt_compute_timer(gpt); 1181 break; 1182 case 0x10: 1183 /* Output enable */ 1184 gpt->oe = value & 0xF8000000; 1185 ppc4xx_gpt_set_outputs(gpt); 1186 break; 1187 case 0x14: 1188 /* Output level */ 1189 gpt->ol = value & 0xF8000000; 1190 ppc4xx_gpt_set_outputs(gpt); 1191 break; 1192 case 0x18: 1193 /* Interrupt mask */ 1194 gpt->im = value & 0x0000F800; 1195 break; 1196 case 0x1C: 1197 /* Interrupt status set */ 1198 gpt->is |= value & 0x0000F800; 1199 ppc4xx_gpt_set_irqs(gpt); 1200 break; 1201 case 0x20: 1202 /* Interrupt status clear */ 1203 gpt->is &= ~(value & 0x0000F800); 1204 ppc4xx_gpt_set_irqs(gpt); 1205 break; 1206 case 0x24: 1207 /* Interrupt enable */ 1208 gpt->ie = value & 0x0000F800; 1209 ppc4xx_gpt_set_irqs(gpt); 1210 break; 1211 case 0x80 ... 0x90: 1212 /* Compare timer */ 1213 idx = (addr - 0x80) >> 2; 1214 gpt->comp[idx] = value & 0xF8000000; 1215 ppc4xx_gpt_compute_timer(gpt); 1216 break; 1217 case 0xC0 ... 0xD0: 1218 /* Compare mask */ 1219 idx = (addr - 0xC0) >> 2; 1220 gpt->mask[idx] = value & 0xF8000000; 1221 ppc4xx_gpt_compute_timer(gpt); 1222 break; 1223 } 1224 } 1225 1226 static const MemoryRegionOps gpt_ops = { 1227 .old_mmio = { 1228 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, 1229 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, 1230 }, 1231 .endianness = DEVICE_NATIVE_ENDIAN, 1232 }; 1233 1234 static void ppc4xx_gpt_cb (void *opaque) 1235 { 1236 ppc4xx_gpt_t *gpt; 1237 1238 gpt = opaque; 1239 ppc4xx_gpt_set_irqs(gpt); 1240 ppc4xx_gpt_set_outputs(gpt); 1241 ppc4xx_gpt_compute_timer(gpt); 1242 } 1243 1244 static void ppc4xx_gpt_reset (void *opaque) 1245 { 1246 ppc4xx_gpt_t *gpt; 1247 int i; 1248 1249 gpt = opaque; 1250 timer_del(gpt->timer); 1251 gpt->oe = 0x00000000; 1252 gpt->ol = 0x00000000; 1253 gpt->im = 0x00000000; 1254 gpt->is = 0x00000000; 1255 gpt->ie = 0x00000000; 1256 for (i = 0; i < 5; i++) { 1257 gpt->comp[i] = 0x00000000; 1258 gpt->mask[i] = 0x00000000; 1259 } 1260 } 1261 1262 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1263 { 1264 ppc4xx_gpt_t *gpt; 1265 int i; 1266 1267 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1268 for (i = 0; i < 5; i++) { 1269 gpt->irqs[i] = irqs[i]; 1270 } 1271 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1272 #ifdef DEBUG_GPT 1273 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1274 #endif 1275 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1276 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1277 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1278 } 1279 1280 /*****************************************************************************/ 1281 /* SPR */ 1282 void ppc40x_core_reset(PowerPCCPU *cpu) 1283 { 1284 CPUPPCState *env = &cpu->env; 1285 target_ulong dbsr; 1286 1287 printf("Reset PowerPC core\n"); 1288 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 1289 dbsr = env->spr[SPR_40x_DBSR]; 1290 dbsr &= ~0x00000300; 1291 dbsr |= 0x00000100; 1292 env->spr[SPR_40x_DBSR] = dbsr; 1293 } 1294 1295 void ppc40x_chip_reset(PowerPCCPU *cpu) 1296 { 1297 CPUPPCState *env = &cpu->env; 1298 target_ulong dbsr; 1299 1300 printf("Reset PowerPC chip\n"); 1301 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 1302 /* XXX: TODO reset all internal peripherals */ 1303 dbsr = env->spr[SPR_40x_DBSR]; 1304 dbsr &= ~0x00000300; 1305 dbsr |= 0x00000200; 1306 env->spr[SPR_40x_DBSR] = dbsr; 1307 } 1308 1309 void ppc40x_system_reset(PowerPCCPU *cpu) 1310 { 1311 printf("Reset PowerPC system\n"); 1312 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1313 } 1314 1315 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) 1316 { 1317 PowerPCCPU *cpu = ppc_env_get_cpu(env); 1318 1319 switch ((val >> 28) & 0x3) { 1320 case 0x0: 1321 /* No action */ 1322 break; 1323 case 0x1: 1324 /* Core reset */ 1325 ppc40x_core_reset(cpu); 1326 break; 1327 case 0x2: 1328 /* Chip reset */ 1329 ppc40x_chip_reset(cpu); 1330 break; 1331 case 0x3: 1332 /* System reset */ 1333 ppc40x_system_reset(cpu); 1334 break; 1335 } 1336 } 1337 1338 /*****************************************************************************/ 1339 /* PowerPC 405CR */ 1340 enum { 1341 PPC405CR_CPC0_PLLMR = 0x0B0, 1342 PPC405CR_CPC0_CR0 = 0x0B1, 1343 PPC405CR_CPC0_CR1 = 0x0B2, 1344 PPC405CR_CPC0_PSR = 0x0B4, 1345 PPC405CR_CPC0_JTAGID = 0x0B5, 1346 PPC405CR_CPC0_ER = 0x0B9, 1347 PPC405CR_CPC0_FR = 0x0BA, 1348 PPC405CR_CPC0_SR = 0x0BB, 1349 }; 1350 1351 enum { 1352 PPC405CR_CPU_CLK = 0, 1353 PPC405CR_TMR_CLK = 1, 1354 PPC405CR_PLB_CLK = 2, 1355 PPC405CR_SDRAM_CLK = 3, 1356 PPC405CR_OPB_CLK = 4, 1357 PPC405CR_EXT_CLK = 5, 1358 PPC405CR_UART_CLK = 6, 1359 PPC405CR_CLK_NB = 7, 1360 }; 1361 1362 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; 1363 struct ppc405cr_cpc_t { 1364 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1365 uint32_t sysclk; 1366 uint32_t psr; 1367 uint32_t cr0; 1368 uint32_t cr1; 1369 uint32_t jtagid; 1370 uint32_t pllmr; 1371 uint32_t er; 1372 uint32_t fr; 1373 }; 1374 1375 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) 1376 { 1377 uint64_t VCO_out, PLL_out; 1378 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; 1379 int M, D0, D1, D2; 1380 1381 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ 1382 if (cpc->pllmr & 0x80000000) { 1383 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ 1384 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ 1385 M = D0 * D1 * D2; 1386 VCO_out = (uint64_t)cpc->sysclk * M; 1387 if (VCO_out < 400000000 || VCO_out > 800000000) { 1388 /* PLL cannot lock */ 1389 cpc->pllmr &= ~0x80000000; 1390 goto bypass_pll; 1391 } 1392 PLL_out = VCO_out / D2; 1393 } else { 1394 /* Bypass PLL */ 1395 bypass_pll: 1396 M = D0; 1397 PLL_out = (uint64_t)cpc->sysclk * M; 1398 } 1399 CPU_clk = PLL_out; 1400 if (cpc->cr1 & 0x00800000) 1401 TMR_clk = cpc->sysclk; /* Should have a separate clock */ 1402 else 1403 TMR_clk = CPU_clk; 1404 PLB_clk = CPU_clk / D0; 1405 SDRAM_clk = PLB_clk; 1406 D0 = ((cpc->pllmr >> 10) & 0x3) + 1; 1407 OPB_clk = PLB_clk / D0; 1408 D0 = ((cpc->pllmr >> 24) & 0x3) + 2; 1409 EXT_clk = PLB_clk / D0; 1410 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; 1411 UART_clk = CPU_clk / D0; 1412 /* Setup CPU clocks */ 1413 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); 1414 /* Setup time-base clock */ 1415 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); 1416 /* Setup PLB clock */ 1417 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); 1418 /* Setup SDRAM clock */ 1419 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); 1420 /* Setup OPB clock */ 1421 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); 1422 /* Setup external clock */ 1423 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); 1424 /* Setup UART clock */ 1425 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); 1426 } 1427 1428 static uint32_t dcr_read_crcpc (void *opaque, int dcrn) 1429 { 1430 ppc405cr_cpc_t *cpc; 1431 uint32_t ret; 1432 1433 cpc = opaque; 1434 switch (dcrn) { 1435 case PPC405CR_CPC0_PLLMR: 1436 ret = cpc->pllmr; 1437 break; 1438 case PPC405CR_CPC0_CR0: 1439 ret = cpc->cr0; 1440 break; 1441 case PPC405CR_CPC0_CR1: 1442 ret = cpc->cr1; 1443 break; 1444 case PPC405CR_CPC0_PSR: 1445 ret = cpc->psr; 1446 break; 1447 case PPC405CR_CPC0_JTAGID: 1448 ret = cpc->jtagid; 1449 break; 1450 case PPC405CR_CPC0_ER: 1451 ret = cpc->er; 1452 break; 1453 case PPC405CR_CPC0_FR: 1454 ret = cpc->fr; 1455 break; 1456 case PPC405CR_CPC0_SR: 1457 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; 1458 break; 1459 default: 1460 /* Avoid gcc warning */ 1461 ret = 0; 1462 break; 1463 } 1464 1465 return ret; 1466 } 1467 1468 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) 1469 { 1470 ppc405cr_cpc_t *cpc; 1471 1472 cpc = opaque; 1473 switch (dcrn) { 1474 case PPC405CR_CPC0_PLLMR: 1475 cpc->pllmr = val & 0xFFF77C3F; 1476 break; 1477 case PPC405CR_CPC0_CR0: 1478 cpc->cr0 = val & 0x0FFFFFFE; 1479 break; 1480 case PPC405CR_CPC0_CR1: 1481 cpc->cr1 = val & 0x00800000; 1482 break; 1483 case PPC405CR_CPC0_PSR: 1484 /* Read-only */ 1485 break; 1486 case PPC405CR_CPC0_JTAGID: 1487 /* Read-only */ 1488 break; 1489 case PPC405CR_CPC0_ER: 1490 cpc->er = val & 0xBFFC0000; 1491 break; 1492 case PPC405CR_CPC0_FR: 1493 cpc->fr = val & 0xBFFC0000; 1494 break; 1495 case PPC405CR_CPC0_SR: 1496 /* Read-only */ 1497 break; 1498 } 1499 } 1500 1501 static void ppc405cr_cpc_reset (void *opaque) 1502 { 1503 ppc405cr_cpc_t *cpc; 1504 int D; 1505 1506 cpc = opaque; 1507 /* Compute PLLMR value from PSR settings */ 1508 cpc->pllmr = 0x80000000; 1509 /* PFWD */ 1510 switch ((cpc->psr >> 30) & 3) { 1511 case 0: 1512 /* Bypass */ 1513 cpc->pllmr &= ~0x80000000; 1514 break; 1515 case 1: 1516 /* Divide by 3 */ 1517 cpc->pllmr |= 5 << 16; 1518 break; 1519 case 2: 1520 /* Divide by 4 */ 1521 cpc->pllmr |= 4 << 16; 1522 break; 1523 case 3: 1524 /* Divide by 6 */ 1525 cpc->pllmr |= 2 << 16; 1526 break; 1527 } 1528 /* PFBD */ 1529 D = (cpc->psr >> 28) & 3; 1530 cpc->pllmr |= (D + 1) << 20; 1531 /* PT */ 1532 D = (cpc->psr >> 25) & 7; 1533 switch (D) { 1534 case 0x2: 1535 cpc->pllmr |= 0x13; 1536 break; 1537 case 0x4: 1538 cpc->pllmr |= 0x15; 1539 break; 1540 case 0x5: 1541 cpc->pllmr |= 0x16; 1542 break; 1543 default: 1544 break; 1545 } 1546 /* PDC */ 1547 D = (cpc->psr >> 23) & 3; 1548 cpc->pllmr |= D << 26; 1549 /* ODP */ 1550 D = (cpc->psr >> 21) & 3; 1551 cpc->pllmr |= D << 10; 1552 /* EBPD */ 1553 D = (cpc->psr >> 17) & 3; 1554 cpc->pllmr |= D << 24; 1555 cpc->cr0 = 0x0000003C; 1556 cpc->cr1 = 0x2B0D8800; 1557 cpc->er = 0x00000000; 1558 cpc->fr = 0x00000000; 1559 ppc405cr_clk_setup(cpc); 1560 } 1561 1562 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) 1563 { 1564 int D; 1565 1566 /* XXX: this should be read from IO pins */ 1567 cpc->psr = 0x00000000; /* 8 bits ROM */ 1568 /* PFWD */ 1569 D = 0x2; /* Divide by 4 */ 1570 cpc->psr |= D << 30; 1571 /* PFBD */ 1572 D = 0x1; /* Divide by 2 */ 1573 cpc->psr |= D << 28; 1574 /* PDC */ 1575 D = 0x1; /* Divide by 2 */ 1576 cpc->psr |= D << 23; 1577 /* PT */ 1578 D = 0x5; /* M = 16 */ 1579 cpc->psr |= D << 25; 1580 /* ODP */ 1581 D = 0x1; /* Divide by 2 */ 1582 cpc->psr |= D << 21; 1583 /* EBDP */ 1584 D = 0x2; /* Divide by 4 */ 1585 cpc->psr |= D << 17; 1586 } 1587 1588 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], 1589 uint32_t sysclk) 1590 { 1591 ppc405cr_cpc_t *cpc; 1592 1593 cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); 1594 memcpy(cpc->clk_setup, clk_setup, 1595 PPC405CR_CLK_NB * sizeof(clk_setup_t)); 1596 cpc->sysclk = sysclk; 1597 cpc->jtagid = 0x42051049; 1598 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, 1599 &dcr_read_crcpc, &dcr_write_crcpc); 1600 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, 1601 &dcr_read_crcpc, &dcr_write_crcpc); 1602 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, 1603 &dcr_read_crcpc, &dcr_write_crcpc); 1604 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, 1605 &dcr_read_crcpc, &dcr_write_crcpc); 1606 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, 1607 &dcr_read_crcpc, &dcr_write_crcpc); 1608 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, 1609 &dcr_read_crcpc, &dcr_write_crcpc); 1610 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, 1611 &dcr_read_crcpc, &dcr_write_crcpc); 1612 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, 1613 &dcr_read_crcpc, &dcr_write_crcpc); 1614 ppc405cr_clk_init(cpc); 1615 qemu_register_reset(ppc405cr_cpc_reset, cpc); 1616 } 1617 1618 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, 1619 MemoryRegion ram_memories[4], 1620 hwaddr ram_bases[4], 1621 hwaddr ram_sizes[4], 1622 uint32_t sysclk, qemu_irq **picp, 1623 int do_init) 1624 { 1625 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1626 qemu_irq dma_irqs[4]; 1627 PowerPCCPU *cpu; 1628 CPUPPCState *env; 1629 qemu_irq *pic, *irqs; 1630 1631 memset(clk_setup, 0, sizeof(clk_setup)); 1632 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), 1633 &clk_setup[PPC405CR_CPU_CLK], 1634 &clk_setup[PPC405CR_TMR_CLK], sysclk); 1635 env = &cpu->env; 1636 /* Memory mapped devices registers */ 1637 /* PLB arbitrer */ 1638 ppc4xx_plb_init(env); 1639 /* PLB to OPB bridge */ 1640 ppc4xx_pob_init(env); 1641 /* OBP arbitrer */ 1642 ppc4xx_opba_init(0xef600600); 1643 /* Universal interrupt controller */ 1644 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); 1645 irqs[PPCUIC_OUTPUT_INT] = 1646 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 1647 irqs[PPCUIC_OUTPUT_CINT] = 1648 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 1649 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 1650 *picp = pic; 1651 /* SDRAM controller */ 1652 ppc4xx_sdram_init(env, pic[14], 1, ram_memories, 1653 ram_bases, ram_sizes, do_init); 1654 /* External bus controller */ 1655 ppc405_ebc_init(env); 1656 /* DMA controller */ 1657 dma_irqs[0] = pic[26]; 1658 dma_irqs[1] = pic[25]; 1659 dma_irqs[2] = pic[24]; 1660 dma_irqs[3] = pic[23]; 1661 ppc405_dma_init(env, dma_irqs); 1662 /* Serial ports */ 1663 if (serial_hd(0) != NULL) { 1664 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 1665 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1666 DEVICE_BIG_ENDIAN); 1667 } 1668 if (serial_hd(1) != NULL) { 1669 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 1670 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1671 DEVICE_BIG_ENDIAN); 1672 } 1673 /* IIC controller */ 1674 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 1675 /* GPIO */ 1676 ppc405_gpio_init(0xef600700); 1677 /* CPU control */ 1678 ppc405cr_cpc_init(env, clk_setup, sysclk); 1679 1680 return env; 1681 } 1682 1683 /*****************************************************************************/ 1684 /* PowerPC 405EP */ 1685 /* CPU control */ 1686 enum { 1687 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1688 PPC405EP_CPC0_BOOT = 0x0F1, 1689 PPC405EP_CPC0_EPCTL = 0x0F3, 1690 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1691 PPC405EP_CPC0_UCR = 0x0F5, 1692 PPC405EP_CPC0_SRR = 0x0F6, 1693 PPC405EP_CPC0_JTAGID = 0x0F7, 1694 PPC405EP_CPC0_PCI = 0x0F9, 1695 #if 0 1696 PPC405EP_CPC0_ER = xxx, 1697 PPC405EP_CPC0_FR = xxx, 1698 PPC405EP_CPC0_SR = xxx, 1699 #endif 1700 }; 1701 1702 enum { 1703 PPC405EP_CPU_CLK = 0, 1704 PPC405EP_PLB_CLK = 1, 1705 PPC405EP_OPB_CLK = 2, 1706 PPC405EP_EBC_CLK = 3, 1707 PPC405EP_MAL_CLK = 4, 1708 PPC405EP_PCI_CLK = 5, 1709 PPC405EP_UART0_CLK = 6, 1710 PPC405EP_UART1_CLK = 7, 1711 PPC405EP_CLK_NB = 8, 1712 }; 1713 1714 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1715 struct ppc405ep_cpc_t { 1716 uint32_t sysclk; 1717 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1718 uint32_t boot; 1719 uint32_t epctl; 1720 uint32_t pllmr[2]; 1721 uint32_t ucr; 1722 uint32_t srr; 1723 uint32_t jtagid; 1724 uint32_t pci; 1725 /* Clock and power management */ 1726 uint32_t er; 1727 uint32_t fr; 1728 uint32_t sr; 1729 }; 1730 1731 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1732 { 1733 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1734 uint32_t UART0_clk, UART1_clk; 1735 uint64_t VCO_out, PLL_out; 1736 int M, D; 1737 1738 VCO_out = 0; 1739 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1740 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1741 #ifdef DEBUG_CLOCKS_LL 1742 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 1743 #endif 1744 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1745 #ifdef DEBUG_CLOCKS_LL 1746 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 1747 #endif 1748 VCO_out = (uint64_t)cpc->sysclk * M * D; 1749 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1750 /* Error - unlock the PLL */ 1751 printf("VCO out of range %" PRIu64 "\n", VCO_out); 1752 #if 0 1753 cpc->pllmr[1] &= ~0x80000000; 1754 goto pll_bypass; 1755 #endif 1756 } 1757 PLL_out = VCO_out / D; 1758 /* Pretend the PLL is locked */ 1759 cpc->boot |= 0x00000001; 1760 } else { 1761 #if 0 1762 pll_bypass: 1763 #endif 1764 PLL_out = cpc->sysclk; 1765 if (cpc->pllmr[1] & 0x40000000) { 1766 /* Pretend the PLL is not locked */ 1767 cpc->boot &= ~0x00000001; 1768 } 1769 } 1770 /* Now, compute all other clocks */ 1771 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1772 #ifdef DEBUG_CLOCKS_LL 1773 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 1774 #endif 1775 CPU_clk = PLL_out / D; 1776 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1777 #ifdef DEBUG_CLOCKS_LL 1778 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 1779 #endif 1780 PLB_clk = CPU_clk / D; 1781 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1782 #ifdef DEBUG_CLOCKS_LL 1783 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 1784 #endif 1785 OPB_clk = PLB_clk / D; 1786 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1787 #ifdef DEBUG_CLOCKS_LL 1788 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 1789 #endif 1790 EBC_clk = PLB_clk / D; 1791 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1792 #ifdef DEBUG_CLOCKS_LL 1793 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 1794 #endif 1795 MAL_clk = PLB_clk / D; 1796 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1797 #ifdef DEBUG_CLOCKS_LL 1798 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 1799 #endif 1800 PCI_clk = PLB_clk / D; 1801 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1802 #ifdef DEBUG_CLOCKS_LL 1803 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 1804 #endif 1805 UART0_clk = PLL_out / D; 1806 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1807 #ifdef DEBUG_CLOCKS_LL 1808 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 1809 #endif 1810 UART1_clk = PLL_out / D; 1811 #ifdef DEBUG_CLOCKS 1812 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1813 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 1814 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1815 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1816 " UART1 %" PRIu32 "\n", 1817 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1818 UART0_clk, UART1_clk); 1819 #endif 1820 /* Setup CPU clocks */ 1821 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1822 /* Setup PLB clock */ 1823 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1824 /* Setup OPB clock */ 1825 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1826 /* Setup external clock */ 1827 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1828 /* Setup MAL clock */ 1829 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1830 /* Setup PCI clock */ 1831 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1832 /* Setup UART0 clock */ 1833 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1834 /* Setup UART1 clock */ 1835 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1836 } 1837 1838 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1839 { 1840 ppc405ep_cpc_t *cpc; 1841 uint32_t ret; 1842 1843 cpc = opaque; 1844 switch (dcrn) { 1845 case PPC405EP_CPC0_BOOT: 1846 ret = cpc->boot; 1847 break; 1848 case PPC405EP_CPC0_EPCTL: 1849 ret = cpc->epctl; 1850 break; 1851 case PPC405EP_CPC0_PLLMR0: 1852 ret = cpc->pllmr[0]; 1853 break; 1854 case PPC405EP_CPC0_PLLMR1: 1855 ret = cpc->pllmr[1]; 1856 break; 1857 case PPC405EP_CPC0_UCR: 1858 ret = cpc->ucr; 1859 break; 1860 case PPC405EP_CPC0_SRR: 1861 ret = cpc->srr; 1862 break; 1863 case PPC405EP_CPC0_JTAGID: 1864 ret = cpc->jtagid; 1865 break; 1866 case PPC405EP_CPC0_PCI: 1867 ret = cpc->pci; 1868 break; 1869 default: 1870 /* Avoid gcc warning */ 1871 ret = 0; 1872 break; 1873 } 1874 1875 return ret; 1876 } 1877 1878 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1879 { 1880 ppc405ep_cpc_t *cpc; 1881 1882 cpc = opaque; 1883 switch (dcrn) { 1884 case PPC405EP_CPC0_BOOT: 1885 /* Read-only register */ 1886 break; 1887 case PPC405EP_CPC0_EPCTL: 1888 /* Don't care for now */ 1889 cpc->epctl = val & 0xC00000F3; 1890 break; 1891 case PPC405EP_CPC0_PLLMR0: 1892 cpc->pllmr[0] = val & 0x00633333; 1893 ppc405ep_compute_clocks(cpc); 1894 break; 1895 case PPC405EP_CPC0_PLLMR1: 1896 cpc->pllmr[1] = val & 0xC0F73FFF; 1897 ppc405ep_compute_clocks(cpc); 1898 break; 1899 case PPC405EP_CPC0_UCR: 1900 /* UART control - don't care for now */ 1901 cpc->ucr = val & 0x003F7F7F; 1902 break; 1903 case PPC405EP_CPC0_SRR: 1904 cpc->srr = val; 1905 break; 1906 case PPC405EP_CPC0_JTAGID: 1907 /* Read-only */ 1908 break; 1909 case PPC405EP_CPC0_PCI: 1910 cpc->pci = val; 1911 break; 1912 } 1913 } 1914 1915 static void ppc405ep_cpc_reset (void *opaque) 1916 { 1917 ppc405ep_cpc_t *cpc = opaque; 1918 1919 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1920 cpc->epctl = 0x00000000; 1921 cpc->pllmr[0] = 0x00011010; 1922 cpc->pllmr[1] = 0x40000000; 1923 cpc->ucr = 0x00000000; 1924 cpc->srr = 0x00040000; 1925 cpc->pci = 0x00000000; 1926 cpc->er = 0x00000000; 1927 cpc->fr = 0x00000000; 1928 cpc->sr = 0x00000000; 1929 ppc405ep_compute_clocks(cpc); 1930 } 1931 1932 /* XXX: sysclk should be between 25 and 100 MHz */ 1933 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1934 uint32_t sysclk) 1935 { 1936 ppc405ep_cpc_t *cpc; 1937 1938 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1939 memcpy(cpc->clk_setup, clk_setup, 1940 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1941 cpc->jtagid = 0x20267049; 1942 cpc->sysclk = sysclk; 1943 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1944 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1945 &dcr_read_epcpc, &dcr_write_epcpc); 1946 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1947 &dcr_read_epcpc, &dcr_write_epcpc); 1948 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1949 &dcr_read_epcpc, &dcr_write_epcpc); 1950 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1951 &dcr_read_epcpc, &dcr_write_epcpc); 1952 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1953 &dcr_read_epcpc, &dcr_write_epcpc); 1954 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1955 &dcr_read_epcpc, &dcr_write_epcpc); 1956 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1957 &dcr_read_epcpc, &dcr_write_epcpc); 1958 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1959 &dcr_read_epcpc, &dcr_write_epcpc); 1960 #if 0 1961 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1962 &dcr_read_epcpc, &dcr_write_epcpc); 1963 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1964 &dcr_read_epcpc, &dcr_write_epcpc); 1965 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1966 &dcr_read_epcpc, &dcr_write_epcpc); 1967 #endif 1968 } 1969 1970 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1971 MemoryRegion ram_memories[2], 1972 hwaddr ram_bases[2], 1973 hwaddr ram_sizes[2], 1974 uint32_t sysclk, qemu_irq **picp, 1975 int do_init) 1976 { 1977 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1978 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1979 PowerPCCPU *cpu; 1980 CPUPPCState *env; 1981 qemu_irq *pic, *irqs; 1982 1983 memset(clk_setup, 0, sizeof(clk_setup)); 1984 /* init CPUs */ 1985 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1986 &clk_setup[PPC405EP_CPU_CLK], 1987 &tlb_clk_setup, sysclk); 1988 env = &cpu->env; 1989 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1990 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1991 /* Internal devices init */ 1992 /* Memory mapped devices registers */ 1993 /* PLB arbitrer */ 1994 ppc4xx_plb_init(env); 1995 /* PLB to OPB bridge */ 1996 ppc4xx_pob_init(env); 1997 /* OBP arbitrer */ 1998 ppc4xx_opba_init(0xef600600); 1999 /* Initialize timers */ 2000 ppc_booke_timers_init(cpu, sysclk, 0); 2001 /* Universal interrupt controller */ 2002 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); 2003 irqs[PPCUIC_OUTPUT_INT] = 2004 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 2005 irqs[PPCUIC_OUTPUT_CINT] = 2006 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 2007 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 2008 *picp = pic; 2009 /* SDRAM controller */ 2010 /* XXX 405EP has no ECC interrupt */ 2011 ppc4xx_sdram_init(env, pic[17], 2, ram_memories, 2012 ram_bases, ram_sizes, do_init); 2013 /* External bus controller */ 2014 ppc405_ebc_init(env); 2015 /* DMA controller */ 2016 dma_irqs[0] = pic[5]; 2017 dma_irqs[1] = pic[6]; 2018 dma_irqs[2] = pic[7]; 2019 dma_irqs[3] = pic[8]; 2020 ppc405_dma_init(env, dma_irqs); 2021 /* IIC controller */ 2022 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 2023 /* GPIO */ 2024 ppc405_gpio_init(0xef600700); 2025 /* Serial ports */ 2026 if (serial_hd(0) != NULL) { 2027 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 2028 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 2029 DEVICE_BIG_ENDIAN); 2030 } 2031 if (serial_hd(1) != NULL) { 2032 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 2033 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 2034 DEVICE_BIG_ENDIAN); 2035 } 2036 /* OCM */ 2037 ppc405_ocm_init(env); 2038 /* GPT */ 2039 gpt_irqs[0] = pic[19]; 2040 gpt_irqs[1] = pic[20]; 2041 gpt_irqs[2] = pic[21]; 2042 gpt_irqs[3] = pic[22]; 2043 gpt_irqs[4] = pic[23]; 2044 ppc4xx_gpt_init(0xef600000, gpt_irqs); 2045 /* PCI */ 2046 /* Uses pic[3], pic[16], pic[18] */ 2047 /* MAL */ 2048 mal_irqs[0] = pic[11]; 2049 mal_irqs[1] = pic[12]; 2050 mal_irqs[2] = pic[13]; 2051 mal_irqs[3] = pic[14]; 2052 ppc4xx_mal_init(env, 4, 2, mal_irqs); 2053 /* Ethernet */ 2054 /* Uses pic[9], pic[15], pic[17] */ 2055 /* CPU control */ 2056 ppc405ep_cpc_init(env, clk_setup, sysclk); 2057 2058 return env; 2059 } 2060