1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "cpu.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/i2c/ppc4xx_i2c.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "ppc405.h" 35 #include "hw/char/serial.h" 36 #include "qemu/timer.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/sysemu.h" 39 #include "exec/address-spaces.h" 40 #include "hw/intc/ppc-uic.h" 41 #include "hw/qdev-properties.h" 42 #include "qapi/error.h" 43 #include "trace.h" 44 45 /*****************************************************************************/ 46 /* Shared peripherals */ 47 48 /*****************************************************************************/ 49 /* PLB to OPB bridge */ 50 enum { 51 POB0_BESR0 = 0x0A0, 52 POB0_BESR1 = 0x0A2, 53 POB0_BEAR = 0x0A4, 54 }; 55 56 static uint32_t dcr_read_pob(void *opaque, int dcrn) 57 { 58 Ppc405PobState *pob = opaque; 59 uint32_t ret; 60 61 switch (dcrn) { 62 case POB0_BEAR: 63 ret = pob->bear; 64 break; 65 case POB0_BESR0: 66 ret = pob->besr0; 67 break; 68 case POB0_BESR1: 69 ret = pob->besr1; 70 break; 71 default: 72 /* Avoid gcc warning */ 73 ret = 0; 74 break; 75 } 76 77 return ret; 78 } 79 80 static void dcr_write_pob(void *opaque, int dcrn, uint32_t val) 81 { 82 Ppc405PobState *pob = opaque; 83 84 switch (dcrn) { 85 case POB0_BEAR: 86 /* Read only */ 87 break; 88 case POB0_BESR0: 89 /* Write-clear */ 90 pob->besr0 &= ~val; 91 break; 92 case POB0_BESR1: 93 /* Write-clear */ 94 pob->besr1 &= ~val; 95 break; 96 } 97 } 98 99 static void ppc405_pob_reset(DeviceState *dev) 100 { 101 Ppc405PobState *pob = PPC405_POB(dev); 102 103 /* No error */ 104 pob->bear = 0x00000000; 105 pob->besr0 = 0x0000000; 106 pob->besr1 = 0x0000000; 107 } 108 109 static void ppc405_pob_realize(DeviceState *dev, Error **errp) 110 { 111 Ppc405PobState *pob = PPC405_POB(dev); 112 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 113 114 ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 115 ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 116 ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 117 } 118 119 static void ppc405_pob_class_init(ObjectClass *oc, void *data) 120 { 121 DeviceClass *dc = DEVICE_CLASS(oc); 122 123 dc->realize = ppc405_pob_realize; 124 dc->reset = ppc405_pob_reset; 125 /* Reason: only works as function of a ppc4xx SoC */ 126 dc->user_creatable = false; 127 } 128 129 /*****************************************************************************/ 130 /* OPB arbitrer */ 131 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 132 { 133 Ppc405OpbaState *opba = opaque; 134 uint32_t ret; 135 136 switch (addr) { 137 case 0x00: 138 ret = opba->cr; 139 break; 140 case 0x01: 141 ret = opba->pr; 142 break; 143 default: 144 ret = 0x00; 145 break; 146 } 147 148 trace_opba_readb(addr, ret); 149 return ret; 150 } 151 152 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 153 unsigned size) 154 { 155 Ppc405OpbaState *opba = opaque; 156 157 trace_opba_writeb(addr, value); 158 159 switch (addr) { 160 case 0x00: 161 opba->cr = value & 0xF8; 162 break; 163 case 0x01: 164 opba->pr = value & 0xFF; 165 break; 166 default: 167 break; 168 } 169 } 170 static const MemoryRegionOps opba_ops = { 171 .read = opba_readb, 172 .write = opba_writeb, 173 .impl.min_access_size = 1, 174 .impl.max_access_size = 1, 175 .valid.min_access_size = 1, 176 .valid.max_access_size = 4, 177 .endianness = DEVICE_BIG_ENDIAN, 178 }; 179 180 static void ppc405_opba_reset(DeviceState *dev) 181 { 182 Ppc405OpbaState *opba = PPC405_OPBA(dev); 183 184 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 185 opba->pr = 0x11; 186 } 187 188 static void ppc405_opba_realize(DeviceState *dev, Error **errp) 189 { 190 Ppc405OpbaState *s = PPC405_OPBA(dev); 191 192 memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2); 193 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); 194 } 195 196 static void ppc405_opba_class_init(ObjectClass *oc, void *data) 197 { 198 DeviceClass *dc = DEVICE_CLASS(oc); 199 200 dc->realize = ppc405_opba_realize; 201 dc->reset = ppc405_opba_reset; 202 /* Reason: only works as function of a ppc4xx SoC */ 203 dc->user_creatable = false; 204 } 205 206 /*****************************************************************************/ 207 /* Code decompression controller */ 208 /* XXX: TODO */ 209 210 /*****************************************************************************/ 211 /* DMA controller */ 212 enum { 213 DMA0_CR0 = 0x100, 214 DMA0_CT0 = 0x101, 215 DMA0_DA0 = 0x102, 216 DMA0_SA0 = 0x103, 217 DMA0_SG0 = 0x104, 218 DMA0_CR1 = 0x108, 219 DMA0_CT1 = 0x109, 220 DMA0_DA1 = 0x10A, 221 DMA0_SA1 = 0x10B, 222 DMA0_SG1 = 0x10C, 223 DMA0_CR2 = 0x110, 224 DMA0_CT2 = 0x111, 225 DMA0_DA2 = 0x112, 226 DMA0_SA2 = 0x113, 227 DMA0_SG2 = 0x114, 228 DMA0_CR3 = 0x118, 229 DMA0_CT3 = 0x119, 230 DMA0_DA3 = 0x11A, 231 DMA0_SA3 = 0x11B, 232 DMA0_SG3 = 0x11C, 233 DMA0_SR = 0x120, 234 DMA0_SGC = 0x123, 235 DMA0_SLP = 0x125, 236 DMA0_POL = 0x126, 237 }; 238 239 static uint32_t dcr_read_dma(void *opaque, int dcrn) 240 { 241 return 0; 242 } 243 244 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) 245 { 246 } 247 248 static void ppc405_dma_reset(DeviceState *dev) 249 { 250 Ppc405DmaState *dma = PPC405_DMA(dev); 251 int i; 252 253 for (i = 0; i < 4; i++) { 254 dma->cr[i] = 0x00000000; 255 dma->ct[i] = 0x00000000; 256 dma->da[i] = 0x00000000; 257 dma->sa[i] = 0x00000000; 258 dma->sg[i] = 0x00000000; 259 } 260 dma->sr = 0x00000000; 261 dma->sgc = 0x00000000; 262 dma->slp = 0x7C000000; 263 dma->pol = 0x00000000; 264 } 265 266 static void ppc405_dma_realize(DeviceState *dev, Error **errp) 267 { 268 Ppc405DmaState *dma = PPC405_DMA(dev); 269 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 270 int i; 271 272 for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) { 273 sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]); 274 } 275 276 ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma); 277 ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma); 278 ppc4xx_dcr_register(dcr, DMA0_DA0, dma, &dcr_read_dma, &dcr_write_dma); 279 ppc4xx_dcr_register(dcr, DMA0_SA0, dma, &dcr_read_dma, &dcr_write_dma); 280 ppc4xx_dcr_register(dcr, DMA0_SG0, dma, &dcr_read_dma, &dcr_write_dma); 281 ppc4xx_dcr_register(dcr, DMA0_CR1, dma, &dcr_read_dma, &dcr_write_dma); 282 ppc4xx_dcr_register(dcr, DMA0_CT1, dma, &dcr_read_dma, &dcr_write_dma); 283 ppc4xx_dcr_register(dcr, DMA0_DA1, dma, &dcr_read_dma, &dcr_write_dma); 284 ppc4xx_dcr_register(dcr, DMA0_SA1, dma, &dcr_read_dma, &dcr_write_dma); 285 ppc4xx_dcr_register(dcr, DMA0_SG1, dma, &dcr_read_dma, &dcr_write_dma); 286 ppc4xx_dcr_register(dcr, DMA0_CR2, dma, &dcr_read_dma, &dcr_write_dma); 287 ppc4xx_dcr_register(dcr, DMA0_CT2, dma, &dcr_read_dma, &dcr_write_dma); 288 ppc4xx_dcr_register(dcr, DMA0_DA2, dma, &dcr_read_dma, &dcr_write_dma); 289 ppc4xx_dcr_register(dcr, DMA0_SA2, dma, &dcr_read_dma, &dcr_write_dma); 290 ppc4xx_dcr_register(dcr, DMA0_SG2, dma, &dcr_read_dma, &dcr_write_dma); 291 ppc4xx_dcr_register(dcr, DMA0_CR3, dma, &dcr_read_dma, &dcr_write_dma); 292 ppc4xx_dcr_register(dcr, DMA0_CT3, dma, &dcr_read_dma, &dcr_write_dma); 293 ppc4xx_dcr_register(dcr, DMA0_DA3, dma, &dcr_read_dma, &dcr_write_dma); 294 ppc4xx_dcr_register(dcr, DMA0_SA3, dma, &dcr_read_dma, &dcr_write_dma); 295 ppc4xx_dcr_register(dcr, DMA0_SG3, dma, &dcr_read_dma, &dcr_write_dma); 296 ppc4xx_dcr_register(dcr, DMA0_SR, dma, &dcr_read_dma, &dcr_write_dma); 297 ppc4xx_dcr_register(dcr, DMA0_SGC, dma, &dcr_read_dma, &dcr_write_dma); 298 ppc4xx_dcr_register(dcr, DMA0_SLP, dma, &dcr_read_dma, &dcr_write_dma); 299 ppc4xx_dcr_register(dcr, DMA0_POL, dma, &dcr_read_dma, &dcr_write_dma); 300 } 301 302 static void ppc405_dma_class_init(ObjectClass *oc, void *data) 303 { 304 DeviceClass *dc = DEVICE_CLASS(oc); 305 306 dc->realize = ppc405_dma_realize; 307 dc->reset = ppc405_dma_reset; 308 /* Reason: only works as function of a ppc4xx SoC */ 309 dc->user_creatable = false; 310 } 311 312 /*****************************************************************************/ 313 /* GPIO */ 314 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 315 { 316 trace_ppc405_gpio_read(addr, size); 317 return 0; 318 } 319 320 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 321 unsigned size) 322 { 323 trace_ppc405_gpio_write(addr, size, value); 324 } 325 326 static const MemoryRegionOps ppc405_gpio_ops = { 327 .read = ppc405_gpio_read, 328 .write = ppc405_gpio_write, 329 .endianness = DEVICE_NATIVE_ENDIAN, 330 }; 331 332 static void ppc405_gpio_realize(DeviceState *dev, Error **errp) 333 { 334 Ppc405GpioState *s = PPC405_GPIO(dev); 335 336 memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio", 337 0x38); 338 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); 339 } 340 341 static void ppc405_gpio_class_init(ObjectClass *oc, void *data) 342 { 343 DeviceClass *dc = DEVICE_CLASS(oc); 344 345 dc->realize = ppc405_gpio_realize; 346 /* Reason: only works as function of a ppc4xx SoC */ 347 dc->user_creatable = false; 348 } 349 350 /*****************************************************************************/ 351 /* On Chip Memory */ 352 enum { 353 OCM0_ISARC = 0x018, 354 OCM0_ISACNTL = 0x019, 355 OCM0_DSARC = 0x01A, 356 OCM0_DSACNTL = 0x01B, 357 }; 358 359 static void ocm_update_mappings(Ppc405OcmState *ocm, 360 uint32_t isarc, uint32_t isacntl, 361 uint32_t dsarc, uint32_t dsacntl) 362 { 363 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, 364 ocm->isacntl, ocm->dsarc, ocm->dsacntl); 365 366 if (ocm->isarc != isarc || 367 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 368 if (ocm->isacntl & 0x80000000) { 369 /* Unmap previously assigned memory region */ 370 trace_ocm_unmap("ISA", ocm->isarc); 371 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 372 } 373 if (isacntl & 0x80000000) { 374 /* Map new instruction memory region */ 375 trace_ocm_map("ISA", isarc); 376 memory_region_add_subregion(get_system_memory(), isarc, 377 &ocm->isarc_ram); 378 } 379 } 380 if (ocm->dsarc != dsarc || 381 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 382 if (ocm->dsacntl & 0x80000000) { 383 /* Beware not to unmap the region we just mapped */ 384 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 385 /* Unmap previously assigned memory region */ 386 trace_ocm_unmap("DSA", ocm->dsarc); 387 memory_region_del_subregion(get_system_memory(), 388 &ocm->dsarc_ram); 389 } 390 } 391 if (dsacntl & 0x80000000) { 392 /* Beware not to remap the region we just mapped */ 393 if (!(isacntl & 0x80000000) || dsarc != isarc) { 394 /* Map new data memory region */ 395 trace_ocm_map("DSA", dsarc); 396 memory_region_add_subregion(get_system_memory(), dsarc, 397 &ocm->dsarc_ram); 398 } 399 } 400 } 401 } 402 403 static uint32_t dcr_read_ocm(void *opaque, int dcrn) 404 { 405 Ppc405OcmState *ocm = opaque; 406 uint32_t ret; 407 408 switch (dcrn) { 409 case OCM0_ISARC: 410 ret = ocm->isarc; 411 break; 412 case OCM0_ISACNTL: 413 ret = ocm->isacntl; 414 break; 415 case OCM0_DSARC: 416 ret = ocm->dsarc; 417 break; 418 case OCM0_DSACNTL: 419 ret = ocm->dsacntl; 420 break; 421 default: 422 ret = 0; 423 break; 424 } 425 426 return ret; 427 } 428 429 static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val) 430 { 431 Ppc405OcmState *ocm = opaque; 432 uint32_t isarc, dsarc, isacntl, dsacntl; 433 434 isarc = ocm->isarc; 435 dsarc = ocm->dsarc; 436 isacntl = ocm->isacntl; 437 dsacntl = ocm->dsacntl; 438 switch (dcrn) { 439 case OCM0_ISARC: 440 isarc = val & 0xFC000000; 441 break; 442 case OCM0_ISACNTL: 443 isacntl = val & 0xC0000000; 444 break; 445 case OCM0_DSARC: 446 isarc = val & 0xFC000000; 447 break; 448 case OCM0_DSACNTL: 449 isacntl = val & 0xC0000000; 450 break; 451 } 452 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 453 ocm->isarc = isarc; 454 ocm->dsarc = dsarc; 455 ocm->isacntl = isacntl; 456 ocm->dsacntl = dsacntl; 457 } 458 459 static void ppc405_ocm_reset(DeviceState *dev) 460 { 461 Ppc405OcmState *ocm = PPC405_OCM(dev); 462 uint32_t isarc, dsarc, isacntl, dsacntl; 463 464 isarc = 0x00000000; 465 isacntl = 0x00000000; 466 dsarc = 0x00000000; 467 dsacntl = 0x00000000; 468 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 469 ocm->isarc = isarc; 470 ocm->dsarc = dsarc; 471 ocm->isacntl = isacntl; 472 ocm->dsacntl = dsacntl; 473 } 474 475 static void ppc405_ocm_realize(DeviceState *dev, Error **errp) 476 { 477 Ppc405OcmState *ocm = PPC405_OCM(dev); 478 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 479 480 /* XXX: Size is 4096 or 0x04000000 */ 481 memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB, 482 &error_fatal); 483 memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc", 484 &ocm->isarc_ram, 0, 4 * KiB); 485 486 ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm); 487 ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm); 488 ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_ocm); 489 ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm); 490 } 491 492 static void ppc405_ocm_class_init(ObjectClass *oc, void *data) 493 { 494 DeviceClass *dc = DEVICE_CLASS(oc); 495 496 dc->realize = ppc405_ocm_realize; 497 dc->reset = ppc405_ocm_reset; 498 /* Reason: only works as function of a ppc4xx SoC */ 499 dc->user_creatable = false; 500 } 501 502 /*****************************************************************************/ 503 /* General purpose timers */ 504 static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n) 505 { 506 /* XXX: TODO */ 507 return 0; 508 } 509 510 static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level) 511 { 512 /* XXX: TODO */ 513 } 514 515 static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt) 516 { 517 uint32_t mask; 518 int i; 519 520 mask = 0x80000000; 521 for (i = 0; i < 5; i++) { 522 if (gpt->oe & mask) { 523 /* Output is enabled */ 524 if (ppc4xx_gpt_compare(gpt, i)) { 525 /* Comparison is OK */ 526 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 527 } else { 528 /* Comparison is KO */ 529 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 530 } 531 } 532 mask = mask >> 1; 533 } 534 } 535 536 static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) 537 { 538 uint32_t mask; 539 int i; 540 541 mask = 0x00008000; 542 for (i = 0; i < 5; i++) { 543 if (gpt->is & gpt->im & mask) { 544 qemu_irq_raise(gpt->irqs[i]); 545 } else { 546 qemu_irq_lower(gpt->irqs[i]); 547 } 548 mask = mask >> 1; 549 } 550 } 551 552 static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt) 553 { 554 /* XXX: TODO */ 555 } 556 557 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 558 { 559 Ppc405GptState *gpt = opaque; 560 uint32_t ret; 561 int idx; 562 563 trace_ppc4xx_gpt_read(addr, size); 564 565 switch (addr) { 566 case 0x00: 567 /* Time base counter */ 568 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 569 gpt->tb_freq, NANOSECONDS_PER_SECOND); 570 break; 571 case 0x10: 572 /* Output enable */ 573 ret = gpt->oe; 574 break; 575 case 0x14: 576 /* Output level */ 577 ret = gpt->ol; 578 break; 579 case 0x18: 580 /* Interrupt mask */ 581 ret = gpt->im; 582 break; 583 case 0x1C: 584 case 0x20: 585 /* Interrupt status */ 586 ret = gpt->is; 587 break; 588 case 0x24: 589 /* Interrupt enable */ 590 ret = gpt->ie; 591 break; 592 case 0x80 ... 0x90: 593 /* Compare timer */ 594 idx = (addr - 0x80) >> 2; 595 ret = gpt->comp[idx]; 596 break; 597 case 0xC0 ... 0xD0: 598 /* Compare mask */ 599 idx = (addr - 0xC0) >> 2; 600 ret = gpt->mask[idx]; 601 break; 602 default: 603 ret = -1; 604 break; 605 } 606 607 return ret; 608 } 609 610 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 611 unsigned size) 612 { 613 Ppc405GptState *gpt = opaque; 614 int idx; 615 616 trace_ppc4xx_gpt_write(addr, size, value); 617 618 switch (addr) { 619 case 0x00: 620 /* Time base counter */ 621 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 622 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 623 ppc4xx_gpt_compute_timer(gpt); 624 break; 625 case 0x10: 626 /* Output enable */ 627 gpt->oe = value & 0xF8000000; 628 ppc4xx_gpt_set_outputs(gpt); 629 break; 630 case 0x14: 631 /* Output level */ 632 gpt->ol = value & 0xF8000000; 633 ppc4xx_gpt_set_outputs(gpt); 634 break; 635 case 0x18: 636 /* Interrupt mask */ 637 gpt->im = value & 0x0000F800; 638 break; 639 case 0x1C: 640 /* Interrupt status set */ 641 gpt->is |= value & 0x0000F800; 642 ppc4xx_gpt_set_irqs(gpt); 643 break; 644 case 0x20: 645 /* Interrupt status clear */ 646 gpt->is &= ~(value & 0x0000F800); 647 ppc4xx_gpt_set_irqs(gpt); 648 break; 649 case 0x24: 650 /* Interrupt enable */ 651 gpt->ie = value & 0x0000F800; 652 ppc4xx_gpt_set_irqs(gpt); 653 break; 654 case 0x80 ... 0x90: 655 /* Compare timer */ 656 idx = (addr - 0x80) >> 2; 657 gpt->comp[idx] = value & 0xF8000000; 658 ppc4xx_gpt_compute_timer(gpt); 659 break; 660 case 0xC0 ... 0xD0: 661 /* Compare mask */ 662 idx = (addr - 0xC0) >> 2; 663 gpt->mask[idx] = value & 0xF8000000; 664 ppc4xx_gpt_compute_timer(gpt); 665 break; 666 } 667 } 668 669 static const MemoryRegionOps gpt_ops = { 670 .read = ppc4xx_gpt_read, 671 .write = ppc4xx_gpt_write, 672 .valid.min_access_size = 4, 673 .valid.max_access_size = 4, 674 .endianness = DEVICE_NATIVE_ENDIAN, 675 }; 676 677 static void ppc4xx_gpt_cb(void *opaque) 678 { 679 Ppc405GptState *gpt = opaque; 680 681 ppc4xx_gpt_set_irqs(gpt); 682 ppc4xx_gpt_set_outputs(gpt); 683 ppc4xx_gpt_compute_timer(gpt); 684 } 685 686 static void ppc405_gpt_reset(DeviceState *dev) 687 { 688 Ppc405GptState *gpt = PPC405_GPT(dev); 689 int i; 690 691 timer_del(gpt->timer); 692 gpt->oe = 0x00000000; 693 gpt->ol = 0x00000000; 694 gpt->im = 0x00000000; 695 gpt->is = 0x00000000; 696 gpt->ie = 0x00000000; 697 for (i = 0; i < 5; i++) { 698 gpt->comp[i] = 0x00000000; 699 gpt->mask[i] = 0x00000000; 700 } 701 } 702 703 static void ppc405_gpt_realize(DeviceState *dev, Error **errp) 704 { 705 Ppc405GptState *s = PPC405_GPT(dev); 706 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 707 int i; 708 709 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s); 710 memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4); 711 sysbus_init_mmio(sbd, &s->iomem); 712 713 for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { 714 sysbus_init_irq(sbd, &s->irqs[i]); 715 } 716 } 717 718 static void ppc405_gpt_finalize(Object *obj) 719 { 720 /* timer will be NULL if the GPT wasn't realized */ 721 if (PPC405_GPT(obj)->timer) { 722 timer_del(PPC405_GPT(obj)->timer); 723 } 724 } 725 726 static void ppc405_gpt_class_init(ObjectClass *oc, void *data) 727 { 728 DeviceClass *dc = DEVICE_CLASS(oc); 729 730 dc->realize = ppc405_gpt_realize; 731 dc->reset = ppc405_gpt_reset; 732 /* Reason: only works as function of a ppc4xx SoC */ 733 dc->user_creatable = false; 734 } 735 736 /*****************************************************************************/ 737 /* PowerPC 405EP */ 738 /* CPU control */ 739 enum { 740 PPC405EP_CPC0_PLLMR0 = 0x0F0, 741 PPC405EP_CPC0_BOOT = 0x0F1, 742 PPC405EP_CPC0_EPCTL = 0x0F3, 743 PPC405EP_CPC0_PLLMR1 = 0x0F4, 744 PPC405EP_CPC0_UCR = 0x0F5, 745 PPC405EP_CPC0_SRR = 0x0F6, 746 PPC405EP_CPC0_JTAGID = 0x0F7, 747 PPC405EP_CPC0_PCI = 0x0F9, 748 #if 0 749 PPC405EP_CPC0_ER = xxx, 750 PPC405EP_CPC0_FR = xxx, 751 PPC405EP_CPC0_SR = xxx, 752 #endif 753 }; 754 755 static void ppc405ep_compute_clocks(Ppc405CpcState *cpc) 756 { 757 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 758 uint32_t UART0_clk, UART1_clk; 759 uint64_t VCO_out, PLL_out; 760 int M, D; 761 762 VCO_out = 0; 763 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 764 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 765 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); 766 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 767 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); 768 VCO_out = (uint64_t)cpc->sysclk * M * D; 769 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 770 /* Error - unlock the PLL */ 771 qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", 772 VCO_out); 773 #if 0 774 cpc->pllmr[1] &= ~0x80000000; 775 goto pll_bypass; 776 #endif 777 } 778 PLL_out = VCO_out / D; 779 /* Pretend the PLL is locked */ 780 cpc->boot |= 0x00000001; 781 } else { 782 #if 0 783 pll_bypass: 784 #endif 785 PLL_out = cpc->sysclk; 786 if (cpc->pllmr[1] & 0x40000000) { 787 /* Pretend the PLL is not locked */ 788 cpc->boot &= ~0x00000001; 789 } 790 } 791 /* Now, compute all other clocks */ 792 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 793 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); 794 CPU_clk = PLL_out / D; 795 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 796 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); 797 PLB_clk = CPU_clk / D; 798 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 799 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); 800 OPB_clk = PLB_clk / D; 801 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 802 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); 803 EBC_clk = PLB_clk / D; 804 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 805 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); 806 MAL_clk = PLB_clk / D; 807 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 808 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); 809 PCI_clk = PLB_clk / D; 810 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 811 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); 812 UART0_clk = PLL_out / D; 813 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 814 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); 815 UART1_clk = PLL_out / D; 816 817 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { 818 g_autofree char *trace = g_strdup_printf( 819 "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 820 " PLL out %" PRIu64 " Hz\n" 821 "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 822 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 823 " UART1 %" PRIu32 "\n", 824 cpc->sysclk, VCO_out, PLL_out, 825 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 826 UART0_clk, UART1_clk); 827 trace_ppc405ep_clocks_setup(trace); 828 } 829 830 /* Setup CPU clocks */ 831 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 832 /* Setup PLB clock */ 833 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 834 /* Setup OPB clock */ 835 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 836 /* Setup external clock */ 837 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 838 /* Setup MAL clock */ 839 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 840 /* Setup PCI clock */ 841 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 842 /* Setup UART0 clock */ 843 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 844 /* Setup UART1 clock */ 845 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 846 } 847 848 static uint32_t dcr_read_epcpc(void *opaque, int dcrn) 849 { 850 Ppc405CpcState *cpc = opaque; 851 uint32_t ret; 852 853 switch (dcrn) { 854 case PPC405EP_CPC0_BOOT: 855 ret = cpc->boot; 856 break; 857 case PPC405EP_CPC0_EPCTL: 858 ret = cpc->epctl; 859 break; 860 case PPC405EP_CPC0_PLLMR0: 861 ret = cpc->pllmr[0]; 862 break; 863 case PPC405EP_CPC0_PLLMR1: 864 ret = cpc->pllmr[1]; 865 break; 866 case PPC405EP_CPC0_UCR: 867 ret = cpc->ucr; 868 break; 869 case PPC405EP_CPC0_SRR: 870 ret = cpc->srr; 871 break; 872 case PPC405EP_CPC0_JTAGID: 873 ret = cpc->jtagid; 874 break; 875 case PPC405EP_CPC0_PCI: 876 ret = cpc->pci; 877 break; 878 default: 879 /* Avoid gcc warning */ 880 ret = 0; 881 break; 882 } 883 884 return ret; 885 } 886 887 static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val) 888 { 889 Ppc405CpcState *cpc = opaque; 890 891 switch (dcrn) { 892 case PPC405EP_CPC0_BOOT: 893 /* Read-only register */ 894 break; 895 case PPC405EP_CPC0_EPCTL: 896 /* Don't care for now */ 897 cpc->epctl = val & 0xC00000F3; 898 break; 899 case PPC405EP_CPC0_PLLMR0: 900 cpc->pllmr[0] = val & 0x00633333; 901 ppc405ep_compute_clocks(cpc); 902 break; 903 case PPC405EP_CPC0_PLLMR1: 904 cpc->pllmr[1] = val & 0xC0F73FFF; 905 ppc405ep_compute_clocks(cpc); 906 break; 907 case PPC405EP_CPC0_UCR: 908 /* UART control - don't care for now */ 909 cpc->ucr = val & 0x003F7F7F; 910 break; 911 case PPC405EP_CPC0_SRR: 912 cpc->srr = val; 913 break; 914 case PPC405EP_CPC0_JTAGID: 915 /* Read-only */ 916 break; 917 case PPC405EP_CPC0_PCI: 918 cpc->pci = val; 919 break; 920 } 921 } 922 923 static void ppc405_cpc_reset(DeviceState *dev) 924 { 925 Ppc405CpcState *cpc = PPC405_CPC(dev); 926 927 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 928 cpc->epctl = 0x00000000; 929 cpc->pllmr[0] = 0x00021002; 930 cpc->pllmr[1] = 0x80a552be; 931 cpc->ucr = 0x00004646; 932 cpc->srr = 0x00040000; 933 cpc->pci = 0x00000000; 934 cpc->er = 0x00000000; 935 cpc->fr = 0x00000000; 936 cpc->sr = 0x00000000; 937 cpc->jtagid = 0x20267049; 938 ppc405ep_compute_clocks(cpc); 939 } 940 941 /* XXX: sysclk should be between 25 and 100 MHz */ 942 static void ppc405_cpc_realize(DeviceState *dev, Error **errp) 943 { 944 Ppc405CpcState *cpc = PPC405_CPC(dev); 945 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 946 947 assert(dcr->cpu); 948 cpc->clk_setup[PPC405EP_CPU_CLK].cb = 949 ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT); 950 cpc->clk_setup[PPC405EP_CPU_CLK].opaque = &dcr->cpu->env; 951 952 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc, 953 &dcr_read_epcpc, &dcr_write_epcpc); 954 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc, 955 &dcr_read_epcpc, &dcr_write_epcpc); 956 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc, 957 &dcr_read_epcpc, &dcr_write_epcpc); 958 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc, 959 &dcr_read_epcpc, &dcr_write_epcpc); 960 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc, 961 &dcr_read_epcpc, &dcr_write_epcpc); 962 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc, 963 &dcr_read_epcpc, &dcr_write_epcpc); 964 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc, 965 &dcr_read_epcpc, &dcr_write_epcpc); 966 ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc, 967 &dcr_read_epcpc, &dcr_write_epcpc); 968 } 969 970 static Property ppc405_cpc_properties[] = { 971 DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0), 972 DEFINE_PROP_END_OF_LIST(), 973 }; 974 975 static void ppc405_cpc_class_init(ObjectClass *oc, void *data) 976 { 977 DeviceClass *dc = DEVICE_CLASS(oc); 978 979 dc->realize = ppc405_cpc_realize; 980 dc->reset = ppc405_cpc_reset; 981 /* Reason: only works as function of a ppc4xx SoC */ 982 dc->user_creatable = false; 983 device_class_set_props(dc, ppc405_cpc_properties); 984 } 985 986 /* PPC405_SOC */ 987 988 static void ppc405_soc_instance_init(Object *obj) 989 { 990 Ppc405SoCState *s = PPC405_SOC(obj); 991 992 object_initialize_child(obj, "cpu", &s->cpu, 993 POWERPC_CPU_TYPE_NAME("405ep")); 994 995 object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC); 996 997 object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); 998 object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); 999 1000 object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); 1001 1002 object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); 1003 1004 object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); 1005 1006 object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); 1007 1008 object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C); 1009 1010 object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC4xx_EBC); 1011 1012 object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); 1013 1014 object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); 1015 1016 object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB); 1017 1018 object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL); 1019 } 1020 1021 static void ppc405_reset(void *opaque) 1022 { 1023 cpu_reset(CPU(opaque)); 1024 } 1025 1026 static void ppc405_soc_realize(DeviceState *dev, Error **errp) 1027 { 1028 Ppc405SoCState *s = PPC405_SOC(dev); 1029 CPUPPCState *env; 1030 SysBusDevice *sbd; 1031 int i; 1032 1033 /* init CPUs */ 1034 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { 1035 return; 1036 } 1037 qemu_register_reset(ppc405_reset, &s->cpu); 1038 1039 env = &s->cpu.env; 1040 1041 ppc_dcr_init(env, NULL, NULL); 1042 1043 /* CPU control */ 1044 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) { 1045 return; 1046 } 1047 1048 /* PLB arbitrer */ 1049 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) { 1050 return; 1051 } 1052 1053 /* PLB to OPB bridge */ 1054 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) { 1055 return; 1056 } 1057 1058 /* OBP arbitrer */ 1059 sbd = SYS_BUS_DEVICE(&s->opba); 1060 if (!sysbus_realize(sbd, errp)) { 1061 return; 1062 } 1063 sysbus_mmio_map(sbd, 0, 0xef600600); 1064 1065 /* Universal interrupt controller */ 1066 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->uic), &s->cpu, errp)) { 1067 return; 1068 } 1069 sbd = SYS_BUS_DEVICE(&s->uic); 1070 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, 1071 qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)); 1072 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, 1073 qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT)); 1074 1075 /* SDRAM controller */ 1076 /* XXX 405EP has no ECC interrupt */ 1077 s->ram_banks[0].base = 0; 1078 s->ram_banks[0].size = s->ram_size; 1079 memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s), 1080 "ppc405.sdram0", s->dram_mr, 1081 s->ram_banks[0].base, s->ram_banks[0].size); 1082 1083 ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, 1084 s->ram_banks); 1085 1086 /* External bus controller */ 1087 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { 1088 return; 1089 } 1090 1091 /* DMA controller */ 1092 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) { 1093 return; 1094 } 1095 sbd = SYS_BUS_DEVICE(&s->dma); 1096 for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) { 1097 sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 5 + i)); 1098 } 1099 1100 /* I2C controller */ 1101 sbd = SYS_BUS_DEVICE(&s->i2c); 1102 if (!sysbus_realize(sbd, errp)) { 1103 return; 1104 } 1105 sysbus_mmio_map(sbd, 0, 0xef600500); 1106 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->uic), 2)); 1107 1108 /* GPIO */ 1109 sbd = SYS_BUS_DEVICE(&s->gpio); 1110 if (!sysbus_realize(sbd, errp)) { 1111 return; 1112 } 1113 sysbus_mmio_map(sbd, 0, 0xef600700); 1114 1115 /* Serial ports */ 1116 if (serial_hd(0) != NULL) { 1117 serial_mm_init(get_system_memory(), 0xef600300, 0, 1118 qdev_get_gpio_in(DEVICE(&s->uic), 0), 1119 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1120 DEVICE_BIG_ENDIAN); 1121 } 1122 if (serial_hd(1) != NULL) { 1123 serial_mm_init(get_system_memory(), 0xef600400, 0, 1124 qdev_get_gpio_in(DEVICE(&s->uic), 1), 1125 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1126 DEVICE_BIG_ENDIAN); 1127 } 1128 1129 /* OCM */ 1130 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) { 1131 return; 1132 } 1133 1134 /* GPT */ 1135 sbd = SYS_BUS_DEVICE(&s->gpt); 1136 if (!sysbus_realize(sbd, errp)) { 1137 return; 1138 } 1139 sysbus_mmio_map(sbd, 0, 0xef600000); 1140 for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { 1141 sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 19 + i)); 1142 } 1143 1144 /* MAL */ 1145 object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort); 1146 object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort); 1147 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) { 1148 return; 1149 } 1150 sbd = SYS_BUS_DEVICE(&s->mal); 1151 for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) { 1152 sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 11 + i)); 1153 } 1154 1155 /* Ethernet */ 1156 /* Uses UIC IRQs 9, 15, 17 */ 1157 } 1158 1159 static Property ppc405_soc_properties[] = { 1160 DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, 1161 MemoryRegion *), 1162 DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), 1163 DEFINE_PROP_END_OF_LIST(), 1164 }; 1165 1166 static void ppc405_soc_class_init(ObjectClass *oc, void *data) 1167 { 1168 DeviceClass *dc = DEVICE_CLASS(oc); 1169 1170 dc->realize = ppc405_soc_realize; 1171 /* Reason: only works as part of a ppc405 board/machine */ 1172 dc->user_creatable = false; 1173 device_class_set_props(dc, ppc405_soc_properties); 1174 } 1175 1176 static const TypeInfo ppc405_types[] = { 1177 { 1178 .name = TYPE_PPC405_POB, 1179 .parent = TYPE_PPC4xx_DCR_DEVICE, 1180 .instance_size = sizeof(Ppc405PobState), 1181 .class_init = ppc405_pob_class_init, 1182 }, { 1183 .name = TYPE_PPC405_OPBA, 1184 .parent = TYPE_SYS_BUS_DEVICE, 1185 .instance_size = sizeof(Ppc405OpbaState), 1186 .class_init = ppc405_opba_class_init, 1187 }, { 1188 .name = TYPE_PPC405_DMA, 1189 .parent = TYPE_PPC4xx_DCR_DEVICE, 1190 .instance_size = sizeof(Ppc405DmaState), 1191 .class_init = ppc405_dma_class_init, 1192 }, { 1193 .name = TYPE_PPC405_GPIO, 1194 .parent = TYPE_SYS_BUS_DEVICE, 1195 .instance_size = sizeof(Ppc405GpioState), 1196 .class_init = ppc405_gpio_class_init, 1197 }, { 1198 .name = TYPE_PPC405_OCM, 1199 .parent = TYPE_PPC4xx_DCR_DEVICE, 1200 .instance_size = sizeof(Ppc405OcmState), 1201 .class_init = ppc405_ocm_class_init, 1202 }, { 1203 .name = TYPE_PPC405_GPT, 1204 .parent = TYPE_SYS_BUS_DEVICE, 1205 .instance_size = sizeof(Ppc405GptState), 1206 .instance_finalize = ppc405_gpt_finalize, 1207 .class_init = ppc405_gpt_class_init, 1208 }, { 1209 .name = TYPE_PPC405_CPC, 1210 .parent = TYPE_PPC4xx_DCR_DEVICE, 1211 .instance_size = sizeof(Ppc405CpcState), 1212 .class_init = ppc405_cpc_class_init, 1213 }, { 1214 .name = TYPE_PPC405_SOC, 1215 .parent = TYPE_DEVICE, 1216 .instance_size = sizeof(Ppc405SoCState), 1217 .instance_init = ppc405_soc_instance_init, 1218 .class_init = ppc405_soc_class_init, 1219 } 1220 }; 1221 1222 DEFINE_TYPES(ppc405_types) 1223