1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/hw.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/boards.h" 32 #include "hw/i2c/ppc4xx_i2c.h" 33 #include "hw/irq.h" 34 #include "ppc405.h" 35 #include "hw/char/serial.h" 36 #include "qemu/timer.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/sysemu.h" 39 #include "qemu/log.h" 40 #include "exec/address-spaces.h" 41 42 //#define DEBUG_OPBA 43 //#define DEBUG_SDRAM 44 //#define DEBUG_GPIO 45 //#define DEBUG_SERIAL 46 //#define DEBUG_OCM 47 //#define DEBUG_GPT 48 //#define DEBUG_CLOCKS 49 //#define DEBUG_CLOCKS_LL 50 51 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 52 uint32_t flags) 53 { 54 CPUState *cs = env_cpu(env); 55 ram_addr_t bdloc; 56 int i, n; 57 58 /* We put the bd structure at the top of memory */ 59 if (bd->bi_memsize >= 0x01000000UL) 60 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 61 else 62 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 63 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 64 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 65 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 66 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 67 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 68 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 69 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 70 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 71 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 72 for (i = 0; i < 6; i++) { 73 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 74 } 75 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 76 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 77 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 78 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 79 for (i = 0; i < 4; i++) { 80 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 81 } 82 for (i = 0; i < 32; i++) { 83 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 84 } 85 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 86 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 87 for (i = 0; i < 6; i++) { 88 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 89 } 90 n = 0x6A; 91 if (flags & 0x00000001) { 92 for (i = 0; i < 6; i++) 93 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 94 } 95 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 96 n += 4; 97 for (i = 0; i < 2; i++) { 98 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 99 n += 4; 100 } 101 102 return bdloc; 103 } 104 105 /*****************************************************************************/ 106 /* Shared peripherals */ 107 108 /*****************************************************************************/ 109 /* Peripheral local bus arbitrer */ 110 enum { 111 PLB3A0_ACR = 0x077, 112 PLB4A0_ACR = 0x081, 113 PLB0_BESR = 0x084, 114 PLB0_BEAR = 0x086, 115 PLB0_ACR = 0x087, 116 PLB4A1_ACR = 0x089, 117 }; 118 119 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 120 struct ppc4xx_plb_t { 121 uint32_t acr; 122 uint32_t bear; 123 uint32_t besr; 124 }; 125 126 static uint32_t dcr_read_plb (void *opaque, int dcrn) 127 { 128 ppc4xx_plb_t *plb; 129 uint32_t ret; 130 131 plb = opaque; 132 switch (dcrn) { 133 case PLB0_ACR: 134 ret = plb->acr; 135 break; 136 case PLB0_BEAR: 137 ret = plb->bear; 138 break; 139 case PLB0_BESR: 140 ret = plb->besr; 141 break; 142 default: 143 /* Avoid gcc warning */ 144 ret = 0; 145 break; 146 } 147 148 return ret; 149 } 150 151 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 152 { 153 ppc4xx_plb_t *plb; 154 155 plb = opaque; 156 switch (dcrn) { 157 case PLB0_ACR: 158 /* We don't care about the actual parameters written as 159 * we don't manage any priorities on the bus 160 */ 161 plb->acr = val & 0xF8000000; 162 break; 163 case PLB0_BEAR: 164 /* Read only */ 165 break; 166 case PLB0_BESR: 167 /* Write-clear */ 168 plb->besr &= ~val; 169 break; 170 } 171 } 172 173 static void ppc4xx_plb_reset (void *opaque) 174 { 175 ppc4xx_plb_t *plb; 176 177 plb = opaque; 178 plb->acr = 0x00000000; 179 plb->bear = 0x00000000; 180 plb->besr = 0x00000000; 181 } 182 183 void ppc4xx_plb_init(CPUPPCState *env) 184 { 185 ppc4xx_plb_t *plb; 186 187 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 188 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 189 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 190 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 191 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 192 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 193 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 194 qemu_register_reset(ppc4xx_plb_reset, plb); 195 } 196 197 /*****************************************************************************/ 198 /* PLB to OPB bridge */ 199 enum { 200 POB0_BESR0 = 0x0A0, 201 POB0_BESR1 = 0x0A2, 202 POB0_BEAR = 0x0A4, 203 }; 204 205 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 206 struct ppc4xx_pob_t { 207 uint32_t bear; 208 uint32_t besr0; 209 uint32_t besr1; 210 }; 211 212 static uint32_t dcr_read_pob (void *opaque, int dcrn) 213 { 214 ppc4xx_pob_t *pob; 215 uint32_t ret; 216 217 pob = opaque; 218 switch (dcrn) { 219 case POB0_BEAR: 220 ret = pob->bear; 221 break; 222 case POB0_BESR0: 223 ret = pob->besr0; 224 break; 225 case POB0_BESR1: 226 ret = pob->besr1; 227 break; 228 default: 229 /* Avoid gcc warning */ 230 ret = 0; 231 break; 232 } 233 234 return ret; 235 } 236 237 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 238 { 239 ppc4xx_pob_t *pob; 240 241 pob = opaque; 242 switch (dcrn) { 243 case POB0_BEAR: 244 /* Read only */ 245 break; 246 case POB0_BESR0: 247 /* Write-clear */ 248 pob->besr0 &= ~val; 249 break; 250 case POB0_BESR1: 251 /* Write-clear */ 252 pob->besr1 &= ~val; 253 break; 254 } 255 } 256 257 static void ppc4xx_pob_reset (void *opaque) 258 { 259 ppc4xx_pob_t *pob; 260 261 pob = opaque; 262 /* No error */ 263 pob->bear = 0x00000000; 264 pob->besr0 = 0x0000000; 265 pob->besr1 = 0x0000000; 266 } 267 268 static void ppc4xx_pob_init(CPUPPCState *env) 269 { 270 ppc4xx_pob_t *pob; 271 272 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 273 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 274 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 275 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 276 qemu_register_reset(ppc4xx_pob_reset, pob); 277 } 278 279 /*****************************************************************************/ 280 /* OPB arbitrer */ 281 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 282 struct ppc4xx_opba_t { 283 MemoryRegion io; 284 uint8_t cr; 285 uint8_t pr; 286 }; 287 288 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 289 { 290 ppc4xx_opba_t *opba; 291 uint32_t ret; 292 293 #ifdef DEBUG_OPBA 294 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 295 #endif 296 opba = opaque; 297 switch (addr) { 298 case 0x00: 299 ret = opba->cr; 300 break; 301 case 0x01: 302 ret = opba->pr; 303 break; 304 default: 305 ret = 0x00; 306 break; 307 } 308 309 return ret; 310 } 311 312 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 313 unsigned size) 314 { 315 ppc4xx_opba_t *opba; 316 317 #ifdef DEBUG_OPBA 318 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 319 value); 320 #endif 321 opba = opaque; 322 switch (addr) { 323 case 0x00: 324 opba->cr = value & 0xF8; 325 break; 326 case 0x01: 327 opba->pr = value & 0xFF; 328 break; 329 default: 330 break; 331 } 332 } 333 static const MemoryRegionOps opba_ops = { 334 .read = opba_readb, 335 .write = opba_writeb, 336 .impl.min_access_size = 1, 337 .impl.max_access_size = 1, 338 .valid.min_access_size = 1, 339 .valid.max_access_size = 4, 340 .endianness = DEVICE_BIG_ENDIAN, 341 }; 342 343 static void ppc4xx_opba_reset (void *opaque) 344 { 345 ppc4xx_opba_t *opba; 346 347 opba = opaque; 348 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 349 opba->pr = 0x11; 350 } 351 352 static void ppc4xx_opba_init(hwaddr base) 353 { 354 ppc4xx_opba_t *opba; 355 356 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 357 #ifdef DEBUG_OPBA 358 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 359 #endif 360 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 361 memory_region_add_subregion(get_system_memory(), base, &opba->io); 362 qemu_register_reset(ppc4xx_opba_reset, opba); 363 } 364 365 /*****************************************************************************/ 366 /* Code decompression controller */ 367 /* XXX: TODO */ 368 369 /*****************************************************************************/ 370 /* Peripheral controller */ 371 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 372 struct ppc4xx_ebc_t { 373 uint32_t addr; 374 uint32_t bcr[8]; 375 uint32_t bap[8]; 376 uint32_t bear; 377 uint32_t besr0; 378 uint32_t besr1; 379 uint32_t cfg; 380 }; 381 382 enum { 383 EBC0_CFGADDR = 0x012, 384 EBC0_CFGDATA = 0x013, 385 }; 386 387 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 388 { 389 ppc4xx_ebc_t *ebc; 390 uint32_t ret; 391 392 ebc = opaque; 393 switch (dcrn) { 394 case EBC0_CFGADDR: 395 ret = ebc->addr; 396 break; 397 case EBC0_CFGDATA: 398 switch (ebc->addr) { 399 case 0x00: /* B0CR */ 400 ret = ebc->bcr[0]; 401 break; 402 case 0x01: /* B1CR */ 403 ret = ebc->bcr[1]; 404 break; 405 case 0x02: /* B2CR */ 406 ret = ebc->bcr[2]; 407 break; 408 case 0x03: /* B3CR */ 409 ret = ebc->bcr[3]; 410 break; 411 case 0x04: /* B4CR */ 412 ret = ebc->bcr[4]; 413 break; 414 case 0x05: /* B5CR */ 415 ret = ebc->bcr[5]; 416 break; 417 case 0x06: /* B6CR */ 418 ret = ebc->bcr[6]; 419 break; 420 case 0x07: /* B7CR */ 421 ret = ebc->bcr[7]; 422 break; 423 case 0x10: /* B0AP */ 424 ret = ebc->bap[0]; 425 break; 426 case 0x11: /* B1AP */ 427 ret = ebc->bap[1]; 428 break; 429 case 0x12: /* B2AP */ 430 ret = ebc->bap[2]; 431 break; 432 case 0x13: /* B3AP */ 433 ret = ebc->bap[3]; 434 break; 435 case 0x14: /* B4AP */ 436 ret = ebc->bap[4]; 437 break; 438 case 0x15: /* B5AP */ 439 ret = ebc->bap[5]; 440 break; 441 case 0x16: /* B6AP */ 442 ret = ebc->bap[6]; 443 break; 444 case 0x17: /* B7AP */ 445 ret = ebc->bap[7]; 446 break; 447 case 0x20: /* BEAR */ 448 ret = ebc->bear; 449 break; 450 case 0x21: /* BESR0 */ 451 ret = ebc->besr0; 452 break; 453 case 0x22: /* BESR1 */ 454 ret = ebc->besr1; 455 break; 456 case 0x23: /* CFG */ 457 ret = ebc->cfg; 458 break; 459 default: 460 ret = 0x00000000; 461 break; 462 } 463 break; 464 default: 465 ret = 0x00000000; 466 break; 467 } 468 469 return ret; 470 } 471 472 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 473 { 474 ppc4xx_ebc_t *ebc; 475 476 ebc = opaque; 477 switch (dcrn) { 478 case EBC0_CFGADDR: 479 ebc->addr = val; 480 break; 481 case EBC0_CFGDATA: 482 switch (ebc->addr) { 483 case 0x00: /* B0CR */ 484 break; 485 case 0x01: /* B1CR */ 486 break; 487 case 0x02: /* B2CR */ 488 break; 489 case 0x03: /* B3CR */ 490 break; 491 case 0x04: /* B4CR */ 492 break; 493 case 0x05: /* B5CR */ 494 break; 495 case 0x06: /* B6CR */ 496 break; 497 case 0x07: /* B7CR */ 498 break; 499 case 0x10: /* B0AP */ 500 break; 501 case 0x11: /* B1AP */ 502 break; 503 case 0x12: /* B2AP */ 504 break; 505 case 0x13: /* B3AP */ 506 break; 507 case 0x14: /* B4AP */ 508 break; 509 case 0x15: /* B5AP */ 510 break; 511 case 0x16: /* B6AP */ 512 break; 513 case 0x17: /* B7AP */ 514 break; 515 case 0x20: /* BEAR */ 516 break; 517 case 0x21: /* BESR0 */ 518 break; 519 case 0x22: /* BESR1 */ 520 break; 521 case 0x23: /* CFG */ 522 break; 523 default: 524 break; 525 } 526 break; 527 default: 528 break; 529 } 530 } 531 532 static void ebc_reset (void *opaque) 533 { 534 ppc4xx_ebc_t *ebc; 535 int i; 536 537 ebc = opaque; 538 ebc->addr = 0x00000000; 539 ebc->bap[0] = 0x7F8FFE80; 540 ebc->bcr[0] = 0xFFE28000; 541 for (i = 0; i < 8; i++) { 542 ebc->bap[i] = 0x00000000; 543 ebc->bcr[i] = 0x00000000; 544 } 545 ebc->besr0 = 0x00000000; 546 ebc->besr1 = 0x00000000; 547 ebc->cfg = 0x80400000; 548 } 549 550 void ppc405_ebc_init(CPUPPCState *env) 551 { 552 ppc4xx_ebc_t *ebc; 553 554 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 555 qemu_register_reset(&ebc_reset, ebc); 556 ppc_dcr_register(env, EBC0_CFGADDR, 557 ebc, &dcr_read_ebc, &dcr_write_ebc); 558 ppc_dcr_register(env, EBC0_CFGDATA, 559 ebc, &dcr_read_ebc, &dcr_write_ebc); 560 } 561 562 /*****************************************************************************/ 563 /* DMA controller */ 564 enum { 565 DMA0_CR0 = 0x100, 566 DMA0_CT0 = 0x101, 567 DMA0_DA0 = 0x102, 568 DMA0_SA0 = 0x103, 569 DMA0_SG0 = 0x104, 570 DMA0_CR1 = 0x108, 571 DMA0_CT1 = 0x109, 572 DMA0_DA1 = 0x10A, 573 DMA0_SA1 = 0x10B, 574 DMA0_SG1 = 0x10C, 575 DMA0_CR2 = 0x110, 576 DMA0_CT2 = 0x111, 577 DMA0_DA2 = 0x112, 578 DMA0_SA2 = 0x113, 579 DMA0_SG2 = 0x114, 580 DMA0_CR3 = 0x118, 581 DMA0_CT3 = 0x119, 582 DMA0_DA3 = 0x11A, 583 DMA0_SA3 = 0x11B, 584 DMA0_SG3 = 0x11C, 585 DMA0_SR = 0x120, 586 DMA0_SGC = 0x123, 587 DMA0_SLP = 0x125, 588 DMA0_POL = 0x126, 589 }; 590 591 typedef struct ppc405_dma_t ppc405_dma_t; 592 struct ppc405_dma_t { 593 qemu_irq irqs[4]; 594 uint32_t cr[4]; 595 uint32_t ct[4]; 596 uint32_t da[4]; 597 uint32_t sa[4]; 598 uint32_t sg[4]; 599 uint32_t sr; 600 uint32_t sgc; 601 uint32_t slp; 602 uint32_t pol; 603 }; 604 605 static uint32_t dcr_read_dma (void *opaque, int dcrn) 606 { 607 return 0; 608 } 609 610 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 611 { 612 } 613 614 static void ppc405_dma_reset (void *opaque) 615 { 616 ppc405_dma_t *dma; 617 int i; 618 619 dma = opaque; 620 for (i = 0; i < 4; i++) { 621 dma->cr[i] = 0x00000000; 622 dma->ct[i] = 0x00000000; 623 dma->da[i] = 0x00000000; 624 dma->sa[i] = 0x00000000; 625 dma->sg[i] = 0x00000000; 626 } 627 dma->sr = 0x00000000; 628 dma->sgc = 0x00000000; 629 dma->slp = 0x7C000000; 630 dma->pol = 0x00000000; 631 } 632 633 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 634 { 635 ppc405_dma_t *dma; 636 637 dma = g_malloc0(sizeof(ppc405_dma_t)); 638 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 639 qemu_register_reset(&ppc405_dma_reset, dma); 640 ppc_dcr_register(env, DMA0_CR0, 641 dma, &dcr_read_dma, &dcr_write_dma); 642 ppc_dcr_register(env, DMA0_CT0, 643 dma, &dcr_read_dma, &dcr_write_dma); 644 ppc_dcr_register(env, DMA0_DA0, 645 dma, &dcr_read_dma, &dcr_write_dma); 646 ppc_dcr_register(env, DMA0_SA0, 647 dma, &dcr_read_dma, &dcr_write_dma); 648 ppc_dcr_register(env, DMA0_SG0, 649 dma, &dcr_read_dma, &dcr_write_dma); 650 ppc_dcr_register(env, DMA0_CR1, 651 dma, &dcr_read_dma, &dcr_write_dma); 652 ppc_dcr_register(env, DMA0_CT1, 653 dma, &dcr_read_dma, &dcr_write_dma); 654 ppc_dcr_register(env, DMA0_DA1, 655 dma, &dcr_read_dma, &dcr_write_dma); 656 ppc_dcr_register(env, DMA0_SA1, 657 dma, &dcr_read_dma, &dcr_write_dma); 658 ppc_dcr_register(env, DMA0_SG1, 659 dma, &dcr_read_dma, &dcr_write_dma); 660 ppc_dcr_register(env, DMA0_CR2, 661 dma, &dcr_read_dma, &dcr_write_dma); 662 ppc_dcr_register(env, DMA0_CT2, 663 dma, &dcr_read_dma, &dcr_write_dma); 664 ppc_dcr_register(env, DMA0_DA2, 665 dma, &dcr_read_dma, &dcr_write_dma); 666 ppc_dcr_register(env, DMA0_SA2, 667 dma, &dcr_read_dma, &dcr_write_dma); 668 ppc_dcr_register(env, DMA0_SG2, 669 dma, &dcr_read_dma, &dcr_write_dma); 670 ppc_dcr_register(env, DMA0_CR3, 671 dma, &dcr_read_dma, &dcr_write_dma); 672 ppc_dcr_register(env, DMA0_CT3, 673 dma, &dcr_read_dma, &dcr_write_dma); 674 ppc_dcr_register(env, DMA0_DA3, 675 dma, &dcr_read_dma, &dcr_write_dma); 676 ppc_dcr_register(env, DMA0_SA3, 677 dma, &dcr_read_dma, &dcr_write_dma); 678 ppc_dcr_register(env, DMA0_SG3, 679 dma, &dcr_read_dma, &dcr_write_dma); 680 ppc_dcr_register(env, DMA0_SR, 681 dma, &dcr_read_dma, &dcr_write_dma); 682 ppc_dcr_register(env, DMA0_SGC, 683 dma, &dcr_read_dma, &dcr_write_dma); 684 ppc_dcr_register(env, DMA0_SLP, 685 dma, &dcr_read_dma, &dcr_write_dma); 686 ppc_dcr_register(env, DMA0_POL, 687 dma, &dcr_read_dma, &dcr_write_dma); 688 } 689 690 /*****************************************************************************/ 691 /* GPIO */ 692 typedef struct ppc405_gpio_t ppc405_gpio_t; 693 struct ppc405_gpio_t { 694 MemoryRegion io; 695 uint32_t or; 696 uint32_t tcr; 697 uint32_t osrh; 698 uint32_t osrl; 699 uint32_t tsrh; 700 uint32_t tsrl; 701 uint32_t odr; 702 uint32_t ir; 703 uint32_t rr1; 704 uint32_t isr1h; 705 uint32_t isr1l; 706 }; 707 708 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 709 { 710 #ifdef DEBUG_GPIO 711 printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); 712 #endif 713 714 return 0; 715 } 716 717 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 718 unsigned size) 719 { 720 #ifdef DEBUG_GPIO 721 printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", 722 __func__, addr, size, value); 723 #endif 724 } 725 726 static const MemoryRegionOps ppc405_gpio_ops = { 727 .read = ppc405_gpio_read, 728 .write = ppc405_gpio_write, 729 .endianness = DEVICE_NATIVE_ENDIAN, 730 }; 731 732 static void ppc405_gpio_reset (void *opaque) 733 { 734 } 735 736 static void ppc405_gpio_init(hwaddr base) 737 { 738 ppc405_gpio_t *gpio; 739 740 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 741 #ifdef DEBUG_GPIO 742 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 743 #endif 744 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 745 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 746 qemu_register_reset(&ppc405_gpio_reset, gpio); 747 } 748 749 /*****************************************************************************/ 750 /* On Chip Memory */ 751 enum { 752 OCM0_ISARC = 0x018, 753 OCM0_ISACNTL = 0x019, 754 OCM0_DSARC = 0x01A, 755 OCM0_DSACNTL = 0x01B, 756 }; 757 758 typedef struct ppc405_ocm_t ppc405_ocm_t; 759 struct ppc405_ocm_t { 760 MemoryRegion ram; 761 MemoryRegion isarc_ram; 762 MemoryRegion dsarc_ram; 763 uint32_t isarc; 764 uint32_t isacntl; 765 uint32_t dsarc; 766 uint32_t dsacntl; 767 }; 768 769 static void ocm_update_mappings (ppc405_ocm_t *ocm, 770 uint32_t isarc, uint32_t isacntl, 771 uint32_t dsarc, uint32_t dsacntl) 772 { 773 #ifdef DEBUG_OCM 774 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 775 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 776 " (%08" PRIx32 " %08" PRIx32 ")\n", 777 isarc, isacntl, dsarc, dsacntl, 778 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 779 #endif 780 if (ocm->isarc != isarc || 781 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 782 if (ocm->isacntl & 0x80000000) { 783 /* Unmap previously assigned memory region */ 784 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 785 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 786 } 787 if (isacntl & 0x80000000) { 788 /* Map new instruction memory region */ 789 #ifdef DEBUG_OCM 790 printf("OCM map ISA %08" PRIx32 "\n", isarc); 791 #endif 792 memory_region_add_subregion(get_system_memory(), isarc, 793 &ocm->isarc_ram); 794 } 795 } 796 if (ocm->dsarc != dsarc || 797 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 798 if (ocm->dsacntl & 0x80000000) { 799 /* Beware not to unmap the region we just mapped */ 800 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 801 /* Unmap previously assigned memory region */ 802 #ifdef DEBUG_OCM 803 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 804 #endif 805 memory_region_del_subregion(get_system_memory(), 806 &ocm->dsarc_ram); 807 } 808 } 809 if (dsacntl & 0x80000000) { 810 /* Beware not to remap the region we just mapped */ 811 if (!(isacntl & 0x80000000) || dsarc != isarc) { 812 /* Map new data memory region */ 813 #ifdef DEBUG_OCM 814 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 815 #endif 816 memory_region_add_subregion(get_system_memory(), dsarc, 817 &ocm->dsarc_ram); 818 } 819 } 820 } 821 } 822 823 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 824 { 825 ppc405_ocm_t *ocm; 826 uint32_t ret; 827 828 ocm = opaque; 829 switch (dcrn) { 830 case OCM0_ISARC: 831 ret = ocm->isarc; 832 break; 833 case OCM0_ISACNTL: 834 ret = ocm->isacntl; 835 break; 836 case OCM0_DSARC: 837 ret = ocm->dsarc; 838 break; 839 case OCM0_DSACNTL: 840 ret = ocm->dsacntl; 841 break; 842 default: 843 ret = 0; 844 break; 845 } 846 847 return ret; 848 } 849 850 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 851 { 852 ppc405_ocm_t *ocm; 853 uint32_t isarc, dsarc, isacntl, dsacntl; 854 855 ocm = opaque; 856 isarc = ocm->isarc; 857 dsarc = ocm->dsarc; 858 isacntl = ocm->isacntl; 859 dsacntl = ocm->dsacntl; 860 switch (dcrn) { 861 case OCM0_ISARC: 862 isarc = val & 0xFC000000; 863 break; 864 case OCM0_ISACNTL: 865 isacntl = val & 0xC0000000; 866 break; 867 case OCM0_DSARC: 868 isarc = val & 0xFC000000; 869 break; 870 case OCM0_DSACNTL: 871 isacntl = val & 0xC0000000; 872 break; 873 } 874 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 875 ocm->isarc = isarc; 876 ocm->dsarc = dsarc; 877 ocm->isacntl = isacntl; 878 ocm->dsacntl = dsacntl; 879 } 880 881 static void ocm_reset (void *opaque) 882 { 883 ppc405_ocm_t *ocm; 884 uint32_t isarc, dsarc, isacntl, dsacntl; 885 886 ocm = opaque; 887 isarc = 0x00000000; 888 isacntl = 0x00000000; 889 dsarc = 0x00000000; 890 dsacntl = 0x00000000; 891 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 892 ocm->isarc = isarc; 893 ocm->dsarc = dsarc; 894 ocm->isacntl = isacntl; 895 ocm->dsacntl = dsacntl; 896 } 897 898 static void ppc405_ocm_init(CPUPPCState *env) 899 { 900 ppc405_ocm_t *ocm; 901 902 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 903 /* XXX: Size is 4096 or 0x04000000 */ 904 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 905 &error_fatal); 906 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 907 &ocm->isarc_ram, 0, 4 * KiB); 908 qemu_register_reset(&ocm_reset, ocm); 909 ppc_dcr_register(env, OCM0_ISARC, 910 ocm, &dcr_read_ocm, &dcr_write_ocm); 911 ppc_dcr_register(env, OCM0_ISACNTL, 912 ocm, &dcr_read_ocm, &dcr_write_ocm); 913 ppc_dcr_register(env, OCM0_DSARC, 914 ocm, &dcr_read_ocm, &dcr_write_ocm); 915 ppc_dcr_register(env, OCM0_DSACNTL, 916 ocm, &dcr_read_ocm, &dcr_write_ocm); 917 } 918 919 /*****************************************************************************/ 920 /* General purpose timers */ 921 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 922 struct ppc4xx_gpt_t { 923 MemoryRegion iomem; 924 int64_t tb_offset; 925 uint32_t tb_freq; 926 QEMUTimer *timer; 927 qemu_irq irqs[5]; 928 uint32_t oe; 929 uint32_t ol; 930 uint32_t im; 931 uint32_t is; 932 uint32_t ie; 933 uint32_t comp[5]; 934 uint32_t mask[5]; 935 }; 936 937 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 938 { 939 /* XXX: TODO */ 940 return 0; 941 } 942 943 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 944 { 945 /* XXX: TODO */ 946 } 947 948 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 949 { 950 uint32_t mask; 951 int i; 952 953 mask = 0x80000000; 954 for (i = 0; i < 5; i++) { 955 if (gpt->oe & mask) { 956 /* Output is enabled */ 957 if (ppc4xx_gpt_compare(gpt, i)) { 958 /* Comparison is OK */ 959 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 960 } else { 961 /* Comparison is KO */ 962 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 963 } 964 } 965 mask = mask >> 1; 966 } 967 } 968 969 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 970 { 971 uint32_t mask; 972 int i; 973 974 mask = 0x00008000; 975 for (i = 0; i < 5; i++) { 976 if (gpt->is & gpt->im & mask) 977 qemu_irq_raise(gpt->irqs[i]); 978 else 979 qemu_irq_lower(gpt->irqs[i]); 980 mask = mask >> 1; 981 } 982 } 983 984 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 985 { 986 /* XXX: TODO */ 987 } 988 989 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 990 { 991 ppc4xx_gpt_t *gpt; 992 uint32_t ret; 993 int idx; 994 995 #ifdef DEBUG_GPT 996 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 997 #endif 998 gpt = opaque; 999 switch (addr) { 1000 case 0x00: 1001 /* Time base counter */ 1002 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1003 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1004 break; 1005 case 0x10: 1006 /* Output enable */ 1007 ret = gpt->oe; 1008 break; 1009 case 0x14: 1010 /* Output level */ 1011 ret = gpt->ol; 1012 break; 1013 case 0x18: 1014 /* Interrupt mask */ 1015 ret = gpt->im; 1016 break; 1017 case 0x1C: 1018 case 0x20: 1019 /* Interrupt status */ 1020 ret = gpt->is; 1021 break; 1022 case 0x24: 1023 /* Interrupt enable */ 1024 ret = gpt->ie; 1025 break; 1026 case 0x80 ... 0x90: 1027 /* Compare timer */ 1028 idx = (addr - 0x80) >> 2; 1029 ret = gpt->comp[idx]; 1030 break; 1031 case 0xC0 ... 0xD0: 1032 /* Compare mask */ 1033 idx = (addr - 0xC0) >> 2; 1034 ret = gpt->mask[idx]; 1035 break; 1036 default: 1037 ret = -1; 1038 break; 1039 } 1040 1041 return ret; 1042 } 1043 1044 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1045 unsigned size) 1046 { 1047 ppc4xx_gpt_t *gpt; 1048 int idx; 1049 1050 #ifdef DEBUG_I2C 1051 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1052 value); 1053 #endif 1054 gpt = opaque; 1055 switch (addr) { 1056 case 0x00: 1057 /* Time base counter */ 1058 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1059 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1060 ppc4xx_gpt_compute_timer(gpt); 1061 break; 1062 case 0x10: 1063 /* Output enable */ 1064 gpt->oe = value & 0xF8000000; 1065 ppc4xx_gpt_set_outputs(gpt); 1066 break; 1067 case 0x14: 1068 /* Output level */ 1069 gpt->ol = value & 0xF8000000; 1070 ppc4xx_gpt_set_outputs(gpt); 1071 break; 1072 case 0x18: 1073 /* Interrupt mask */ 1074 gpt->im = value & 0x0000F800; 1075 break; 1076 case 0x1C: 1077 /* Interrupt status set */ 1078 gpt->is |= value & 0x0000F800; 1079 ppc4xx_gpt_set_irqs(gpt); 1080 break; 1081 case 0x20: 1082 /* Interrupt status clear */ 1083 gpt->is &= ~(value & 0x0000F800); 1084 ppc4xx_gpt_set_irqs(gpt); 1085 break; 1086 case 0x24: 1087 /* Interrupt enable */ 1088 gpt->ie = value & 0x0000F800; 1089 ppc4xx_gpt_set_irqs(gpt); 1090 break; 1091 case 0x80 ... 0x90: 1092 /* Compare timer */ 1093 idx = (addr - 0x80) >> 2; 1094 gpt->comp[idx] = value & 0xF8000000; 1095 ppc4xx_gpt_compute_timer(gpt); 1096 break; 1097 case 0xC0 ... 0xD0: 1098 /* Compare mask */ 1099 idx = (addr - 0xC0) >> 2; 1100 gpt->mask[idx] = value & 0xF8000000; 1101 ppc4xx_gpt_compute_timer(gpt); 1102 break; 1103 } 1104 } 1105 1106 static const MemoryRegionOps gpt_ops = { 1107 .read = ppc4xx_gpt_read, 1108 .write = ppc4xx_gpt_write, 1109 .valid.min_access_size = 4, 1110 .valid.max_access_size = 4, 1111 .endianness = DEVICE_NATIVE_ENDIAN, 1112 }; 1113 1114 static void ppc4xx_gpt_cb (void *opaque) 1115 { 1116 ppc4xx_gpt_t *gpt; 1117 1118 gpt = opaque; 1119 ppc4xx_gpt_set_irqs(gpt); 1120 ppc4xx_gpt_set_outputs(gpt); 1121 ppc4xx_gpt_compute_timer(gpt); 1122 } 1123 1124 static void ppc4xx_gpt_reset (void *opaque) 1125 { 1126 ppc4xx_gpt_t *gpt; 1127 int i; 1128 1129 gpt = opaque; 1130 timer_del(gpt->timer); 1131 gpt->oe = 0x00000000; 1132 gpt->ol = 0x00000000; 1133 gpt->im = 0x00000000; 1134 gpt->is = 0x00000000; 1135 gpt->ie = 0x00000000; 1136 for (i = 0; i < 5; i++) { 1137 gpt->comp[i] = 0x00000000; 1138 gpt->mask[i] = 0x00000000; 1139 } 1140 } 1141 1142 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1143 { 1144 ppc4xx_gpt_t *gpt; 1145 int i; 1146 1147 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1148 for (i = 0; i < 5; i++) { 1149 gpt->irqs[i] = irqs[i]; 1150 } 1151 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1152 #ifdef DEBUG_GPT 1153 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1154 #endif 1155 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1156 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1157 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1158 } 1159 1160 /*****************************************************************************/ 1161 /* PowerPC 405CR */ 1162 enum { 1163 PPC405CR_CPC0_PLLMR = 0x0B0, 1164 PPC405CR_CPC0_CR0 = 0x0B1, 1165 PPC405CR_CPC0_CR1 = 0x0B2, 1166 PPC405CR_CPC0_PSR = 0x0B4, 1167 PPC405CR_CPC0_JTAGID = 0x0B5, 1168 PPC405CR_CPC0_ER = 0x0B9, 1169 PPC405CR_CPC0_FR = 0x0BA, 1170 PPC405CR_CPC0_SR = 0x0BB, 1171 }; 1172 1173 enum { 1174 PPC405CR_CPU_CLK = 0, 1175 PPC405CR_TMR_CLK = 1, 1176 PPC405CR_PLB_CLK = 2, 1177 PPC405CR_SDRAM_CLK = 3, 1178 PPC405CR_OPB_CLK = 4, 1179 PPC405CR_EXT_CLK = 5, 1180 PPC405CR_UART_CLK = 6, 1181 PPC405CR_CLK_NB = 7, 1182 }; 1183 1184 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; 1185 struct ppc405cr_cpc_t { 1186 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1187 uint32_t sysclk; 1188 uint32_t psr; 1189 uint32_t cr0; 1190 uint32_t cr1; 1191 uint32_t jtagid; 1192 uint32_t pllmr; 1193 uint32_t er; 1194 uint32_t fr; 1195 }; 1196 1197 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) 1198 { 1199 uint64_t VCO_out, PLL_out; 1200 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; 1201 int M, D0, D1, D2; 1202 1203 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ 1204 if (cpc->pllmr & 0x80000000) { 1205 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ 1206 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ 1207 M = D0 * D1 * D2; 1208 VCO_out = (uint64_t)cpc->sysclk * M; 1209 if (VCO_out < 400000000 || VCO_out > 800000000) { 1210 /* PLL cannot lock */ 1211 cpc->pllmr &= ~0x80000000; 1212 goto bypass_pll; 1213 } 1214 PLL_out = VCO_out / D2; 1215 } else { 1216 /* Bypass PLL */ 1217 bypass_pll: 1218 M = D0; 1219 PLL_out = (uint64_t)cpc->sysclk * M; 1220 } 1221 CPU_clk = PLL_out; 1222 if (cpc->cr1 & 0x00800000) 1223 TMR_clk = cpc->sysclk; /* Should have a separate clock */ 1224 else 1225 TMR_clk = CPU_clk; 1226 PLB_clk = CPU_clk / D0; 1227 SDRAM_clk = PLB_clk; 1228 D0 = ((cpc->pllmr >> 10) & 0x3) + 1; 1229 OPB_clk = PLB_clk / D0; 1230 D0 = ((cpc->pllmr >> 24) & 0x3) + 2; 1231 EXT_clk = PLB_clk / D0; 1232 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; 1233 UART_clk = CPU_clk / D0; 1234 /* Setup CPU clocks */ 1235 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); 1236 /* Setup time-base clock */ 1237 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); 1238 /* Setup PLB clock */ 1239 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); 1240 /* Setup SDRAM clock */ 1241 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); 1242 /* Setup OPB clock */ 1243 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); 1244 /* Setup external clock */ 1245 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); 1246 /* Setup UART clock */ 1247 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); 1248 } 1249 1250 static uint32_t dcr_read_crcpc (void *opaque, int dcrn) 1251 { 1252 ppc405cr_cpc_t *cpc; 1253 uint32_t ret; 1254 1255 cpc = opaque; 1256 switch (dcrn) { 1257 case PPC405CR_CPC0_PLLMR: 1258 ret = cpc->pllmr; 1259 break; 1260 case PPC405CR_CPC0_CR0: 1261 ret = cpc->cr0; 1262 break; 1263 case PPC405CR_CPC0_CR1: 1264 ret = cpc->cr1; 1265 break; 1266 case PPC405CR_CPC0_PSR: 1267 ret = cpc->psr; 1268 break; 1269 case PPC405CR_CPC0_JTAGID: 1270 ret = cpc->jtagid; 1271 break; 1272 case PPC405CR_CPC0_ER: 1273 ret = cpc->er; 1274 break; 1275 case PPC405CR_CPC0_FR: 1276 ret = cpc->fr; 1277 break; 1278 case PPC405CR_CPC0_SR: 1279 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; 1280 break; 1281 default: 1282 /* Avoid gcc warning */ 1283 ret = 0; 1284 break; 1285 } 1286 1287 return ret; 1288 } 1289 1290 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) 1291 { 1292 ppc405cr_cpc_t *cpc; 1293 1294 cpc = opaque; 1295 switch (dcrn) { 1296 case PPC405CR_CPC0_PLLMR: 1297 cpc->pllmr = val & 0xFFF77C3F; 1298 break; 1299 case PPC405CR_CPC0_CR0: 1300 cpc->cr0 = val & 0x0FFFFFFE; 1301 break; 1302 case PPC405CR_CPC0_CR1: 1303 cpc->cr1 = val & 0x00800000; 1304 break; 1305 case PPC405CR_CPC0_PSR: 1306 /* Read-only */ 1307 break; 1308 case PPC405CR_CPC0_JTAGID: 1309 /* Read-only */ 1310 break; 1311 case PPC405CR_CPC0_ER: 1312 cpc->er = val & 0xBFFC0000; 1313 break; 1314 case PPC405CR_CPC0_FR: 1315 cpc->fr = val & 0xBFFC0000; 1316 break; 1317 case PPC405CR_CPC0_SR: 1318 /* Read-only */ 1319 break; 1320 } 1321 } 1322 1323 static void ppc405cr_cpc_reset (void *opaque) 1324 { 1325 ppc405cr_cpc_t *cpc; 1326 int D; 1327 1328 cpc = opaque; 1329 /* Compute PLLMR value from PSR settings */ 1330 cpc->pllmr = 0x80000000; 1331 /* PFWD */ 1332 switch ((cpc->psr >> 30) & 3) { 1333 case 0: 1334 /* Bypass */ 1335 cpc->pllmr &= ~0x80000000; 1336 break; 1337 case 1: 1338 /* Divide by 3 */ 1339 cpc->pllmr |= 5 << 16; 1340 break; 1341 case 2: 1342 /* Divide by 4 */ 1343 cpc->pllmr |= 4 << 16; 1344 break; 1345 case 3: 1346 /* Divide by 6 */ 1347 cpc->pllmr |= 2 << 16; 1348 break; 1349 } 1350 /* PFBD */ 1351 D = (cpc->psr >> 28) & 3; 1352 cpc->pllmr |= (D + 1) << 20; 1353 /* PT */ 1354 D = (cpc->psr >> 25) & 7; 1355 switch (D) { 1356 case 0x2: 1357 cpc->pllmr |= 0x13; 1358 break; 1359 case 0x4: 1360 cpc->pllmr |= 0x15; 1361 break; 1362 case 0x5: 1363 cpc->pllmr |= 0x16; 1364 break; 1365 default: 1366 break; 1367 } 1368 /* PDC */ 1369 D = (cpc->psr >> 23) & 3; 1370 cpc->pllmr |= D << 26; 1371 /* ODP */ 1372 D = (cpc->psr >> 21) & 3; 1373 cpc->pllmr |= D << 10; 1374 /* EBPD */ 1375 D = (cpc->psr >> 17) & 3; 1376 cpc->pllmr |= D << 24; 1377 cpc->cr0 = 0x0000003C; 1378 cpc->cr1 = 0x2B0D8800; 1379 cpc->er = 0x00000000; 1380 cpc->fr = 0x00000000; 1381 ppc405cr_clk_setup(cpc); 1382 } 1383 1384 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) 1385 { 1386 int D; 1387 1388 /* XXX: this should be read from IO pins */ 1389 cpc->psr = 0x00000000; /* 8 bits ROM */ 1390 /* PFWD */ 1391 D = 0x2; /* Divide by 4 */ 1392 cpc->psr |= D << 30; 1393 /* PFBD */ 1394 D = 0x1; /* Divide by 2 */ 1395 cpc->psr |= D << 28; 1396 /* PDC */ 1397 D = 0x1; /* Divide by 2 */ 1398 cpc->psr |= D << 23; 1399 /* PT */ 1400 D = 0x5; /* M = 16 */ 1401 cpc->psr |= D << 25; 1402 /* ODP */ 1403 D = 0x1; /* Divide by 2 */ 1404 cpc->psr |= D << 21; 1405 /* EBDP */ 1406 D = 0x2; /* Divide by 4 */ 1407 cpc->psr |= D << 17; 1408 } 1409 1410 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], 1411 uint32_t sysclk) 1412 { 1413 ppc405cr_cpc_t *cpc; 1414 1415 cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); 1416 memcpy(cpc->clk_setup, clk_setup, 1417 PPC405CR_CLK_NB * sizeof(clk_setup_t)); 1418 cpc->sysclk = sysclk; 1419 cpc->jtagid = 0x42051049; 1420 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, 1421 &dcr_read_crcpc, &dcr_write_crcpc); 1422 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, 1423 &dcr_read_crcpc, &dcr_write_crcpc); 1424 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, 1425 &dcr_read_crcpc, &dcr_write_crcpc); 1426 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, 1427 &dcr_read_crcpc, &dcr_write_crcpc); 1428 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, 1429 &dcr_read_crcpc, &dcr_write_crcpc); 1430 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, 1431 &dcr_read_crcpc, &dcr_write_crcpc); 1432 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, 1433 &dcr_read_crcpc, &dcr_write_crcpc); 1434 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, 1435 &dcr_read_crcpc, &dcr_write_crcpc); 1436 ppc405cr_clk_init(cpc); 1437 qemu_register_reset(ppc405cr_cpc_reset, cpc); 1438 } 1439 1440 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, 1441 MemoryRegion ram_memories[4], 1442 hwaddr ram_bases[4], 1443 hwaddr ram_sizes[4], 1444 uint32_t sysclk, qemu_irq **picp, 1445 int do_init) 1446 { 1447 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1448 qemu_irq dma_irqs[4]; 1449 PowerPCCPU *cpu; 1450 CPUPPCState *env; 1451 qemu_irq *pic, *irqs; 1452 1453 memset(clk_setup, 0, sizeof(clk_setup)); 1454 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), 1455 &clk_setup[PPC405CR_CPU_CLK], 1456 &clk_setup[PPC405CR_TMR_CLK], sysclk); 1457 env = &cpu->env; 1458 /* Memory mapped devices registers */ 1459 /* PLB arbitrer */ 1460 ppc4xx_plb_init(env); 1461 /* PLB to OPB bridge */ 1462 ppc4xx_pob_init(env); 1463 /* OBP arbitrer */ 1464 ppc4xx_opba_init(0xef600600); 1465 /* Universal interrupt controller */ 1466 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 1467 irqs[PPCUIC_OUTPUT_INT] = 1468 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 1469 irqs[PPCUIC_OUTPUT_CINT] = 1470 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 1471 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 1472 *picp = pic; 1473 /* SDRAM controller */ 1474 ppc4xx_sdram_init(env, pic[14], 1, ram_memories, 1475 ram_bases, ram_sizes, do_init); 1476 /* External bus controller */ 1477 ppc405_ebc_init(env); 1478 /* DMA controller */ 1479 dma_irqs[0] = pic[26]; 1480 dma_irqs[1] = pic[25]; 1481 dma_irqs[2] = pic[24]; 1482 dma_irqs[3] = pic[23]; 1483 ppc405_dma_init(env, dma_irqs); 1484 /* Serial ports */ 1485 if (serial_hd(0) != NULL) { 1486 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 1487 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1488 DEVICE_BIG_ENDIAN); 1489 } 1490 if (serial_hd(1) != NULL) { 1491 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 1492 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1493 DEVICE_BIG_ENDIAN); 1494 } 1495 /* IIC controller */ 1496 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 1497 /* GPIO */ 1498 ppc405_gpio_init(0xef600700); 1499 /* CPU control */ 1500 ppc405cr_cpc_init(env, clk_setup, sysclk); 1501 1502 return env; 1503 } 1504 1505 /*****************************************************************************/ 1506 /* PowerPC 405EP */ 1507 /* CPU control */ 1508 enum { 1509 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1510 PPC405EP_CPC0_BOOT = 0x0F1, 1511 PPC405EP_CPC0_EPCTL = 0x0F3, 1512 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1513 PPC405EP_CPC0_UCR = 0x0F5, 1514 PPC405EP_CPC0_SRR = 0x0F6, 1515 PPC405EP_CPC0_JTAGID = 0x0F7, 1516 PPC405EP_CPC0_PCI = 0x0F9, 1517 #if 0 1518 PPC405EP_CPC0_ER = xxx, 1519 PPC405EP_CPC0_FR = xxx, 1520 PPC405EP_CPC0_SR = xxx, 1521 #endif 1522 }; 1523 1524 enum { 1525 PPC405EP_CPU_CLK = 0, 1526 PPC405EP_PLB_CLK = 1, 1527 PPC405EP_OPB_CLK = 2, 1528 PPC405EP_EBC_CLK = 3, 1529 PPC405EP_MAL_CLK = 4, 1530 PPC405EP_PCI_CLK = 5, 1531 PPC405EP_UART0_CLK = 6, 1532 PPC405EP_UART1_CLK = 7, 1533 PPC405EP_CLK_NB = 8, 1534 }; 1535 1536 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1537 struct ppc405ep_cpc_t { 1538 uint32_t sysclk; 1539 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1540 uint32_t boot; 1541 uint32_t epctl; 1542 uint32_t pllmr[2]; 1543 uint32_t ucr; 1544 uint32_t srr; 1545 uint32_t jtagid; 1546 uint32_t pci; 1547 /* Clock and power management */ 1548 uint32_t er; 1549 uint32_t fr; 1550 uint32_t sr; 1551 }; 1552 1553 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1554 { 1555 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1556 uint32_t UART0_clk, UART1_clk; 1557 uint64_t VCO_out, PLL_out; 1558 int M, D; 1559 1560 VCO_out = 0; 1561 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1562 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1563 #ifdef DEBUG_CLOCKS_LL 1564 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 1565 #endif 1566 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1567 #ifdef DEBUG_CLOCKS_LL 1568 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 1569 #endif 1570 VCO_out = (uint64_t)cpc->sysclk * M * D; 1571 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1572 /* Error - unlock the PLL */ 1573 printf("VCO out of range %" PRIu64 "\n", VCO_out); 1574 #if 0 1575 cpc->pllmr[1] &= ~0x80000000; 1576 goto pll_bypass; 1577 #endif 1578 } 1579 PLL_out = VCO_out / D; 1580 /* Pretend the PLL is locked */ 1581 cpc->boot |= 0x00000001; 1582 } else { 1583 #if 0 1584 pll_bypass: 1585 #endif 1586 PLL_out = cpc->sysclk; 1587 if (cpc->pllmr[1] & 0x40000000) { 1588 /* Pretend the PLL is not locked */ 1589 cpc->boot &= ~0x00000001; 1590 } 1591 } 1592 /* Now, compute all other clocks */ 1593 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1594 #ifdef DEBUG_CLOCKS_LL 1595 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 1596 #endif 1597 CPU_clk = PLL_out / D; 1598 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1599 #ifdef DEBUG_CLOCKS_LL 1600 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 1601 #endif 1602 PLB_clk = CPU_clk / D; 1603 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1604 #ifdef DEBUG_CLOCKS_LL 1605 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 1606 #endif 1607 OPB_clk = PLB_clk / D; 1608 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1609 #ifdef DEBUG_CLOCKS_LL 1610 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 1611 #endif 1612 EBC_clk = PLB_clk / D; 1613 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1614 #ifdef DEBUG_CLOCKS_LL 1615 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 1616 #endif 1617 MAL_clk = PLB_clk / D; 1618 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1619 #ifdef DEBUG_CLOCKS_LL 1620 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 1621 #endif 1622 PCI_clk = PLB_clk / D; 1623 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1624 #ifdef DEBUG_CLOCKS_LL 1625 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 1626 #endif 1627 UART0_clk = PLL_out / D; 1628 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1629 #ifdef DEBUG_CLOCKS_LL 1630 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 1631 #endif 1632 UART1_clk = PLL_out / D; 1633 #ifdef DEBUG_CLOCKS 1634 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1635 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 1636 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1637 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1638 " UART1 %" PRIu32 "\n", 1639 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1640 UART0_clk, UART1_clk); 1641 #endif 1642 /* Setup CPU clocks */ 1643 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1644 /* Setup PLB clock */ 1645 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1646 /* Setup OPB clock */ 1647 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1648 /* Setup external clock */ 1649 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1650 /* Setup MAL clock */ 1651 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1652 /* Setup PCI clock */ 1653 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1654 /* Setup UART0 clock */ 1655 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1656 /* Setup UART1 clock */ 1657 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1658 } 1659 1660 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1661 { 1662 ppc405ep_cpc_t *cpc; 1663 uint32_t ret; 1664 1665 cpc = opaque; 1666 switch (dcrn) { 1667 case PPC405EP_CPC0_BOOT: 1668 ret = cpc->boot; 1669 break; 1670 case PPC405EP_CPC0_EPCTL: 1671 ret = cpc->epctl; 1672 break; 1673 case PPC405EP_CPC0_PLLMR0: 1674 ret = cpc->pllmr[0]; 1675 break; 1676 case PPC405EP_CPC0_PLLMR1: 1677 ret = cpc->pllmr[1]; 1678 break; 1679 case PPC405EP_CPC0_UCR: 1680 ret = cpc->ucr; 1681 break; 1682 case PPC405EP_CPC0_SRR: 1683 ret = cpc->srr; 1684 break; 1685 case PPC405EP_CPC0_JTAGID: 1686 ret = cpc->jtagid; 1687 break; 1688 case PPC405EP_CPC0_PCI: 1689 ret = cpc->pci; 1690 break; 1691 default: 1692 /* Avoid gcc warning */ 1693 ret = 0; 1694 break; 1695 } 1696 1697 return ret; 1698 } 1699 1700 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1701 { 1702 ppc405ep_cpc_t *cpc; 1703 1704 cpc = opaque; 1705 switch (dcrn) { 1706 case PPC405EP_CPC0_BOOT: 1707 /* Read-only register */ 1708 break; 1709 case PPC405EP_CPC0_EPCTL: 1710 /* Don't care for now */ 1711 cpc->epctl = val & 0xC00000F3; 1712 break; 1713 case PPC405EP_CPC0_PLLMR0: 1714 cpc->pllmr[0] = val & 0x00633333; 1715 ppc405ep_compute_clocks(cpc); 1716 break; 1717 case PPC405EP_CPC0_PLLMR1: 1718 cpc->pllmr[1] = val & 0xC0F73FFF; 1719 ppc405ep_compute_clocks(cpc); 1720 break; 1721 case PPC405EP_CPC0_UCR: 1722 /* UART control - don't care for now */ 1723 cpc->ucr = val & 0x003F7F7F; 1724 break; 1725 case PPC405EP_CPC0_SRR: 1726 cpc->srr = val; 1727 break; 1728 case PPC405EP_CPC0_JTAGID: 1729 /* Read-only */ 1730 break; 1731 case PPC405EP_CPC0_PCI: 1732 cpc->pci = val; 1733 break; 1734 } 1735 } 1736 1737 static void ppc405ep_cpc_reset (void *opaque) 1738 { 1739 ppc405ep_cpc_t *cpc = opaque; 1740 1741 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1742 cpc->epctl = 0x00000000; 1743 cpc->pllmr[0] = 0x00011010; 1744 cpc->pllmr[1] = 0x40000000; 1745 cpc->ucr = 0x00000000; 1746 cpc->srr = 0x00040000; 1747 cpc->pci = 0x00000000; 1748 cpc->er = 0x00000000; 1749 cpc->fr = 0x00000000; 1750 cpc->sr = 0x00000000; 1751 ppc405ep_compute_clocks(cpc); 1752 } 1753 1754 /* XXX: sysclk should be between 25 and 100 MHz */ 1755 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1756 uint32_t sysclk) 1757 { 1758 ppc405ep_cpc_t *cpc; 1759 1760 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1761 memcpy(cpc->clk_setup, clk_setup, 1762 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1763 cpc->jtagid = 0x20267049; 1764 cpc->sysclk = sysclk; 1765 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1766 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1767 &dcr_read_epcpc, &dcr_write_epcpc); 1768 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1769 &dcr_read_epcpc, &dcr_write_epcpc); 1770 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1771 &dcr_read_epcpc, &dcr_write_epcpc); 1772 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1773 &dcr_read_epcpc, &dcr_write_epcpc); 1774 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1775 &dcr_read_epcpc, &dcr_write_epcpc); 1776 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1777 &dcr_read_epcpc, &dcr_write_epcpc); 1778 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1779 &dcr_read_epcpc, &dcr_write_epcpc); 1780 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1781 &dcr_read_epcpc, &dcr_write_epcpc); 1782 #if 0 1783 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1784 &dcr_read_epcpc, &dcr_write_epcpc); 1785 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1786 &dcr_read_epcpc, &dcr_write_epcpc); 1787 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1788 &dcr_read_epcpc, &dcr_write_epcpc); 1789 #endif 1790 } 1791 1792 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1793 MemoryRegion ram_memories[2], 1794 hwaddr ram_bases[2], 1795 hwaddr ram_sizes[2], 1796 uint32_t sysclk, qemu_irq **picp, 1797 int do_init) 1798 { 1799 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1800 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1801 PowerPCCPU *cpu; 1802 CPUPPCState *env; 1803 qemu_irq *pic, *irqs; 1804 1805 memset(clk_setup, 0, sizeof(clk_setup)); 1806 /* init CPUs */ 1807 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1808 &clk_setup[PPC405EP_CPU_CLK], 1809 &tlb_clk_setup, sysclk); 1810 env = &cpu->env; 1811 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1812 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1813 /* Internal devices init */ 1814 /* Memory mapped devices registers */ 1815 /* PLB arbitrer */ 1816 ppc4xx_plb_init(env); 1817 /* PLB to OPB bridge */ 1818 ppc4xx_pob_init(env); 1819 /* OBP arbitrer */ 1820 ppc4xx_opba_init(0xef600600); 1821 /* Initialize timers */ 1822 ppc_booke_timers_init(cpu, sysclk, 0); 1823 /* Universal interrupt controller */ 1824 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 1825 irqs[PPCUIC_OUTPUT_INT] = 1826 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 1827 irqs[PPCUIC_OUTPUT_CINT] = 1828 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 1829 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 1830 *picp = pic; 1831 /* SDRAM controller */ 1832 /* XXX 405EP has no ECC interrupt */ 1833 ppc4xx_sdram_init(env, pic[17], 2, ram_memories, 1834 ram_bases, ram_sizes, do_init); 1835 /* External bus controller */ 1836 ppc405_ebc_init(env); 1837 /* DMA controller */ 1838 dma_irqs[0] = pic[5]; 1839 dma_irqs[1] = pic[6]; 1840 dma_irqs[2] = pic[7]; 1841 dma_irqs[3] = pic[8]; 1842 ppc405_dma_init(env, dma_irqs); 1843 /* IIC controller */ 1844 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 1845 /* GPIO */ 1846 ppc405_gpio_init(0xef600700); 1847 /* Serial ports */ 1848 if (serial_hd(0) != NULL) { 1849 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 1850 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1851 DEVICE_BIG_ENDIAN); 1852 } 1853 if (serial_hd(1) != NULL) { 1854 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 1855 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1856 DEVICE_BIG_ENDIAN); 1857 } 1858 /* OCM */ 1859 ppc405_ocm_init(env); 1860 /* GPT */ 1861 gpt_irqs[0] = pic[19]; 1862 gpt_irqs[1] = pic[20]; 1863 gpt_irqs[2] = pic[21]; 1864 gpt_irqs[3] = pic[22]; 1865 gpt_irqs[4] = pic[23]; 1866 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1867 /* PCI */ 1868 /* Uses pic[3], pic[16], pic[18] */ 1869 /* MAL */ 1870 mal_irqs[0] = pic[11]; 1871 mal_irqs[1] = pic[12]; 1872 mal_irqs[2] = pic[13]; 1873 mal_irqs[3] = pic[14]; 1874 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1875 /* Ethernet */ 1876 /* Uses pic[9], pic[15], pic[17] */ 1877 /* CPU control */ 1878 ppc405ep_cpc_init(env, clk_setup, sysclk); 1879 1880 return env; 1881 } 1882