1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "hw/boards.h" 31 #include "ppc405.h" 32 #include "hw/char/serial.h" 33 #include "qemu/timer.h" 34 #include "sysemu/sysemu.h" 35 #include "qemu/log.h" 36 #include "exec/address-spaces.h" 37 38 //#define DEBUG_OPBA 39 //#define DEBUG_SDRAM 40 //#define DEBUG_GPIO 41 //#define DEBUG_SERIAL 42 //#define DEBUG_OCM 43 //#define DEBUG_I2C 44 //#define DEBUG_GPT 45 //#define DEBUG_MAL 46 //#define DEBUG_CLOCKS 47 //#define DEBUG_CLOCKS_LL 48 49 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 50 uint32_t flags) 51 { 52 CPUState *cs = CPU(ppc_env_get_cpu(env)); 53 ram_addr_t bdloc; 54 int i, n; 55 56 /* We put the bd structure at the top of memory */ 57 if (bd->bi_memsize >= 0x01000000UL) 58 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 59 else 60 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 61 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 62 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 63 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 64 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 65 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 66 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 67 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 68 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 69 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 70 for (i = 0; i < 6; i++) { 71 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 72 } 73 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 74 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 75 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 76 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 77 for (i = 0; i < 4; i++) { 78 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 79 } 80 for (i = 0; i < 32; i++) { 81 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 82 } 83 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 84 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 85 for (i = 0; i < 6; i++) { 86 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 87 } 88 n = 0x6A; 89 if (flags & 0x00000001) { 90 for (i = 0; i < 6; i++) 91 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 92 } 93 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 94 n += 4; 95 for (i = 0; i < 2; i++) { 96 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 97 n += 4; 98 } 99 100 return bdloc; 101 } 102 103 /*****************************************************************************/ 104 /* Shared peripherals */ 105 106 /*****************************************************************************/ 107 /* Peripheral local bus arbitrer */ 108 enum { 109 PLB0_BESR = 0x084, 110 PLB0_BEAR = 0x086, 111 PLB0_ACR = 0x087, 112 }; 113 114 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 115 struct ppc4xx_plb_t { 116 uint32_t acr; 117 uint32_t bear; 118 uint32_t besr; 119 }; 120 121 static uint32_t dcr_read_plb (void *opaque, int dcrn) 122 { 123 ppc4xx_plb_t *plb; 124 uint32_t ret; 125 126 plb = opaque; 127 switch (dcrn) { 128 case PLB0_ACR: 129 ret = plb->acr; 130 break; 131 case PLB0_BEAR: 132 ret = plb->bear; 133 break; 134 case PLB0_BESR: 135 ret = plb->besr; 136 break; 137 default: 138 /* Avoid gcc warning */ 139 ret = 0; 140 break; 141 } 142 143 return ret; 144 } 145 146 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 147 { 148 ppc4xx_plb_t *plb; 149 150 plb = opaque; 151 switch (dcrn) { 152 case PLB0_ACR: 153 /* We don't care about the actual parameters written as 154 * we don't manage any priorities on the bus 155 */ 156 plb->acr = val & 0xF8000000; 157 break; 158 case PLB0_BEAR: 159 /* Read only */ 160 break; 161 case PLB0_BESR: 162 /* Write-clear */ 163 plb->besr &= ~val; 164 break; 165 } 166 } 167 168 static void ppc4xx_plb_reset (void *opaque) 169 { 170 ppc4xx_plb_t *plb; 171 172 plb = opaque; 173 plb->acr = 0x00000000; 174 plb->bear = 0x00000000; 175 plb->besr = 0x00000000; 176 } 177 178 static void ppc4xx_plb_init(CPUPPCState *env) 179 { 180 ppc4xx_plb_t *plb; 181 182 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 183 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 184 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 185 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 186 qemu_register_reset(ppc4xx_plb_reset, plb); 187 } 188 189 /*****************************************************************************/ 190 /* PLB to OPB bridge */ 191 enum { 192 POB0_BESR0 = 0x0A0, 193 POB0_BESR1 = 0x0A2, 194 POB0_BEAR = 0x0A4, 195 }; 196 197 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 198 struct ppc4xx_pob_t { 199 uint32_t bear; 200 uint32_t besr0; 201 uint32_t besr1; 202 }; 203 204 static uint32_t dcr_read_pob (void *opaque, int dcrn) 205 { 206 ppc4xx_pob_t *pob; 207 uint32_t ret; 208 209 pob = opaque; 210 switch (dcrn) { 211 case POB0_BEAR: 212 ret = pob->bear; 213 break; 214 case POB0_BESR0: 215 ret = pob->besr0; 216 break; 217 case POB0_BESR1: 218 ret = pob->besr1; 219 break; 220 default: 221 /* Avoid gcc warning */ 222 ret = 0; 223 break; 224 } 225 226 return ret; 227 } 228 229 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 230 { 231 ppc4xx_pob_t *pob; 232 233 pob = opaque; 234 switch (dcrn) { 235 case POB0_BEAR: 236 /* Read only */ 237 break; 238 case POB0_BESR0: 239 /* Write-clear */ 240 pob->besr0 &= ~val; 241 break; 242 case POB0_BESR1: 243 /* Write-clear */ 244 pob->besr1 &= ~val; 245 break; 246 } 247 } 248 249 static void ppc4xx_pob_reset (void *opaque) 250 { 251 ppc4xx_pob_t *pob; 252 253 pob = opaque; 254 /* No error */ 255 pob->bear = 0x00000000; 256 pob->besr0 = 0x0000000; 257 pob->besr1 = 0x0000000; 258 } 259 260 static void ppc4xx_pob_init(CPUPPCState *env) 261 { 262 ppc4xx_pob_t *pob; 263 264 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 265 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 266 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 267 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 268 qemu_register_reset(ppc4xx_pob_reset, pob); 269 } 270 271 /*****************************************************************************/ 272 /* OPB arbitrer */ 273 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 274 struct ppc4xx_opba_t { 275 MemoryRegion io; 276 uint8_t cr; 277 uint8_t pr; 278 }; 279 280 static uint32_t opba_readb (void *opaque, hwaddr addr) 281 { 282 ppc4xx_opba_t *opba; 283 uint32_t ret; 284 285 #ifdef DEBUG_OPBA 286 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 287 #endif 288 opba = opaque; 289 switch (addr) { 290 case 0x00: 291 ret = opba->cr; 292 break; 293 case 0x01: 294 ret = opba->pr; 295 break; 296 default: 297 ret = 0x00; 298 break; 299 } 300 301 return ret; 302 } 303 304 static void opba_writeb (void *opaque, 305 hwaddr addr, uint32_t value) 306 { 307 ppc4xx_opba_t *opba; 308 309 #ifdef DEBUG_OPBA 310 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 311 value); 312 #endif 313 opba = opaque; 314 switch (addr) { 315 case 0x00: 316 opba->cr = value & 0xF8; 317 break; 318 case 0x01: 319 opba->pr = value & 0xFF; 320 break; 321 default: 322 break; 323 } 324 } 325 326 static uint32_t opba_readw (void *opaque, hwaddr addr) 327 { 328 uint32_t ret; 329 330 #ifdef DEBUG_OPBA 331 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 332 #endif 333 ret = opba_readb(opaque, addr) << 8; 334 ret |= opba_readb(opaque, addr + 1); 335 336 return ret; 337 } 338 339 static void opba_writew (void *opaque, 340 hwaddr addr, uint32_t value) 341 { 342 #ifdef DEBUG_OPBA 343 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 344 value); 345 #endif 346 opba_writeb(opaque, addr, value >> 8); 347 opba_writeb(opaque, addr + 1, value); 348 } 349 350 static uint32_t opba_readl (void *opaque, hwaddr addr) 351 { 352 uint32_t ret; 353 354 #ifdef DEBUG_OPBA 355 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 356 #endif 357 ret = opba_readb(opaque, addr) << 24; 358 ret |= opba_readb(opaque, addr + 1) << 16; 359 360 return ret; 361 } 362 363 static void opba_writel (void *opaque, 364 hwaddr addr, uint32_t value) 365 { 366 #ifdef DEBUG_OPBA 367 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 368 value); 369 #endif 370 opba_writeb(opaque, addr, value >> 24); 371 opba_writeb(opaque, addr + 1, value >> 16); 372 } 373 374 static const MemoryRegionOps opba_ops = { 375 .old_mmio = { 376 .read = { opba_readb, opba_readw, opba_readl, }, 377 .write = { opba_writeb, opba_writew, opba_writel, }, 378 }, 379 .endianness = DEVICE_NATIVE_ENDIAN, 380 }; 381 382 static void ppc4xx_opba_reset (void *opaque) 383 { 384 ppc4xx_opba_t *opba; 385 386 opba = opaque; 387 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 388 opba->pr = 0x11; 389 } 390 391 static void ppc4xx_opba_init(hwaddr base) 392 { 393 ppc4xx_opba_t *opba; 394 395 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 396 #ifdef DEBUG_OPBA 397 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 398 #endif 399 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 400 memory_region_add_subregion(get_system_memory(), base, &opba->io); 401 qemu_register_reset(ppc4xx_opba_reset, opba); 402 } 403 404 /*****************************************************************************/ 405 /* Code decompression controller */ 406 /* XXX: TODO */ 407 408 /*****************************************************************************/ 409 /* Peripheral controller */ 410 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 411 struct ppc4xx_ebc_t { 412 uint32_t addr; 413 uint32_t bcr[8]; 414 uint32_t bap[8]; 415 uint32_t bear; 416 uint32_t besr0; 417 uint32_t besr1; 418 uint32_t cfg; 419 }; 420 421 enum { 422 EBC0_CFGADDR = 0x012, 423 EBC0_CFGDATA = 0x013, 424 }; 425 426 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 427 { 428 ppc4xx_ebc_t *ebc; 429 uint32_t ret; 430 431 ebc = opaque; 432 switch (dcrn) { 433 case EBC0_CFGADDR: 434 ret = ebc->addr; 435 break; 436 case EBC0_CFGDATA: 437 switch (ebc->addr) { 438 case 0x00: /* B0CR */ 439 ret = ebc->bcr[0]; 440 break; 441 case 0x01: /* B1CR */ 442 ret = ebc->bcr[1]; 443 break; 444 case 0x02: /* B2CR */ 445 ret = ebc->bcr[2]; 446 break; 447 case 0x03: /* B3CR */ 448 ret = ebc->bcr[3]; 449 break; 450 case 0x04: /* B4CR */ 451 ret = ebc->bcr[4]; 452 break; 453 case 0x05: /* B5CR */ 454 ret = ebc->bcr[5]; 455 break; 456 case 0x06: /* B6CR */ 457 ret = ebc->bcr[6]; 458 break; 459 case 0x07: /* B7CR */ 460 ret = ebc->bcr[7]; 461 break; 462 case 0x10: /* B0AP */ 463 ret = ebc->bap[0]; 464 break; 465 case 0x11: /* B1AP */ 466 ret = ebc->bap[1]; 467 break; 468 case 0x12: /* B2AP */ 469 ret = ebc->bap[2]; 470 break; 471 case 0x13: /* B3AP */ 472 ret = ebc->bap[3]; 473 break; 474 case 0x14: /* B4AP */ 475 ret = ebc->bap[4]; 476 break; 477 case 0x15: /* B5AP */ 478 ret = ebc->bap[5]; 479 break; 480 case 0x16: /* B6AP */ 481 ret = ebc->bap[6]; 482 break; 483 case 0x17: /* B7AP */ 484 ret = ebc->bap[7]; 485 break; 486 case 0x20: /* BEAR */ 487 ret = ebc->bear; 488 break; 489 case 0x21: /* BESR0 */ 490 ret = ebc->besr0; 491 break; 492 case 0x22: /* BESR1 */ 493 ret = ebc->besr1; 494 break; 495 case 0x23: /* CFG */ 496 ret = ebc->cfg; 497 break; 498 default: 499 ret = 0x00000000; 500 break; 501 } 502 break; 503 default: 504 ret = 0x00000000; 505 break; 506 } 507 508 return ret; 509 } 510 511 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 512 { 513 ppc4xx_ebc_t *ebc; 514 515 ebc = opaque; 516 switch (dcrn) { 517 case EBC0_CFGADDR: 518 ebc->addr = val; 519 break; 520 case EBC0_CFGDATA: 521 switch (ebc->addr) { 522 case 0x00: /* B0CR */ 523 break; 524 case 0x01: /* B1CR */ 525 break; 526 case 0x02: /* B2CR */ 527 break; 528 case 0x03: /* B3CR */ 529 break; 530 case 0x04: /* B4CR */ 531 break; 532 case 0x05: /* B5CR */ 533 break; 534 case 0x06: /* B6CR */ 535 break; 536 case 0x07: /* B7CR */ 537 break; 538 case 0x10: /* B0AP */ 539 break; 540 case 0x11: /* B1AP */ 541 break; 542 case 0x12: /* B2AP */ 543 break; 544 case 0x13: /* B3AP */ 545 break; 546 case 0x14: /* B4AP */ 547 break; 548 case 0x15: /* B5AP */ 549 break; 550 case 0x16: /* B6AP */ 551 break; 552 case 0x17: /* B7AP */ 553 break; 554 case 0x20: /* BEAR */ 555 break; 556 case 0x21: /* BESR0 */ 557 break; 558 case 0x22: /* BESR1 */ 559 break; 560 case 0x23: /* CFG */ 561 break; 562 default: 563 break; 564 } 565 break; 566 default: 567 break; 568 } 569 } 570 571 static void ebc_reset (void *opaque) 572 { 573 ppc4xx_ebc_t *ebc; 574 int i; 575 576 ebc = opaque; 577 ebc->addr = 0x00000000; 578 ebc->bap[0] = 0x7F8FFE80; 579 ebc->bcr[0] = 0xFFE28000; 580 for (i = 0; i < 8; i++) { 581 ebc->bap[i] = 0x00000000; 582 ebc->bcr[i] = 0x00000000; 583 } 584 ebc->besr0 = 0x00000000; 585 ebc->besr1 = 0x00000000; 586 ebc->cfg = 0x80400000; 587 } 588 589 static void ppc405_ebc_init(CPUPPCState *env) 590 { 591 ppc4xx_ebc_t *ebc; 592 593 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 594 qemu_register_reset(&ebc_reset, ebc); 595 ppc_dcr_register(env, EBC0_CFGADDR, 596 ebc, &dcr_read_ebc, &dcr_write_ebc); 597 ppc_dcr_register(env, EBC0_CFGDATA, 598 ebc, &dcr_read_ebc, &dcr_write_ebc); 599 } 600 601 /*****************************************************************************/ 602 /* DMA controller */ 603 enum { 604 DMA0_CR0 = 0x100, 605 DMA0_CT0 = 0x101, 606 DMA0_DA0 = 0x102, 607 DMA0_SA0 = 0x103, 608 DMA0_SG0 = 0x104, 609 DMA0_CR1 = 0x108, 610 DMA0_CT1 = 0x109, 611 DMA0_DA1 = 0x10A, 612 DMA0_SA1 = 0x10B, 613 DMA0_SG1 = 0x10C, 614 DMA0_CR2 = 0x110, 615 DMA0_CT2 = 0x111, 616 DMA0_DA2 = 0x112, 617 DMA0_SA2 = 0x113, 618 DMA0_SG2 = 0x114, 619 DMA0_CR3 = 0x118, 620 DMA0_CT3 = 0x119, 621 DMA0_DA3 = 0x11A, 622 DMA0_SA3 = 0x11B, 623 DMA0_SG3 = 0x11C, 624 DMA0_SR = 0x120, 625 DMA0_SGC = 0x123, 626 DMA0_SLP = 0x125, 627 DMA0_POL = 0x126, 628 }; 629 630 typedef struct ppc405_dma_t ppc405_dma_t; 631 struct ppc405_dma_t { 632 qemu_irq irqs[4]; 633 uint32_t cr[4]; 634 uint32_t ct[4]; 635 uint32_t da[4]; 636 uint32_t sa[4]; 637 uint32_t sg[4]; 638 uint32_t sr; 639 uint32_t sgc; 640 uint32_t slp; 641 uint32_t pol; 642 }; 643 644 static uint32_t dcr_read_dma (void *opaque, int dcrn) 645 { 646 return 0; 647 } 648 649 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 650 { 651 } 652 653 static void ppc405_dma_reset (void *opaque) 654 { 655 ppc405_dma_t *dma; 656 int i; 657 658 dma = opaque; 659 for (i = 0; i < 4; i++) { 660 dma->cr[i] = 0x00000000; 661 dma->ct[i] = 0x00000000; 662 dma->da[i] = 0x00000000; 663 dma->sa[i] = 0x00000000; 664 dma->sg[i] = 0x00000000; 665 } 666 dma->sr = 0x00000000; 667 dma->sgc = 0x00000000; 668 dma->slp = 0x7C000000; 669 dma->pol = 0x00000000; 670 } 671 672 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 673 { 674 ppc405_dma_t *dma; 675 676 dma = g_malloc0(sizeof(ppc405_dma_t)); 677 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 678 qemu_register_reset(&ppc405_dma_reset, dma); 679 ppc_dcr_register(env, DMA0_CR0, 680 dma, &dcr_read_dma, &dcr_write_dma); 681 ppc_dcr_register(env, DMA0_CT0, 682 dma, &dcr_read_dma, &dcr_write_dma); 683 ppc_dcr_register(env, DMA0_DA0, 684 dma, &dcr_read_dma, &dcr_write_dma); 685 ppc_dcr_register(env, DMA0_SA0, 686 dma, &dcr_read_dma, &dcr_write_dma); 687 ppc_dcr_register(env, DMA0_SG0, 688 dma, &dcr_read_dma, &dcr_write_dma); 689 ppc_dcr_register(env, DMA0_CR1, 690 dma, &dcr_read_dma, &dcr_write_dma); 691 ppc_dcr_register(env, DMA0_CT1, 692 dma, &dcr_read_dma, &dcr_write_dma); 693 ppc_dcr_register(env, DMA0_DA1, 694 dma, &dcr_read_dma, &dcr_write_dma); 695 ppc_dcr_register(env, DMA0_SA1, 696 dma, &dcr_read_dma, &dcr_write_dma); 697 ppc_dcr_register(env, DMA0_SG1, 698 dma, &dcr_read_dma, &dcr_write_dma); 699 ppc_dcr_register(env, DMA0_CR2, 700 dma, &dcr_read_dma, &dcr_write_dma); 701 ppc_dcr_register(env, DMA0_CT2, 702 dma, &dcr_read_dma, &dcr_write_dma); 703 ppc_dcr_register(env, DMA0_DA2, 704 dma, &dcr_read_dma, &dcr_write_dma); 705 ppc_dcr_register(env, DMA0_SA2, 706 dma, &dcr_read_dma, &dcr_write_dma); 707 ppc_dcr_register(env, DMA0_SG2, 708 dma, &dcr_read_dma, &dcr_write_dma); 709 ppc_dcr_register(env, DMA0_CR3, 710 dma, &dcr_read_dma, &dcr_write_dma); 711 ppc_dcr_register(env, DMA0_CT3, 712 dma, &dcr_read_dma, &dcr_write_dma); 713 ppc_dcr_register(env, DMA0_DA3, 714 dma, &dcr_read_dma, &dcr_write_dma); 715 ppc_dcr_register(env, DMA0_SA3, 716 dma, &dcr_read_dma, &dcr_write_dma); 717 ppc_dcr_register(env, DMA0_SG3, 718 dma, &dcr_read_dma, &dcr_write_dma); 719 ppc_dcr_register(env, DMA0_SR, 720 dma, &dcr_read_dma, &dcr_write_dma); 721 ppc_dcr_register(env, DMA0_SGC, 722 dma, &dcr_read_dma, &dcr_write_dma); 723 ppc_dcr_register(env, DMA0_SLP, 724 dma, &dcr_read_dma, &dcr_write_dma); 725 ppc_dcr_register(env, DMA0_POL, 726 dma, &dcr_read_dma, &dcr_write_dma); 727 } 728 729 /*****************************************************************************/ 730 /* GPIO */ 731 typedef struct ppc405_gpio_t ppc405_gpio_t; 732 struct ppc405_gpio_t { 733 MemoryRegion io; 734 uint32_t or; 735 uint32_t tcr; 736 uint32_t osrh; 737 uint32_t osrl; 738 uint32_t tsrh; 739 uint32_t tsrl; 740 uint32_t odr; 741 uint32_t ir; 742 uint32_t rr1; 743 uint32_t isr1h; 744 uint32_t isr1l; 745 }; 746 747 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr) 748 { 749 #ifdef DEBUG_GPIO 750 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 751 #endif 752 753 return 0; 754 } 755 756 static void ppc405_gpio_writeb (void *opaque, 757 hwaddr addr, uint32_t value) 758 { 759 #ifdef DEBUG_GPIO 760 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 761 value); 762 #endif 763 } 764 765 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr) 766 { 767 #ifdef DEBUG_GPIO 768 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 769 #endif 770 771 return 0; 772 } 773 774 static void ppc405_gpio_writew (void *opaque, 775 hwaddr addr, uint32_t value) 776 { 777 #ifdef DEBUG_GPIO 778 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 779 value); 780 #endif 781 } 782 783 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr) 784 { 785 #ifdef DEBUG_GPIO 786 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 787 #endif 788 789 return 0; 790 } 791 792 static void ppc405_gpio_writel (void *opaque, 793 hwaddr addr, uint32_t value) 794 { 795 #ifdef DEBUG_GPIO 796 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 797 value); 798 #endif 799 } 800 801 static const MemoryRegionOps ppc405_gpio_ops = { 802 .old_mmio = { 803 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, 804 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, 805 }, 806 .endianness = DEVICE_NATIVE_ENDIAN, 807 }; 808 809 static void ppc405_gpio_reset (void *opaque) 810 { 811 } 812 813 static void ppc405_gpio_init(hwaddr base) 814 { 815 ppc405_gpio_t *gpio; 816 817 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 818 #ifdef DEBUG_GPIO 819 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 820 #endif 821 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 822 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 823 qemu_register_reset(&ppc405_gpio_reset, gpio); 824 } 825 826 /*****************************************************************************/ 827 /* On Chip Memory */ 828 enum { 829 OCM0_ISARC = 0x018, 830 OCM0_ISACNTL = 0x019, 831 OCM0_DSARC = 0x01A, 832 OCM0_DSACNTL = 0x01B, 833 }; 834 835 typedef struct ppc405_ocm_t ppc405_ocm_t; 836 struct ppc405_ocm_t { 837 MemoryRegion ram; 838 MemoryRegion isarc_ram; 839 MemoryRegion dsarc_ram; 840 uint32_t isarc; 841 uint32_t isacntl; 842 uint32_t dsarc; 843 uint32_t dsacntl; 844 }; 845 846 static void ocm_update_mappings (ppc405_ocm_t *ocm, 847 uint32_t isarc, uint32_t isacntl, 848 uint32_t dsarc, uint32_t dsacntl) 849 { 850 #ifdef DEBUG_OCM 851 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 852 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 853 " (%08" PRIx32 " %08" PRIx32 ")\n", 854 isarc, isacntl, dsarc, dsacntl, 855 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 856 #endif 857 if (ocm->isarc != isarc || 858 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 859 if (ocm->isacntl & 0x80000000) { 860 /* Unmap previously assigned memory region */ 861 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 862 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 863 } 864 if (isacntl & 0x80000000) { 865 /* Map new instruction memory region */ 866 #ifdef DEBUG_OCM 867 printf("OCM map ISA %08" PRIx32 "\n", isarc); 868 #endif 869 memory_region_add_subregion(get_system_memory(), isarc, 870 &ocm->isarc_ram); 871 } 872 } 873 if (ocm->dsarc != dsarc || 874 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 875 if (ocm->dsacntl & 0x80000000) { 876 /* Beware not to unmap the region we just mapped */ 877 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 878 /* Unmap previously assigned memory region */ 879 #ifdef DEBUG_OCM 880 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 881 #endif 882 memory_region_del_subregion(get_system_memory(), 883 &ocm->dsarc_ram); 884 } 885 } 886 if (dsacntl & 0x80000000) { 887 /* Beware not to remap the region we just mapped */ 888 if (!(isacntl & 0x80000000) || dsarc != isarc) { 889 /* Map new data memory region */ 890 #ifdef DEBUG_OCM 891 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 892 #endif 893 memory_region_add_subregion(get_system_memory(), dsarc, 894 &ocm->dsarc_ram); 895 } 896 } 897 } 898 } 899 900 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 901 { 902 ppc405_ocm_t *ocm; 903 uint32_t ret; 904 905 ocm = opaque; 906 switch (dcrn) { 907 case OCM0_ISARC: 908 ret = ocm->isarc; 909 break; 910 case OCM0_ISACNTL: 911 ret = ocm->isacntl; 912 break; 913 case OCM0_DSARC: 914 ret = ocm->dsarc; 915 break; 916 case OCM0_DSACNTL: 917 ret = ocm->dsacntl; 918 break; 919 default: 920 ret = 0; 921 break; 922 } 923 924 return ret; 925 } 926 927 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 928 { 929 ppc405_ocm_t *ocm; 930 uint32_t isarc, dsarc, isacntl, dsacntl; 931 932 ocm = opaque; 933 isarc = ocm->isarc; 934 dsarc = ocm->dsarc; 935 isacntl = ocm->isacntl; 936 dsacntl = ocm->dsacntl; 937 switch (dcrn) { 938 case OCM0_ISARC: 939 isarc = val & 0xFC000000; 940 break; 941 case OCM0_ISACNTL: 942 isacntl = val & 0xC0000000; 943 break; 944 case OCM0_DSARC: 945 isarc = val & 0xFC000000; 946 break; 947 case OCM0_DSACNTL: 948 isacntl = val & 0xC0000000; 949 break; 950 } 951 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 952 ocm->isarc = isarc; 953 ocm->dsarc = dsarc; 954 ocm->isacntl = isacntl; 955 ocm->dsacntl = dsacntl; 956 } 957 958 static void ocm_reset (void *opaque) 959 { 960 ppc405_ocm_t *ocm; 961 uint32_t isarc, dsarc, isacntl, dsacntl; 962 963 ocm = opaque; 964 isarc = 0x00000000; 965 isacntl = 0x00000000; 966 dsarc = 0x00000000; 967 dsacntl = 0x00000000; 968 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 969 ocm->isarc = isarc; 970 ocm->dsarc = dsarc; 971 ocm->isacntl = isacntl; 972 ocm->dsacntl = dsacntl; 973 } 974 975 static void ppc405_ocm_init(CPUPPCState *env) 976 { 977 ppc405_ocm_t *ocm; 978 979 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 980 /* XXX: Size is 4096 or 0x04000000 */ 981 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096, 982 &error_fatal); 983 vmstate_register_ram_global(&ocm->isarc_ram); 984 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram, 985 0, 4096); 986 qemu_register_reset(&ocm_reset, ocm); 987 ppc_dcr_register(env, OCM0_ISARC, 988 ocm, &dcr_read_ocm, &dcr_write_ocm); 989 ppc_dcr_register(env, OCM0_ISACNTL, 990 ocm, &dcr_read_ocm, &dcr_write_ocm); 991 ppc_dcr_register(env, OCM0_DSARC, 992 ocm, &dcr_read_ocm, &dcr_write_ocm); 993 ppc_dcr_register(env, OCM0_DSACNTL, 994 ocm, &dcr_read_ocm, &dcr_write_ocm); 995 } 996 997 /*****************************************************************************/ 998 /* I2C controller */ 999 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; 1000 struct ppc4xx_i2c_t { 1001 qemu_irq irq; 1002 MemoryRegion iomem; 1003 uint8_t mdata; 1004 uint8_t lmadr; 1005 uint8_t hmadr; 1006 uint8_t cntl; 1007 uint8_t mdcntl; 1008 uint8_t sts; 1009 uint8_t extsts; 1010 uint8_t sdata; 1011 uint8_t lsadr; 1012 uint8_t hsadr; 1013 uint8_t clkdiv; 1014 uint8_t intrmsk; 1015 uint8_t xfrcnt; 1016 uint8_t xtcntlss; 1017 uint8_t directcntl; 1018 }; 1019 1020 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr) 1021 { 1022 ppc4xx_i2c_t *i2c; 1023 uint32_t ret; 1024 1025 #ifdef DEBUG_I2C 1026 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1027 #endif 1028 i2c = opaque; 1029 switch (addr) { 1030 case 0x00: 1031 // i2c_readbyte(&i2c->mdata); 1032 ret = i2c->mdata; 1033 break; 1034 case 0x02: 1035 ret = i2c->sdata; 1036 break; 1037 case 0x04: 1038 ret = i2c->lmadr; 1039 break; 1040 case 0x05: 1041 ret = i2c->hmadr; 1042 break; 1043 case 0x06: 1044 ret = i2c->cntl; 1045 break; 1046 case 0x07: 1047 ret = i2c->mdcntl; 1048 break; 1049 case 0x08: 1050 ret = i2c->sts; 1051 break; 1052 case 0x09: 1053 ret = i2c->extsts; 1054 break; 1055 case 0x0A: 1056 ret = i2c->lsadr; 1057 break; 1058 case 0x0B: 1059 ret = i2c->hsadr; 1060 break; 1061 case 0x0C: 1062 ret = i2c->clkdiv; 1063 break; 1064 case 0x0D: 1065 ret = i2c->intrmsk; 1066 break; 1067 case 0x0E: 1068 ret = i2c->xfrcnt; 1069 break; 1070 case 0x0F: 1071 ret = i2c->xtcntlss; 1072 break; 1073 case 0x10: 1074 ret = i2c->directcntl; 1075 break; 1076 default: 1077 ret = 0x00; 1078 break; 1079 } 1080 #ifdef DEBUG_I2C 1081 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret); 1082 #endif 1083 1084 return ret; 1085 } 1086 1087 static void ppc4xx_i2c_writeb (void *opaque, 1088 hwaddr addr, uint32_t value) 1089 { 1090 ppc4xx_i2c_t *i2c; 1091 1092 #ifdef DEBUG_I2C 1093 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1094 value); 1095 #endif 1096 i2c = opaque; 1097 switch (addr) { 1098 case 0x00: 1099 i2c->mdata = value; 1100 // i2c_sendbyte(&i2c->mdata); 1101 break; 1102 case 0x02: 1103 i2c->sdata = value; 1104 break; 1105 case 0x04: 1106 i2c->lmadr = value; 1107 break; 1108 case 0x05: 1109 i2c->hmadr = value; 1110 break; 1111 case 0x06: 1112 i2c->cntl = value; 1113 break; 1114 case 0x07: 1115 i2c->mdcntl = value & 0xDF; 1116 break; 1117 case 0x08: 1118 i2c->sts &= ~(value & 0x0A); 1119 break; 1120 case 0x09: 1121 i2c->extsts &= ~(value & 0x8F); 1122 break; 1123 case 0x0A: 1124 i2c->lsadr = value; 1125 break; 1126 case 0x0B: 1127 i2c->hsadr = value; 1128 break; 1129 case 0x0C: 1130 i2c->clkdiv = value; 1131 break; 1132 case 0x0D: 1133 i2c->intrmsk = value; 1134 break; 1135 case 0x0E: 1136 i2c->xfrcnt = value & 0x77; 1137 break; 1138 case 0x0F: 1139 i2c->xtcntlss = value; 1140 break; 1141 case 0x10: 1142 i2c->directcntl = value & 0x7; 1143 break; 1144 } 1145 } 1146 1147 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr) 1148 { 1149 uint32_t ret; 1150 1151 #ifdef DEBUG_I2C 1152 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1153 #endif 1154 ret = ppc4xx_i2c_readb(opaque, addr) << 8; 1155 ret |= ppc4xx_i2c_readb(opaque, addr + 1); 1156 1157 return ret; 1158 } 1159 1160 static void ppc4xx_i2c_writew (void *opaque, 1161 hwaddr addr, uint32_t value) 1162 { 1163 #ifdef DEBUG_I2C 1164 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1165 value); 1166 #endif 1167 ppc4xx_i2c_writeb(opaque, addr, value >> 8); 1168 ppc4xx_i2c_writeb(opaque, addr + 1, value); 1169 } 1170 1171 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr) 1172 { 1173 uint32_t ret; 1174 1175 #ifdef DEBUG_I2C 1176 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1177 #endif 1178 ret = ppc4xx_i2c_readb(opaque, addr) << 24; 1179 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; 1180 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; 1181 ret |= ppc4xx_i2c_readb(opaque, addr + 3); 1182 1183 return ret; 1184 } 1185 1186 static void ppc4xx_i2c_writel (void *opaque, 1187 hwaddr addr, uint32_t value) 1188 { 1189 #ifdef DEBUG_I2C 1190 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1191 value); 1192 #endif 1193 ppc4xx_i2c_writeb(opaque, addr, value >> 24); 1194 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); 1195 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); 1196 ppc4xx_i2c_writeb(opaque, addr + 3, value); 1197 } 1198 1199 static const MemoryRegionOps i2c_ops = { 1200 .old_mmio = { 1201 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, }, 1202 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, }, 1203 }, 1204 .endianness = DEVICE_NATIVE_ENDIAN, 1205 }; 1206 1207 static void ppc4xx_i2c_reset (void *opaque) 1208 { 1209 ppc4xx_i2c_t *i2c; 1210 1211 i2c = opaque; 1212 i2c->mdata = 0x00; 1213 i2c->sdata = 0x00; 1214 i2c->cntl = 0x00; 1215 i2c->mdcntl = 0x00; 1216 i2c->sts = 0x00; 1217 i2c->extsts = 0x00; 1218 i2c->clkdiv = 0x00; 1219 i2c->xfrcnt = 0x00; 1220 i2c->directcntl = 0x0F; 1221 } 1222 1223 static void ppc405_i2c_init(hwaddr base, qemu_irq irq) 1224 { 1225 ppc4xx_i2c_t *i2c; 1226 1227 i2c = g_malloc0(sizeof(ppc4xx_i2c_t)); 1228 i2c->irq = irq; 1229 #ifdef DEBUG_I2C 1230 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1231 #endif 1232 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011); 1233 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem); 1234 qemu_register_reset(ppc4xx_i2c_reset, i2c); 1235 } 1236 1237 /*****************************************************************************/ 1238 /* General purpose timers */ 1239 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 1240 struct ppc4xx_gpt_t { 1241 MemoryRegion iomem; 1242 int64_t tb_offset; 1243 uint32_t tb_freq; 1244 QEMUTimer *timer; 1245 qemu_irq irqs[5]; 1246 uint32_t oe; 1247 uint32_t ol; 1248 uint32_t im; 1249 uint32_t is; 1250 uint32_t ie; 1251 uint32_t comp[5]; 1252 uint32_t mask[5]; 1253 }; 1254 1255 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr) 1256 { 1257 #ifdef DEBUG_GPT 1258 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1259 #endif 1260 /* XXX: generate a bus fault */ 1261 return -1; 1262 } 1263 1264 static void ppc4xx_gpt_writeb (void *opaque, 1265 hwaddr addr, uint32_t value) 1266 { 1267 #ifdef DEBUG_I2C 1268 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1269 value); 1270 #endif 1271 /* XXX: generate a bus fault */ 1272 } 1273 1274 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr) 1275 { 1276 #ifdef DEBUG_GPT 1277 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1278 #endif 1279 /* XXX: generate a bus fault */ 1280 return -1; 1281 } 1282 1283 static void ppc4xx_gpt_writew (void *opaque, 1284 hwaddr addr, uint32_t value) 1285 { 1286 #ifdef DEBUG_I2C 1287 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1288 value); 1289 #endif 1290 /* XXX: generate a bus fault */ 1291 } 1292 1293 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 1294 { 1295 /* XXX: TODO */ 1296 return 0; 1297 } 1298 1299 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 1300 { 1301 /* XXX: TODO */ 1302 } 1303 1304 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 1305 { 1306 uint32_t mask; 1307 int i; 1308 1309 mask = 0x80000000; 1310 for (i = 0; i < 5; i++) { 1311 if (gpt->oe & mask) { 1312 /* Output is enabled */ 1313 if (ppc4xx_gpt_compare(gpt, i)) { 1314 /* Comparison is OK */ 1315 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 1316 } else { 1317 /* Comparison is KO */ 1318 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 1319 } 1320 } 1321 mask = mask >> 1; 1322 } 1323 } 1324 1325 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 1326 { 1327 uint32_t mask; 1328 int i; 1329 1330 mask = 0x00008000; 1331 for (i = 0; i < 5; i++) { 1332 if (gpt->is & gpt->im & mask) 1333 qemu_irq_raise(gpt->irqs[i]); 1334 else 1335 qemu_irq_lower(gpt->irqs[i]); 1336 mask = mask >> 1; 1337 } 1338 } 1339 1340 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 1341 { 1342 /* XXX: TODO */ 1343 } 1344 1345 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) 1346 { 1347 ppc4xx_gpt_t *gpt; 1348 uint32_t ret; 1349 int idx; 1350 1351 #ifdef DEBUG_GPT 1352 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 1353 #endif 1354 gpt = opaque; 1355 switch (addr) { 1356 case 0x00: 1357 /* Time base counter */ 1358 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1359 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1360 break; 1361 case 0x10: 1362 /* Output enable */ 1363 ret = gpt->oe; 1364 break; 1365 case 0x14: 1366 /* Output level */ 1367 ret = gpt->ol; 1368 break; 1369 case 0x18: 1370 /* Interrupt mask */ 1371 ret = gpt->im; 1372 break; 1373 case 0x1C: 1374 case 0x20: 1375 /* Interrupt status */ 1376 ret = gpt->is; 1377 break; 1378 case 0x24: 1379 /* Interrupt enable */ 1380 ret = gpt->ie; 1381 break; 1382 case 0x80 ... 0x90: 1383 /* Compare timer */ 1384 idx = (addr - 0x80) >> 2; 1385 ret = gpt->comp[idx]; 1386 break; 1387 case 0xC0 ... 0xD0: 1388 /* Compare mask */ 1389 idx = (addr - 0xC0) >> 2; 1390 ret = gpt->mask[idx]; 1391 break; 1392 default: 1393 ret = -1; 1394 break; 1395 } 1396 1397 return ret; 1398 } 1399 1400 static void ppc4xx_gpt_writel (void *opaque, 1401 hwaddr addr, uint32_t value) 1402 { 1403 ppc4xx_gpt_t *gpt; 1404 int idx; 1405 1406 #ifdef DEBUG_I2C 1407 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1408 value); 1409 #endif 1410 gpt = opaque; 1411 switch (addr) { 1412 case 0x00: 1413 /* Time base counter */ 1414 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1415 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1416 ppc4xx_gpt_compute_timer(gpt); 1417 break; 1418 case 0x10: 1419 /* Output enable */ 1420 gpt->oe = value & 0xF8000000; 1421 ppc4xx_gpt_set_outputs(gpt); 1422 break; 1423 case 0x14: 1424 /* Output level */ 1425 gpt->ol = value & 0xF8000000; 1426 ppc4xx_gpt_set_outputs(gpt); 1427 break; 1428 case 0x18: 1429 /* Interrupt mask */ 1430 gpt->im = value & 0x0000F800; 1431 break; 1432 case 0x1C: 1433 /* Interrupt status set */ 1434 gpt->is |= value & 0x0000F800; 1435 ppc4xx_gpt_set_irqs(gpt); 1436 break; 1437 case 0x20: 1438 /* Interrupt status clear */ 1439 gpt->is &= ~(value & 0x0000F800); 1440 ppc4xx_gpt_set_irqs(gpt); 1441 break; 1442 case 0x24: 1443 /* Interrupt enable */ 1444 gpt->ie = value & 0x0000F800; 1445 ppc4xx_gpt_set_irqs(gpt); 1446 break; 1447 case 0x80 ... 0x90: 1448 /* Compare timer */ 1449 idx = (addr - 0x80) >> 2; 1450 gpt->comp[idx] = value & 0xF8000000; 1451 ppc4xx_gpt_compute_timer(gpt); 1452 break; 1453 case 0xC0 ... 0xD0: 1454 /* Compare mask */ 1455 idx = (addr - 0xC0) >> 2; 1456 gpt->mask[idx] = value & 0xF8000000; 1457 ppc4xx_gpt_compute_timer(gpt); 1458 break; 1459 } 1460 } 1461 1462 static const MemoryRegionOps gpt_ops = { 1463 .old_mmio = { 1464 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, 1465 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, 1466 }, 1467 .endianness = DEVICE_NATIVE_ENDIAN, 1468 }; 1469 1470 static void ppc4xx_gpt_cb (void *opaque) 1471 { 1472 ppc4xx_gpt_t *gpt; 1473 1474 gpt = opaque; 1475 ppc4xx_gpt_set_irqs(gpt); 1476 ppc4xx_gpt_set_outputs(gpt); 1477 ppc4xx_gpt_compute_timer(gpt); 1478 } 1479 1480 static void ppc4xx_gpt_reset (void *opaque) 1481 { 1482 ppc4xx_gpt_t *gpt; 1483 int i; 1484 1485 gpt = opaque; 1486 timer_del(gpt->timer); 1487 gpt->oe = 0x00000000; 1488 gpt->ol = 0x00000000; 1489 gpt->im = 0x00000000; 1490 gpt->is = 0x00000000; 1491 gpt->ie = 0x00000000; 1492 for (i = 0; i < 5; i++) { 1493 gpt->comp[i] = 0x00000000; 1494 gpt->mask[i] = 0x00000000; 1495 } 1496 } 1497 1498 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1499 { 1500 ppc4xx_gpt_t *gpt; 1501 int i; 1502 1503 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1504 for (i = 0; i < 5; i++) { 1505 gpt->irqs[i] = irqs[i]; 1506 } 1507 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1508 #ifdef DEBUG_GPT 1509 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1510 #endif 1511 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1512 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1513 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1514 } 1515 1516 /*****************************************************************************/ 1517 /* MAL */ 1518 enum { 1519 MAL0_CFG = 0x180, 1520 MAL0_ESR = 0x181, 1521 MAL0_IER = 0x182, 1522 MAL0_TXCASR = 0x184, 1523 MAL0_TXCARR = 0x185, 1524 MAL0_TXEOBISR = 0x186, 1525 MAL0_TXDEIR = 0x187, 1526 MAL0_RXCASR = 0x190, 1527 MAL0_RXCARR = 0x191, 1528 MAL0_RXEOBISR = 0x192, 1529 MAL0_RXDEIR = 0x193, 1530 MAL0_TXCTP0R = 0x1A0, 1531 MAL0_TXCTP1R = 0x1A1, 1532 MAL0_TXCTP2R = 0x1A2, 1533 MAL0_TXCTP3R = 0x1A3, 1534 MAL0_RXCTP0R = 0x1C0, 1535 MAL0_RXCTP1R = 0x1C1, 1536 MAL0_RCBS0 = 0x1E0, 1537 MAL0_RCBS1 = 0x1E1, 1538 }; 1539 1540 typedef struct ppc40x_mal_t ppc40x_mal_t; 1541 struct ppc40x_mal_t { 1542 qemu_irq irqs[4]; 1543 uint32_t cfg; 1544 uint32_t esr; 1545 uint32_t ier; 1546 uint32_t txcasr; 1547 uint32_t txcarr; 1548 uint32_t txeobisr; 1549 uint32_t txdeir; 1550 uint32_t rxcasr; 1551 uint32_t rxcarr; 1552 uint32_t rxeobisr; 1553 uint32_t rxdeir; 1554 uint32_t txctpr[4]; 1555 uint32_t rxctpr[2]; 1556 uint32_t rcbs[2]; 1557 }; 1558 1559 static void ppc40x_mal_reset (void *opaque); 1560 1561 static uint32_t dcr_read_mal (void *opaque, int dcrn) 1562 { 1563 ppc40x_mal_t *mal; 1564 uint32_t ret; 1565 1566 mal = opaque; 1567 switch (dcrn) { 1568 case MAL0_CFG: 1569 ret = mal->cfg; 1570 break; 1571 case MAL0_ESR: 1572 ret = mal->esr; 1573 break; 1574 case MAL0_IER: 1575 ret = mal->ier; 1576 break; 1577 case MAL0_TXCASR: 1578 ret = mal->txcasr; 1579 break; 1580 case MAL0_TXCARR: 1581 ret = mal->txcarr; 1582 break; 1583 case MAL0_TXEOBISR: 1584 ret = mal->txeobisr; 1585 break; 1586 case MAL0_TXDEIR: 1587 ret = mal->txdeir; 1588 break; 1589 case MAL0_RXCASR: 1590 ret = mal->rxcasr; 1591 break; 1592 case MAL0_RXCARR: 1593 ret = mal->rxcarr; 1594 break; 1595 case MAL0_RXEOBISR: 1596 ret = mal->rxeobisr; 1597 break; 1598 case MAL0_RXDEIR: 1599 ret = mal->rxdeir; 1600 break; 1601 case MAL0_TXCTP0R: 1602 ret = mal->txctpr[0]; 1603 break; 1604 case MAL0_TXCTP1R: 1605 ret = mal->txctpr[1]; 1606 break; 1607 case MAL0_TXCTP2R: 1608 ret = mal->txctpr[2]; 1609 break; 1610 case MAL0_TXCTP3R: 1611 ret = mal->txctpr[3]; 1612 break; 1613 case MAL0_RXCTP0R: 1614 ret = mal->rxctpr[0]; 1615 break; 1616 case MAL0_RXCTP1R: 1617 ret = mal->rxctpr[1]; 1618 break; 1619 case MAL0_RCBS0: 1620 ret = mal->rcbs[0]; 1621 break; 1622 case MAL0_RCBS1: 1623 ret = mal->rcbs[1]; 1624 break; 1625 default: 1626 ret = 0; 1627 break; 1628 } 1629 1630 return ret; 1631 } 1632 1633 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val) 1634 { 1635 ppc40x_mal_t *mal; 1636 int idx; 1637 1638 mal = opaque; 1639 switch (dcrn) { 1640 case MAL0_CFG: 1641 if (val & 0x80000000) 1642 ppc40x_mal_reset(mal); 1643 mal->cfg = val & 0x00FFC087; 1644 break; 1645 case MAL0_ESR: 1646 /* Read/clear */ 1647 mal->esr &= ~val; 1648 break; 1649 case MAL0_IER: 1650 mal->ier = val & 0x0000001F; 1651 break; 1652 case MAL0_TXCASR: 1653 mal->txcasr = val & 0xF0000000; 1654 break; 1655 case MAL0_TXCARR: 1656 mal->txcarr = val & 0xF0000000; 1657 break; 1658 case MAL0_TXEOBISR: 1659 /* Read/clear */ 1660 mal->txeobisr &= ~val; 1661 break; 1662 case MAL0_TXDEIR: 1663 /* Read/clear */ 1664 mal->txdeir &= ~val; 1665 break; 1666 case MAL0_RXCASR: 1667 mal->rxcasr = val & 0xC0000000; 1668 break; 1669 case MAL0_RXCARR: 1670 mal->rxcarr = val & 0xC0000000; 1671 break; 1672 case MAL0_RXEOBISR: 1673 /* Read/clear */ 1674 mal->rxeobisr &= ~val; 1675 break; 1676 case MAL0_RXDEIR: 1677 /* Read/clear */ 1678 mal->rxdeir &= ~val; 1679 break; 1680 case MAL0_TXCTP0R: 1681 idx = 0; 1682 goto update_tx_ptr; 1683 case MAL0_TXCTP1R: 1684 idx = 1; 1685 goto update_tx_ptr; 1686 case MAL0_TXCTP2R: 1687 idx = 2; 1688 goto update_tx_ptr; 1689 case MAL0_TXCTP3R: 1690 idx = 3; 1691 update_tx_ptr: 1692 mal->txctpr[idx] = val; 1693 break; 1694 case MAL0_RXCTP0R: 1695 idx = 0; 1696 goto update_rx_ptr; 1697 case MAL0_RXCTP1R: 1698 idx = 1; 1699 update_rx_ptr: 1700 mal->rxctpr[idx] = val; 1701 break; 1702 case MAL0_RCBS0: 1703 idx = 0; 1704 goto update_rx_size; 1705 case MAL0_RCBS1: 1706 idx = 1; 1707 update_rx_size: 1708 mal->rcbs[idx] = val & 0x000000FF; 1709 break; 1710 } 1711 } 1712 1713 static void ppc40x_mal_reset (void *opaque) 1714 { 1715 ppc40x_mal_t *mal; 1716 1717 mal = opaque; 1718 mal->cfg = 0x0007C000; 1719 mal->esr = 0x00000000; 1720 mal->ier = 0x00000000; 1721 mal->rxcasr = 0x00000000; 1722 mal->rxdeir = 0x00000000; 1723 mal->rxeobisr = 0x00000000; 1724 mal->txcasr = 0x00000000; 1725 mal->txdeir = 0x00000000; 1726 mal->txeobisr = 0x00000000; 1727 } 1728 1729 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) 1730 { 1731 ppc40x_mal_t *mal; 1732 int i; 1733 1734 mal = g_malloc0(sizeof(ppc40x_mal_t)); 1735 for (i = 0; i < 4; i++) 1736 mal->irqs[i] = irqs[i]; 1737 qemu_register_reset(&ppc40x_mal_reset, mal); 1738 ppc_dcr_register(env, MAL0_CFG, 1739 mal, &dcr_read_mal, &dcr_write_mal); 1740 ppc_dcr_register(env, MAL0_ESR, 1741 mal, &dcr_read_mal, &dcr_write_mal); 1742 ppc_dcr_register(env, MAL0_IER, 1743 mal, &dcr_read_mal, &dcr_write_mal); 1744 ppc_dcr_register(env, MAL0_TXCASR, 1745 mal, &dcr_read_mal, &dcr_write_mal); 1746 ppc_dcr_register(env, MAL0_TXCARR, 1747 mal, &dcr_read_mal, &dcr_write_mal); 1748 ppc_dcr_register(env, MAL0_TXEOBISR, 1749 mal, &dcr_read_mal, &dcr_write_mal); 1750 ppc_dcr_register(env, MAL0_TXDEIR, 1751 mal, &dcr_read_mal, &dcr_write_mal); 1752 ppc_dcr_register(env, MAL0_RXCASR, 1753 mal, &dcr_read_mal, &dcr_write_mal); 1754 ppc_dcr_register(env, MAL0_RXCARR, 1755 mal, &dcr_read_mal, &dcr_write_mal); 1756 ppc_dcr_register(env, MAL0_RXEOBISR, 1757 mal, &dcr_read_mal, &dcr_write_mal); 1758 ppc_dcr_register(env, MAL0_RXDEIR, 1759 mal, &dcr_read_mal, &dcr_write_mal); 1760 ppc_dcr_register(env, MAL0_TXCTP0R, 1761 mal, &dcr_read_mal, &dcr_write_mal); 1762 ppc_dcr_register(env, MAL0_TXCTP1R, 1763 mal, &dcr_read_mal, &dcr_write_mal); 1764 ppc_dcr_register(env, MAL0_TXCTP2R, 1765 mal, &dcr_read_mal, &dcr_write_mal); 1766 ppc_dcr_register(env, MAL0_TXCTP3R, 1767 mal, &dcr_read_mal, &dcr_write_mal); 1768 ppc_dcr_register(env, MAL0_RXCTP0R, 1769 mal, &dcr_read_mal, &dcr_write_mal); 1770 ppc_dcr_register(env, MAL0_RXCTP1R, 1771 mal, &dcr_read_mal, &dcr_write_mal); 1772 ppc_dcr_register(env, MAL0_RCBS0, 1773 mal, &dcr_read_mal, &dcr_write_mal); 1774 ppc_dcr_register(env, MAL0_RCBS1, 1775 mal, &dcr_read_mal, &dcr_write_mal); 1776 } 1777 1778 /*****************************************************************************/ 1779 /* SPR */ 1780 void ppc40x_core_reset(PowerPCCPU *cpu) 1781 { 1782 CPUPPCState *env = &cpu->env; 1783 target_ulong dbsr; 1784 1785 printf("Reset PowerPC core\n"); 1786 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 1787 dbsr = env->spr[SPR_40x_DBSR]; 1788 dbsr &= ~0x00000300; 1789 dbsr |= 0x00000100; 1790 env->spr[SPR_40x_DBSR] = dbsr; 1791 } 1792 1793 void ppc40x_chip_reset(PowerPCCPU *cpu) 1794 { 1795 CPUPPCState *env = &cpu->env; 1796 target_ulong dbsr; 1797 1798 printf("Reset PowerPC chip\n"); 1799 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 1800 /* XXX: TODO reset all internal peripherals */ 1801 dbsr = env->spr[SPR_40x_DBSR]; 1802 dbsr &= ~0x00000300; 1803 dbsr |= 0x00000200; 1804 env->spr[SPR_40x_DBSR] = dbsr; 1805 } 1806 1807 void ppc40x_system_reset(PowerPCCPU *cpu) 1808 { 1809 printf("Reset PowerPC system\n"); 1810 qemu_system_reset_request(); 1811 } 1812 1813 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) 1814 { 1815 PowerPCCPU *cpu = ppc_env_get_cpu(env); 1816 1817 switch ((val >> 28) & 0x3) { 1818 case 0x0: 1819 /* No action */ 1820 break; 1821 case 0x1: 1822 /* Core reset */ 1823 ppc40x_core_reset(cpu); 1824 break; 1825 case 0x2: 1826 /* Chip reset */ 1827 ppc40x_chip_reset(cpu); 1828 break; 1829 case 0x3: 1830 /* System reset */ 1831 ppc40x_system_reset(cpu); 1832 break; 1833 } 1834 } 1835 1836 /*****************************************************************************/ 1837 /* PowerPC 405CR */ 1838 enum { 1839 PPC405CR_CPC0_PLLMR = 0x0B0, 1840 PPC405CR_CPC0_CR0 = 0x0B1, 1841 PPC405CR_CPC0_CR1 = 0x0B2, 1842 PPC405CR_CPC0_PSR = 0x0B4, 1843 PPC405CR_CPC0_JTAGID = 0x0B5, 1844 PPC405CR_CPC0_ER = 0x0B9, 1845 PPC405CR_CPC0_FR = 0x0BA, 1846 PPC405CR_CPC0_SR = 0x0BB, 1847 }; 1848 1849 enum { 1850 PPC405CR_CPU_CLK = 0, 1851 PPC405CR_TMR_CLK = 1, 1852 PPC405CR_PLB_CLK = 2, 1853 PPC405CR_SDRAM_CLK = 3, 1854 PPC405CR_OPB_CLK = 4, 1855 PPC405CR_EXT_CLK = 5, 1856 PPC405CR_UART_CLK = 6, 1857 PPC405CR_CLK_NB = 7, 1858 }; 1859 1860 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; 1861 struct ppc405cr_cpc_t { 1862 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 1863 uint32_t sysclk; 1864 uint32_t psr; 1865 uint32_t cr0; 1866 uint32_t cr1; 1867 uint32_t jtagid; 1868 uint32_t pllmr; 1869 uint32_t er; 1870 uint32_t fr; 1871 }; 1872 1873 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) 1874 { 1875 uint64_t VCO_out, PLL_out; 1876 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; 1877 int M, D0, D1, D2; 1878 1879 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ 1880 if (cpc->pllmr & 0x80000000) { 1881 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ 1882 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ 1883 M = D0 * D1 * D2; 1884 VCO_out = cpc->sysclk * M; 1885 if (VCO_out < 400000000 || VCO_out > 800000000) { 1886 /* PLL cannot lock */ 1887 cpc->pllmr &= ~0x80000000; 1888 goto bypass_pll; 1889 } 1890 PLL_out = VCO_out / D2; 1891 } else { 1892 /* Bypass PLL */ 1893 bypass_pll: 1894 M = D0; 1895 PLL_out = cpc->sysclk * M; 1896 } 1897 CPU_clk = PLL_out; 1898 if (cpc->cr1 & 0x00800000) 1899 TMR_clk = cpc->sysclk; /* Should have a separate clock */ 1900 else 1901 TMR_clk = CPU_clk; 1902 PLB_clk = CPU_clk / D0; 1903 SDRAM_clk = PLB_clk; 1904 D0 = ((cpc->pllmr >> 10) & 0x3) + 1; 1905 OPB_clk = PLB_clk / D0; 1906 D0 = ((cpc->pllmr >> 24) & 0x3) + 2; 1907 EXT_clk = PLB_clk / D0; 1908 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; 1909 UART_clk = CPU_clk / D0; 1910 /* Setup CPU clocks */ 1911 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); 1912 /* Setup time-base clock */ 1913 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); 1914 /* Setup PLB clock */ 1915 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); 1916 /* Setup SDRAM clock */ 1917 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); 1918 /* Setup OPB clock */ 1919 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); 1920 /* Setup external clock */ 1921 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); 1922 /* Setup UART clock */ 1923 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); 1924 } 1925 1926 static uint32_t dcr_read_crcpc (void *opaque, int dcrn) 1927 { 1928 ppc405cr_cpc_t *cpc; 1929 uint32_t ret; 1930 1931 cpc = opaque; 1932 switch (dcrn) { 1933 case PPC405CR_CPC0_PLLMR: 1934 ret = cpc->pllmr; 1935 break; 1936 case PPC405CR_CPC0_CR0: 1937 ret = cpc->cr0; 1938 break; 1939 case PPC405CR_CPC0_CR1: 1940 ret = cpc->cr1; 1941 break; 1942 case PPC405CR_CPC0_PSR: 1943 ret = cpc->psr; 1944 break; 1945 case PPC405CR_CPC0_JTAGID: 1946 ret = cpc->jtagid; 1947 break; 1948 case PPC405CR_CPC0_ER: 1949 ret = cpc->er; 1950 break; 1951 case PPC405CR_CPC0_FR: 1952 ret = cpc->fr; 1953 break; 1954 case PPC405CR_CPC0_SR: 1955 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; 1956 break; 1957 default: 1958 /* Avoid gcc warning */ 1959 ret = 0; 1960 break; 1961 } 1962 1963 return ret; 1964 } 1965 1966 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) 1967 { 1968 ppc405cr_cpc_t *cpc; 1969 1970 cpc = opaque; 1971 switch (dcrn) { 1972 case PPC405CR_CPC0_PLLMR: 1973 cpc->pllmr = val & 0xFFF77C3F; 1974 break; 1975 case PPC405CR_CPC0_CR0: 1976 cpc->cr0 = val & 0x0FFFFFFE; 1977 break; 1978 case PPC405CR_CPC0_CR1: 1979 cpc->cr1 = val & 0x00800000; 1980 break; 1981 case PPC405CR_CPC0_PSR: 1982 /* Read-only */ 1983 break; 1984 case PPC405CR_CPC0_JTAGID: 1985 /* Read-only */ 1986 break; 1987 case PPC405CR_CPC0_ER: 1988 cpc->er = val & 0xBFFC0000; 1989 break; 1990 case PPC405CR_CPC0_FR: 1991 cpc->fr = val & 0xBFFC0000; 1992 break; 1993 case PPC405CR_CPC0_SR: 1994 /* Read-only */ 1995 break; 1996 } 1997 } 1998 1999 static void ppc405cr_cpc_reset (void *opaque) 2000 { 2001 ppc405cr_cpc_t *cpc; 2002 int D; 2003 2004 cpc = opaque; 2005 /* Compute PLLMR value from PSR settings */ 2006 cpc->pllmr = 0x80000000; 2007 /* PFWD */ 2008 switch ((cpc->psr >> 30) & 3) { 2009 case 0: 2010 /* Bypass */ 2011 cpc->pllmr &= ~0x80000000; 2012 break; 2013 case 1: 2014 /* Divide by 3 */ 2015 cpc->pllmr |= 5 << 16; 2016 break; 2017 case 2: 2018 /* Divide by 4 */ 2019 cpc->pllmr |= 4 << 16; 2020 break; 2021 case 3: 2022 /* Divide by 6 */ 2023 cpc->pllmr |= 2 << 16; 2024 break; 2025 } 2026 /* PFBD */ 2027 D = (cpc->psr >> 28) & 3; 2028 cpc->pllmr |= (D + 1) << 20; 2029 /* PT */ 2030 D = (cpc->psr >> 25) & 7; 2031 switch (D) { 2032 case 0x2: 2033 cpc->pllmr |= 0x13; 2034 break; 2035 case 0x4: 2036 cpc->pllmr |= 0x15; 2037 break; 2038 case 0x5: 2039 cpc->pllmr |= 0x16; 2040 break; 2041 default: 2042 break; 2043 } 2044 /* PDC */ 2045 D = (cpc->psr >> 23) & 3; 2046 cpc->pllmr |= D << 26; 2047 /* ODP */ 2048 D = (cpc->psr >> 21) & 3; 2049 cpc->pllmr |= D << 10; 2050 /* EBPD */ 2051 D = (cpc->psr >> 17) & 3; 2052 cpc->pllmr |= D << 24; 2053 cpc->cr0 = 0x0000003C; 2054 cpc->cr1 = 0x2B0D8800; 2055 cpc->er = 0x00000000; 2056 cpc->fr = 0x00000000; 2057 ppc405cr_clk_setup(cpc); 2058 } 2059 2060 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) 2061 { 2062 int D; 2063 2064 /* XXX: this should be read from IO pins */ 2065 cpc->psr = 0x00000000; /* 8 bits ROM */ 2066 /* PFWD */ 2067 D = 0x2; /* Divide by 4 */ 2068 cpc->psr |= D << 30; 2069 /* PFBD */ 2070 D = 0x1; /* Divide by 2 */ 2071 cpc->psr |= D << 28; 2072 /* PDC */ 2073 D = 0x1; /* Divide by 2 */ 2074 cpc->psr |= D << 23; 2075 /* PT */ 2076 D = 0x5; /* M = 16 */ 2077 cpc->psr |= D << 25; 2078 /* ODP */ 2079 D = 0x1; /* Divide by 2 */ 2080 cpc->psr |= D << 21; 2081 /* EBDP */ 2082 D = 0x2; /* Divide by 4 */ 2083 cpc->psr |= D << 17; 2084 } 2085 2086 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], 2087 uint32_t sysclk) 2088 { 2089 ppc405cr_cpc_t *cpc; 2090 2091 cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); 2092 memcpy(cpc->clk_setup, clk_setup, 2093 PPC405CR_CLK_NB * sizeof(clk_setup_t)); 2094 cpc->sysclk = sysclk; 2095 cpc->jtagid = 0x42051049; 2096 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, 2097 &dcr_read_crcpc, &dcr_write_crcpc); 2098 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, 2099 &dcr_read_crcpc, &dcr_write_crcpc); 2100 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, 2101 &dcr_read_crcpc, &dcr_write_crcpc); 2102 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, 2103 &dcr_read_crcpc, &dcr_write_crcpc); 2104 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, 2105 &dcr_read_crcpc, &dcr_write_crcpc); 2106 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, 2107 &dcr_read_crcpc, &dcr_write_crcpc); 2108 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, 2109 &dcr_read_crcpc, &dcr_write_crcpc); 2110 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, 2111 &dcr_read_crcpc, &dcr_write_crcpc); 2112 ppc405cr_clk_init(cpc); 2113 qemu_register_reset(ppc405cr_cpc_reset, cpc); 2114 } 2115 2116 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, 2117 MemoryRegion ram_memories[4], 2118 hwaddr ram_bases[4], 2119 hwaddr ram_sizes[4], 2120 uint32_t sysclk, qemu_irq **picp, 2121 int do_init) 2122 { 2123 clk_setup_t clk_setup[PPC405CR_CLK_NB]; 2124 qemu_irq dma_irqs[4]; 2125 PowerPCCPU *cpu; 2126 CPUPPCState *env; 2127 qemu_irq *pic, *irqs; 2128 2129 memset(clk_setup, 0, sizeof(clk_setup)); 2130 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK], 2131 &clk_setup[PPC405CR_TMR_CLK], sysclk); 2132 env = &cpu->env; 2133 /* Memory mapped devices registers */ 2134 /* PLB arbitrer */ 2135 ppc4xx_plb_init(env); 2136 /* PLB to OPB bridge */ 2137 ppc4xx_pob_init(env); 2138 /* OBP arbitrer */ 2139 ppc4xx_opba_init(0xef600600); 2140 /* Universal interrupt controller */ 2141 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); 2142 irqs[PPCUIC_OUTPUT_INT] = 2143 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 2144 irqs[PPCUIC_OUTPUT_CINT] = 2145 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 2146 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 2147 *picp = pic; 2148 /* SDRAM controller */ 2149 ppc4xx_sdram_init(env, pic[14], 1, ram_memories, 2150 ram_bases, ram_sizes, do_init); 2151 /* External bus controller */ 2152 ppc405_ebc_init(env); 2153 /* DMA controller */ 2154 dma_irqs[0] = pic[26]; 2155 dma_irqs[1] = pic[25]; 2156 dma_irqs[2] = pic[24]; 2157 dma_irqs[3] = pic[23]; 2158 ppc405_dma_init(env, dma_irqs); 2159 /* Serial ports */ 2160 if (serial_hds[0] != NULL) { 2161 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 2162 PPC_SERIAL_MM_BAUDBASE, serial_hds[0], 2163 DEVICE_BIG_ENDIAN); 2164 } 2165 if (serial_hds[1] != NULL) { 2166 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 2167 PPC_SERIAL_MM_BAUDBASE, serial_hds[1], 2168 DEVICE_BIG_ENDIAN); 2169 } 2170 /* IIC controller */ 2171 ppc405_i2c_init(0xef600500, pic[2]); 2172 /* GPIO */ 2173 ppc405_gpio_init(0xef600700); 2174 /* CPU control */ 2175 ppc405cr_cpc_init(env, clk_setup, sysclk); 2176 2177 return env; 2178 } 2179 2180 /*****************************************************************************/ 2181 /* PowerPC 405EP */ 2182 /* CPU control */ 2183 enum { 2184 PPC405EP_CPC0_PLLMR0 = 0x0F0, 2185 PPC405EP_CPC0_BOOT = 0x0F1, 2186 PPC405EP_CPC0_EPCTL = 0x0F3, 2187 PPC405EP_CPC0_PLLMR1 = 0x0F4, 2188 PPC405EP_CPC0_UCR = 0x0F5, 2189 PPC405EP_CPC0_SRR = 0x0F6, 2190 PPC405EP_CPC0_JTAGID = 0x0F7, 2191 PPC405EP_CPC0_PCI = 0x0F9, 2192 #if 0 2193 PPC405EP_CPC0_ER = xxx, 2194 PPC405EP_CPC0_FR = xxx, 2195 PPC405EP_CPC0_SR = xxx, 2196 #endif 2197 }; 2198 2199 enum { 2200 PPC405EP_CPU_CLK = 0, 2201 PPC405EP_PLB_CLK = 1, 2202 PPC405EP_OPB_CLK = 2, 2203 PPC405EP_EBC_CLK = 3, 2204 PPC405EP_MAL_CLK = 4, 2205 PPC405EP_PCI_CLK = 5, 2206 PPC405EP_UART0_CLK = 6, 2207 PPC405EP_UART1_CLK = 7, 2208 PPC405EP_CLK_NB = 8, 2209 }; 2210 2211 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 2212 struct ppc405ep_cpc_t { 2213 uint32_t sysclk; 2214 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 2215 uint32_t boot; 2216 uint32_t epctl; 2217 uint32_t pllmr[2]; 2218 uint32_t ucr; 2219 uint32_t srr; 2220 uint32_t jtagid; 2221 uint32_t pci; 2222 /* Clock and power management */ 2223 uint32_t er; 2224 uint32_t fr; 2225 uint32_t sr; 2226 }; 2227 2228 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 2229 { 2230 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 2231 uint32_t UART0_clk, UART1_clk; 2232 uint64_t VCO_out, PLL_out; 2233 int M, D; 2234 2235 VCO_out = 0; 2236 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 2237 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 2238 #ifdef DEBUG_CLOCKS_LL 2239 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 2240 #endif 2241 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 2242 #ifdef DEBUG_CLOCKS_LL 2243 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 2244 #endif 2245 VCO_out = cpc->sysclk * M * D; 2246 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 2247 /* Error - unlock the PLL */ 2248 printf("VCO out of range %" PRIu64 "\n", VCO_out); 2249 #if 0 2250 cpc->pllmr[1] &= ~0x80000000; 2251 goto pll_bypass; 2252 #endif 2253 } 2254 PLL_out = VCO_out / D; 2255 /* Pretend the PLL is locked */ 2256 cpc->boot |= 0x00000001; 2257 } else { 2258 #if 0 2259 pll_bypass: 2260 #endif 2261 PLL_out = cpc->sysclk; 2262 if (cpc->pllmr[1] & 0x40000000) { 2263 /* Pretend the PLL is not locked */ 2264 cpc->boot &= ~0x00000001; 2265 } 2266 } 2267 /* Now, compute all other clocks */ 2268 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 2269 #ifdef DEBUG_CLOCKS_LL 2270 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 2271 #endif 2272 CPU_clk = PLL_out / D; 2273 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 2274 #ifdef DEBUG_CLOCKS_LL 2275 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 2276 #endif 2277 PLB_clk = CPU_clk / D; 2278 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 2279 #ifdef DEBUG_CLOCKS_LL 2280 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 2281 #endif 2282 OPB_clk = PLB_clk / D; 2283 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 2284 #ifdef DEBUG_CLOCKS_LL 2285 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 2286 #endif 2287 EBC_clk = PLB_clk / D; 2288 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 2289 #ifdef DEBUG_CLOCKS_LL 2290 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 2291 #endif 2292 MAL_clk = PLB_clk / D; 2293 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 2294 #ifdef DEBUG_CLOCKS_LL 2295 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 2296 #endif 2297 PCI_clk = PLB_clk / D; 2298 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 2299 #ifdef DEBUG_CLOCKS_LL 2300 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 2301 #endif 2302 UART0_clk = PLL_out / D; 2303 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 2304 #ifdef DEBUG_CLOCKS_LL 2305 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 2306 #endif 2307 UART1_clk = PLL_out / D; 2308 #ifdef DEBUG_CLOCKS 2309 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 2310 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 2311 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 2312 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 2313 " UART1 %" PRIu32 "\n", 2314 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 2315 UART0_clk, UART1_clk); 2316 #endif 2317 /* Setup CPU clocks */ 2318 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 2319 /* Setup PLB clock */ 2320 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 2321 /* Setup OPB clock */ 2322 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 2323 /* Setup external clock */ 2324 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 2325 /* Setup MAL clock */ 2326 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 2327 /* Setup PCI clock */ 2328 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 2329 /* Setup UART0 clock */ 2330 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 2331 /* Setup UART1 clock */ 2332 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 2333 } 2334 2335 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 2336 { 2337 ppc405ep_cpc_t *cpc; 2338 uint32_t ret; 2339 2340 cpc = opaque; 2341 switch (dcrn) { 2342 case PPC405EP_CPC0_BOOT: 2343 ret = cpc->boot; 2344 break; 2345 case PPC405EP_CPC0_EPCTL: 2346 ret = cpc->epctl; 2347 break; 2348 case PPC405EP_CPC0_PLLMR0: 2349 ret = cpc->pllmr[0]; 2350 break; 2351 case PPC405EP_CPC0_PLLMR1: 2352 ret = cpc->pllmr[1]; 2353 break; 2354 case PPC405EP_CPC0_UCR: 2355 ret = cpc->ucr; 2356 break; 2357 case PPC405EP_CPC0_SRR: 2358 ret = cpc->srr; 2359 break; 2360 case PPC405EP_CPC0_JTAGID: 2361 ret = cpc->jtagid; 2362 break; 2363 case PPC405EP_CPC0_PCI: 2364 ret = cpc->pci; 2365 break; 2366 default: 2367 /* Avoid gcc warning */ 2368 ret = 0; 2369 break; 2370 } 2371 2372 return ret; 2373 } 2374 2375 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 2376 { 2377 ppc405ep_cpc_t *cpc; 2378 2379 cpc = opaque; 2380 switch (dcrn) { 2381 case PPC405EP_CPC0_BOOT: 2382 /* Read-only register */ 2383 break; 2384 case PPC405EP_CPC0_EPCTL: 2385 /* Don't care for now */ 2386 cpc->epctl = val & 0xC00000F3; 2387 break; 2388 case PPC405EP_CPC0_PLLMR0: 2389 cpc->pllmr[0] = val & 0x00633333; 2390 ppc405ep_compute_clocks(cpc); 2391 break; 2392 case PPC405EP_CPC0_PLLMR1: 2393 cpc->pllmr[1] = val & 0xC0F73FFF; 2394 ppc405ep_compute_clocks(cpc); 2395 break; 2396 case PPC405EP_CPC0_UCR: 2397 /* UART control - don't care for now */ 2398 cpc->ucr = val & 0x003F7F7F; 2399 break; 2400 case PPC405EP_CPC0_SRR: 2401 cpc->srr = val; 2402 break; 2403 case PPC405EP_CPC0_JTAGID: 2404 /* Read-only */ 2405 break; 2406 case PPC405EP_CPC0_PCI: 2407 cpc->pci = val; 2408 break; 2409 } 2410 } 2411 2412 static void ppc405ep_cpc_reset (void *opaque) 2413 { 2414 ppc405ep_cpc_t *cpc = opaque; 2415 2416 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 2417 cpc->epctl = 0x00000000; 2418 cpc->pllmr[0] = 0x00011010; 2419 cpc->pllmr[1] = 0x40000000; 2420 cpc->ucr = 0x00000000; 2421 cpc->srr = 0x00040000; 2422 cpc->pci = 0x00000000; 2423 cpc->er = 0x00000000; 2424 cpc->fr = 0x00000000; 2425 cpc->sr = 0x00000000; 2426 ppc405ep_compute_clocks(cpc); 2427 } 2428 2429 /* XXX: sysclk should be between 25 and 100 MHz */ 2430 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 2431 uint32_t sysclk) 2432 { 2433 ppc405ep_cpc_t *cpc; 2434 2435 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 2436 memcpy(cpc->clk_setup, clk_setup, 2437 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 2438 cpc->jtagid = 0x20267049; 2439 cpc->sysclk = sysclk; 2440 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 2441 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 2442 &dcr_read_epcpc, &dcr_write_epcpc); 2443 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 2444 &dcr_read_epcpc, &dcr_write_epcpc); 2445 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 2446 &dcr_read_epcpc, &dcr_write_epcpc); 2447 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 2448 &dcr_read_epcpc, &dcr_write_epcpc); 2449 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 2450 &dcr_read_epcpc, &dcr_write_epcpc); 2451 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 2452 &dcr_read_epcpc, &dcr_write_epcpc); 2453 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 2454 &dcr_read_epcpc, &dcr_write_epcpc); 2455 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 2456 &dcr_read_epcpc, &dcr_write_epcpc); 2457 #if 0 2458 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 2459 &dcr_read_epcpc, &dcr_write_epcpc); 2460 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 2461 &dcr_read_epcpc, &dcr_write_epcpc); 2462 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 2463 &dcr_read_epcpc, &dcr_write_epcpc); 2464 #endif 2465 } 2466 2467 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 2468 MemoryRegion ram_memories[2], 2469 hwaddr ram_bases[2], 2470 hwaddr ram_sizes[2], 2471 uint32_t sysclk, qemu_irq **picp, 2472 int do_init) 2473 { 2474 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 2475 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 2476 PowerPCCPU *cpu; 2477 CPUPPCState *env; 2478 qemu_irq *pic, *irqs; 2479 2480 memset(clk_setup, 0, sizeof(clk_setup)); 2481 /* init CPUs */ 2482 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK], 2483 &tlb_clk_setup, sysclk); 2484 env = &cpu->env; 2485 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 2486 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 2487 /* Internal devices init */ 2488 /* Memory mapped devices registers */ 2489 /* PLB arbitrer */ 2490 ppc4xx_plb_init(env); 2491 /* PLB to OPB bridge */ 2492 ppc4xx_pob_init(env); 2493 /* OBP arbitrer */ 2494 ppc4xx_opba_init(0xef600600); 2495 /* Initialize timers */ 2496 ppc_booke_timers_init(cpu, sysclk, 0); 2497 /* Universal interrupt controller */ 2498 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); 2499 irqs[PPCUIC_OUTPUT_INT] = 2500 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 2501 irqs[PPCUIC_OUTPUT_CINT] = 2502 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 2503 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 2504 *picp = pic; 2505 /* SDRAM controller */ 2506 /* XXX 405EP has no ECC interrupt */ 2507 ppc4xx_sdram_init(env, pic[17], 2, ram_memories, 2508 ram_bases, ram_sizes, do_init); 2509 /* External bus controller */ 2510 ppc405_ebc_init(env); 2511 /* DMA controller */ 2512 dma_irqs[0] = pic[5]; 2513 dma_irqs[1] = pic[6]; 2514 dma_irqs[2] = pic[7]; 2515 dma_irqs[3] = pic[8]; 2516 ppc405_dma_init(env, dma_irqs); 2517 /* IIC controller */ 2518 ppc405_i2c_init(0xef600500, pic[2]); 2519 /* GPIO */ 2520 ppc405_gpio_init(0xef600700); 2521 /* Serial ports */ 2522 if (serial_hds[0] != NULL) { 2523 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 2524 PPC_SERIAL_MM_BAUDBASE, serial_hds[0], 2525 DEVICE_BIG_ENDIAN); 2526 } 2527 if (serial_hds[1] != NULL) { 2528 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 2529 PPC_SERIAL_MM_BAUDBASE, serial_hds[1], 2530 DEVICE_BIG_ENDIAN); 2531 } 2532 /* OCM */ 2533 ppc405_ocm_init(env); 2534 /* GPT */ 2535 gpt_irqs[0] = pic[19]; 2536 gpt_irqs[1] = pic[20]; 2537 gpt_irqs[2] = pic[21]; 2538 gpt_irqs[3] = pic[22]; 2539 gpt_irqs[4] = pic[23]; 2540 ppc4xx_gpt_init(0xef600000, gpt_irqs); 2541 /* PCI */ 2542 /* Uses pic[3], pic[16], pic[18] */ 2543 /* MAL */ 2544 mal_irqs[0] = pic[11]; 2545 mal_irqs[1] = pic[12]; 2546 mal_irqs[2] = pic[13]; 2547 mal_irqs[3] = pic[14]; 2548 ppc405_mal_init(env, mal_irqs); 2549 /* Ethernet */ 2550 /* Uses pic[9], pic[15], pic[17] */ 2551 /* CPU control */ 2552 ppc405ep_cpc_init(env, clk_setup, sysclk); 2553 2554 return env; 2555 } 2556