1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/ppc/ppc.h" 30 #include "hw/i2c/ppc4xx_i2c.h" 31 #include "hw/irq.h" 32 #include "ppc405.h" 33 #include "hw/char/serial.h" 34 #include "qemu/timer.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/sysemu.h" 37 #include "qemu/log.h" 38 #include "exec/address-spaces.h" 39 #include "hw/intc/ppc-uic.h" 40 #include "hw/qdev-properties.h" 41 #include "qapi/error.h" 42 43 //#define DEBUG_OPBA 44 //#define DEBUG_SDRAM 45 //#define DEBUG_GPIO 46 //#define DEBUG_SERIAL 47 //#define DEBUG_OCM 48 //#define DEBUG_GPT 49 //#define DEBUG_CLOCKS 50 //#define DEBUG_CLOCKS_LL 51 52 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 53 uint32_t flags) 54 { 55 CPUState *cs = env_cpu(env); 56 ram_addr_t bdloc; 57 int i, n; 58 59 /* We put the bd structure at the top of memory */ 60 if (bd->bi_memsize >= 0x01000000UL) 61 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 62 else 63 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 64 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 65 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 66 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 67 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 68 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 69 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 70 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 71 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 72 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 73 for (i = 0; i < 6; i++) { 74 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 75 } 76 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 77 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 78 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 79 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 80 for (i = 0; i < 4; i++) { 81 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 82 } 83 for (i = 0; i < 32; i++) { 84 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 85 } 86 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 87 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 88 for (i = 0; i < 6; i++) { 89 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 90 } 91 n = 0x6A; 92 if (flags & 0x00000001) { 93 for (i = 0; i < 6; i++) 94 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 95 } 96 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 97 n += 4; 98 for (i = 0; i < 2; i++) { 99 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 100 n += 4; 101 } 102 103 return bdloc; 104 } 105 106 /*****************************************************************************/ 107 /* Shared peripherals */ 108 109 /*****************************************************************************/ 110 /* Peripheral local bus arbitrer */ 111 enum { 112 PLB3A0_ACR = 0x077, 113 PLB4A0_ACR = 0x081, 114 PLB0_BESR = 0x084, 115 PLB0_BEAR = 0x086, 116 PLB0_ACR = 0x087, 117 PLB4A1_ACR = 0x089, 118 }; 119 120 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 121 struct ppc4xx_plb_t { 122 uint32_t acr; 123 uint32_t bear; 124 uint32_t besr; 125 }; 126 127 static uint32_t dcr_read_plb (void *opaque, int dcrn) 128 { 129 ppc4xx_plb_t *plb; 130 uint32_t ret; 131 132 plb = opaque; 133 switch (dcrn) { 134 case PLB0_ACR: 135 ret = plb->acr; 136 break; 137 case PLB0_BEAR: 138 ret = plb->bear; 139 break; 140 case PLB0_BESR: 141 ret = plb->besr; 142 break; 143 default: 144 /* Avoid gcc warning */ 145 ret = 0; 146 break; 147 } 148 149 return ret; 150 } 151 152 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 153 { 154 ppc4xx_plb_t *plb; 155 156 plb = opaque; 157 switch (dcrn) { 158 case PLB0_ACR: 159 /* We don't care about the actual parameters written as 160 * we don't manage any priorities on the bus 161 */ 162 plb->acr = val & 0xF8000000; 163 break; 164 case PLB0_BEAR: 165 /* Read only */ 166 break; 167 case PLB0_BESR: 168 /* Write-clear */ 169 plb->besr &= ~val; 170 break; 171 } 172 } 173 174 static void ppc4xx_plb_reset (void *opaque) 175 { 176 ppc4xx_plb_t *plb; 177 178 plb = opaque; 179 plb->acr = 0x00000000; 180 plb->bear = 0x00000000; 181 plb->besr = 0x00000000; 182 } 183 184 void ppc4xx_plb_init(CPUPPCState *env) 185 { 186 ppc4xx_plb_t *plb; 187 188 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 189 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 190 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 191 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 192 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 193 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 194 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 195 qemu_register_reset(ppc4xx_plb_reset, plb); 196 } 197 198 /*****************************************************************************/ 199 /* PLB to OPB bridge */ 200 enum { 201 POB0_BESR0 = 0x0A0, 202 POB0_BESR1 = 0x0A2, 203 POB0_BEAR = 0x0A4, 204 }; 205 206 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 207 struct ppc4xx_pob_t { 208 uint32_t bear; 209 uint32_t besr0; 210 uint32_t besr1; 211 }; 212 213 static uint32_t dcr_read_pob (void *opaque, int dcrn) 214 { 215 ppc4xx_pob_t *pob; 216 uint32_t ret; 217 218 pob = opaque; 219 switch (dcrn) { 220 case POB0_BEAR: 221 ret = pob->bear; 222 break; 223 case POB0_BESR0: 224 ret = pob->besr0; 225 break; 226 case POB0_BESR1: 227 ret = pob->besr1; 228 break; 229 default: 230 /* Avoid gcc warning */ 231 ret = 0; 232 break; 233 } 234 235 return ret; 236 } 237 238 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 239 { 240 ppc4xx_pob_t *pob; 241 242 pob = opaque; 243 switch (dcrn) { 244 case POB0_BEAR: 245 /* Read only */ 246 break; 247 case POB0_BESR0: 248 /* Write-clear */ 249 pob->besr0 &= ~val; 250 break; 251 case POB0_BESR1: 252 /* Write-clear */ 253 pob->besr1 &= ~val; 254 break; 255 } 256 } 257 258 static void ppc4xx_pob_reset (void *opaque) 259 { 260 ppc4xx_pob_t *pob; 261 262 pob = opaque; 263 /* No error */ 264 pob->bear = 0x00000000; 265 pob->besr0 = 0x0000000; 266 pob->besr1 = 0x0000000; 267 } 268 269 static void ppc4xx_pob_init(CPUPPCState *env) 270 { 271 ppc4xx_pob_t *pob; 272 273 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 274 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 275 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 276 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 277 qemu_register_reset(ppc4xx_pob_reset, pob); 278 } 279 280 /*****************************************************************************/ 281 /* OPB arbitrer */ 282 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 283 struct ppc4xx_opba_t { 284 MemoryRegion io; 285 uint8_t cr; 286 uint8_t pr; 287 }; 288 289 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 290 { 291 ppc4xx_opba_t *opba; 292 uint32_t ret; 293 294 #ifdef DEBUG_OPBA 295 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 296 #endif 297 opba = opaque; 298 switch (addr) { 299 case 0x00: 300 ret = opba->cr; 301 break; 302 case 0x01: 303 ret = opba->pr; 304 break; 305 default: 306 ret = 0x00; 307 break; 308 } 309 310 return ret; 311 } 312 313 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 314 unsigned size) 315 { 316 ppc4xx_opba_t *opba; 317 318 #ifdef DEBUG_OPBA 319 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 320 value); 321 #endif 322 opba = opaque; 323 switch (addr) { 324 case 0x00: 325 opba->cr = value & 0xF8; 326 break; 327 case 0x01: 328 opba->pr = value & 0xFF; 329 break; 330 default: 331 break; 332 } 333 } 334 static const MemoryRegionOps opba_ops = { 335 .read = opba_readb, 336 .write = opba_writeb, 337 .impl.min_access_size = 1, 338 .impl.max_access_size = 1, 339 .valid.min_access_size = 1, 340 .valid.max_access_size = 4, 341 .endianness = DEVICE_BIG_ENDIAN, 342 }; 343 344 static void ppc4xx_opba_reset (void *opaque) 345 { 346 ppc4xx_opba_t *opba; 347 348 opba = opaque; 349 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 350 opba->pr = 0x11; 351 } 352 353 static void ppc4xx_opba_init(hwaddr base) 354 { 355 ppc4xx_opba_t *opba; 356 357 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 358 #ifdef DEBUG_OPBA 359 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 360 #endif 361 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 362 memory_region_add_subregion(get_system_memory(), base, &opba->io); 363 qemu_register_reset(ppc4xx_opba_reset, opba); 364 } 365 366 /*****************************************************************************/ 367 /* Code decompression controller */ 368 /* XXX: TODO */ 369 370 /*****************************************************************************/ 371 /* Peripheral controller */ 372 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 373 struct ppc4xx_ebc_t { 374 uint32_t addr; 375 uint32_t bcr[8]; 376 uint32_t bap[8]; 377 uint32_t bear; 378 uint32_t besr0; 379 uint32_t besr1; 380 uint32_t cfg; 381 }; 382 383 enum { 384 EBC0_CFGADDR = 0x012, 385 EBC0_CFGDATA = 0x013, 386 }; 387 388 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 389 { 390 ppc4xx_ebc_t *ebc; 391 uint32_t ret; 392 393 ebc = opaque; 394 switch (dcrn) { 395 case EBC0_CFGADDR: 396 ret = ebc->addr; 397 break; 398 case EBC0_CFGDATA: 399 switch (ebc->addr) { 400 case 0x00: /* B0CR */ 401 ret = ebc->bcr[0]; 402 break; 403 case 0x01: /* B1CR */ 404 ret = ebc->bcr[1]; 405 break; 406 case 0x02: /* B2CR */ 407 ret = ebc->bcr[2]; 408 break; 409 case 0x03: /* B3CR */ 410 ret = ebc->bcr[3]; 411 break; 412 case 0x04: /* B4CR */ 413 ret = ebc->bcr[4]; 414 break; 415 case 0x05: /* B5CR */ 416 ret = ebc->bcr[5]; 417 break; 418 case 0x06: /* B6CR */ 419 ret = ebc->bcr[6]; 420 break; 421 case 0x07: /* B7CR */ 422 ret = ebc->bcr[7]; 423 break; 424 case 0x10: /* B0AP */ 425 ret = ebc->bap[0]; 426 break; 427 case 0x11: /* B1AP */ 428 ret = ebc->bap[1]; 429 break; 430 case 0x12: /* B2AP */ 431 ret = ebc->bap[2]; 432 break; 433 case 0x13: /* B3AP */ 434 ret = ebc->bap[3]; 435 break; 436 case 0x14: /* B4AP */ 437 ret = ebc->bap[4]; 438 break; 439 case 0x15: /* B5AP */ 440 ret = ebc->bap[5]; 441 break; 442 case 0x16: /* B6AP */ 443 ret = ebc->bap[6]; 444 break; 445 case 0x17: /* B7AP */ 446 ret = ebc->bap[7]; 447 break; 448 case 0x20: /* BEAR */ 449 ret = ebc->bear; 450 break; 451 case 0x21: /* BESR0 */ 452 ret = ebc->besr0; 453 break; 454 case 0x22: /* BESR1 */ 455 ret = ebc->besr1; 456 break; 457 case 0x23: /* CFG */ 458 ret = ebc->cfg; 459 break; 460 default: 461 ret = 0x00000000; 462 break; 463 } 464 break; 465 default: 466 ret = 0x00000000; 467 break; 468 } 469 470 return ret; 471 } 472 473 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 474 { 475 ppc4xx_ebc_t *ebc; 476 477 ebc = opaque; 478 switch (dcrn) { 479 case EBC0_CFGADDR: 480 ebc->addr = val; 481 break; 482 case EBC0_CFGDATA: 483 switch (ebc->addr) { 484 case 0x00: /* B0CR */ 485 break; 486 case 0x01: /* B1CR */ 487 break; 488 case 0x02: /* B2CR */ 489 break; 490 case 0x03: /* B3CR */ 491 break; 492 case 0x04: /* B4CR */ 493 break; 494 case 0x05: /* B5CR */ 495 break; 496 case 0x06: /* B6CR */ 497 break; 498 case 0x07: /* B7CR */ 499 break; 500 case 0x10: /* B0AP */ 501 break; 502 case 0x11: /* B1AP */ 503 break; 504 case 0x12: /* B2AP */ 505 break; 506 case 0x13: /* B3AP */ 507 break; 508 case 0x14: /* B4AP */ 509 break; 510 case 0x15: /* B5AP */ 511 break; 512 case 0x16: /* B6AP */ 513 break; 514 case 0x17: /* B7AP */ 515 break; 516 case 0x20: /* BEAR */ 517 break; 518 case 0x21: /* BESR0 */ 519 break; 520 case 0x22: /* BESR1 */ 521 break; 522 case 0x23: /* CFG */ 523 break; 524 default: 525 break; 526 } 527 break; 528 default: 529 break; 530 } 531 } 532 533 static void ebc_reset (void *opaque) 534 { 535 ppc4xx_ebc_t *ebc; 536 int i; 537 538 ebc = opaque; 539 ebc->addr = 0x00000000; 540 ebc->bap[0] = 0x7F8FFE80; 541 ebc->bcr[0] = 0xFFE28000; 542 for (i = 0; i < 8; i++) { 543 ebc->bap[i] = 0x00000000; 544 ebc->bcr[i] = 0x00000000; 545 } 546 ebc->besr0 = 0x00000000; 547 ebc->besr1 = 0x00000000; 548 ebc->cfg = 0x80400000; 549 } 550 551 void ppc405_ebc_init(CPUPPCState *env) 552 { 553 ppc4xx_ebc_t *ebc; 554 555 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 556 qemu_register_reset(&ebc_reset, ebc); 557 ppc_dcr_register(env, EBC0_CFGADDR, 558 ebc, &dcr_read_ebc, &dcr_write_ebc); 559 ppc_dcr_register(env, EBC0_CFGDATA, 560 ebc, &dcr_read_ebc, &dcr_write_ebc); 561 } 562 563 /*****************************************************************************/ 564 /* DMA controller */ 565 enum { 566 DMA0_CR0 = 0x100, 567 DMA0_CT0 = 0x101, 568 DMA0_DA0 = 0x102, 569 DMA0_SA0 = 0x103, 570 DMA0_SG0 = 0x104, 571 DMA0_CR1 = 0x108, 572 DMA0_CT1 = 0x109, 573 DMA0_DA1 = 0x10A, 574 DMA0_SA1 = 0x10B, 575 DMA0_SG1 = 0x10C, 576 DMA0_CR2 = 0x110, 577 DMA0_CT2 = 0x111, 578 DMA0_DA2 = 0x112, 579 DMA0_SA2 = 0x113, 580 DMA0_SG2 = 0x114, 581 DMA0_CR3 = 0x118, 582 DMA0_CT3 = 0x119, 583 DMA0_DA3 = 0x11A, 584 DMA0_SA3 = 0x11B, 585 DMA0_SG3 = 0x11C, 586 DMA0_SR = 0x120, 587 DMA0_SGC = 0x123, 588 DMA0_SLP = 0x125, 589 DMA0_POL = 0x126, 590 }; 591 592 typedef struct ppc405_dma_t ppc405_dma_t; 593 struct ppc405_dma_t { 594 qemu_irq irqs[4]; 595 uint32_t cr[4]; 596 uint32_t ct[4]; 597 uint32_t da[4]; 598 uint32_t sa[4]; 599 uint32_t sg[4]; 600 uint32_t sr; 601 uint32_t sgc; 602 uint32_t slp; 603 uint32_t pol; 604 }; 605 606 static uint32_t dcr_read_dma (void *opaque, int dcrn) 607 { 608 return 0; 609 } 610 611 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 612 { 613 } 614 615 static void ppc405_dma_reset (void *opaque) 616 { 617 ppc405_dma_t *dma; 618 int i; 619 620 dma = opaque; 621 for (i = 0; i < 4; i++) { 622 dma->cr[i] = 0x00000000; 623 dma->ct[i] = 0x00000000; 624 dma->da[i] = 0x00000000; 625 dma->sa[i] = 0x00000000; 626 dma->sg[i] = 0x00000000; 627 } 628 dma->sr = 0x00000000; 629 dma->sgc = 0x00000000; 630 dma->slp = 0x7C000000; 631 dma->pol = 0x00000000; 632 } 633 634 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 635 { 636 ppc405_dma_t *dma; 637 638 dma = g_malloc0(sizeof(ppc405_dma_t)); 639 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 640 qemu_register_reset(&ppc405_dma_reset, dma); 641 ppc_dcr_register(env, DMA0_CR0, 642 dma, &dcr_read_dma, &dcr_write_dma); 643 ppc_dcr_register(env, DMA0_CT0, 644 dma, &dcr_read_dma, &dcr_write_dma); 645 ppc_dcr_register(env, DMA0_DA0, 646 dma, &dcr_read_dma, &dcr_write_dma); 647 ppc_dcr_register(env, DMA0_SA0, 648 dma, &dcr_read_dma, &dcr_write_dma); 649 ppc_dcr_register(env, DMA0_SG0, 650 dma, &dcr_read_dma, &dcr_write_dma); 651 ppc_dcr_register(env, DMA0_CR1, 652 dma, &dcr_read_dma, &dcr_write_dma); 653 ppc_dcr_register(env, DMA0_CT1, 654 dma, &dcr_read_dma, &dcr_write_dma); 655 ppc_dcr_register(env, DMA0_DA1, 656 dma, &dcr_read_dma, &dcr_write_dma); 657 ppc_dcr_register(env, DMA0_SA1, 658 dma, &dcr_read_dma, &dcr_write_dma); 659 ppc_dcr_register(env, DMA0_SG1, 660 dma, &dcr_read_dma, &dcr_write_dma); 661 ppc_dcr_register(env, DMA0_CR2, 662 dma, &dcr_read_dma, &dcr_write_dma); 663 ppc_dcr_register(env, DMA0_CT2, 664 dma, &dcr_read_dma, &dcr_write_dma); 665 ppc_dcr_register(env, DMA0_DA2, 666 dma, &dcr_read_dma, &dcr_write_dma); 667 ppc_dcr_register(env, DMA0_SA2, 668 dma, &dcr_read_dma, &dcr_write_dma); 669 ppc_dcr_register(env, DMA0_SG2, 670 dma, &dcr_read_dma, &dcr_write_dma); 671 ppc_dcr_register(env, DMA0_CR3, 672 dma, &dcr_read_dma, &dcr_write_dma); 673 ppc_dcr_register(env, DMA0_CT3, 674 dma, &dcr_read_dma, &dcr_write_dma); 675 ppc_dcr_register(env, DMA0_DA3, 676 dma, &dcr_read_dma, &dcr_write_dma); 677 ppc_dcr_register(env, DMA0_SA3, 678 dma, &dcr_read_dma, &dcr_write_dma); 679 ppc_dcr_register(env, DMA0_SG3, 680 dma, &dcr_read_dma, &dcr_write_dma); 681 ppc_dcr_register(env, DMA0_SR, 682 dma, &dcr_read_dma, &dcr_write_dma); 683 ppc_dcr_register(env, DMA0_SGC, 684 dma, &dcr_read_dma, &dcr_write_dma); 685 ppc_dcr_register(env, DMA0_SLP, 686 dma, &dcr_read_dma, &dcr_write_dma); 687 ppc_dcr_register(env, DMA0_POL, 688 dma, &dcr_read_dma, &dcr_write_dma); 689 } 690 691 /*****************************************************************************/ 692 /* GPIO */ 693 typedef struct ppc405_gpio_t ppc405_gpio_t; 694 struct ppc405_gpio_t { 695 MemoryRegion io; 696 uint32_t or; 697 uint32_t tcr; 698 uint32_t osrh; 699 uint32_t osrl; 700 uint32_t tsrh; 701 uint32_t tsrl; 702 uint32_t odr; 703 uint32_t ir; 704 uint32_t rr1; 705 uint32_t isr1h; 706 uint32_t isr1l; 707 }; 708 709 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 710 { 711 #ifdef DEBUG_GPIO 712 printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); 713 #endif 714 715 return 0; 716 } 717 718 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 719 unsigned size) 720 { 721 #ifdef DEBUG_GPIO 722 printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", 723 __func__, addr, size, value); 724 #endif 725 } 726 727 static const MemoryRegionOps ppc405_gpio_ops = { 728 .read = ppc405_gpio_read, 729 .write = ppc405_gpio_write, 730 .endianness = DEVICE_NATIVE_ENDIAN, 731 }; 732 733 static void ppc405_gpio_reset (void *opaque) 734 { 735 } 736 737 static void ppc405_gpio_init(hwaddr base) 738 { 739 ppc405_gpio_t *gpio; 740 741 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 742 #ifdef DEBUG_GPIO 743 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 744 #endif 745 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 746 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 747 qemu_register_reset(&ppc405_gpio_reset, gpio); 748 } 749 750 /*****************************************************************************/ 751 /* On Chip Memory */ 752 enum { 753 OCM0_ISARC = 0x018, 754 OCM0_ISACNTL = 0x019, 755 OCM0_DSARC = 0x01A, 756 OCM0_DSACNTL = 0x01B, 757 }; 758 759 typedef struct ppc405_ocm_t ppc405_ocm_t; 760 struct ppc405_ocm_t { 761 MemoryRegion ram; 762 MemoryRegion isarc_ram; 763 MemoryRegion dsarc_ram; 764 uint32_t isarc; 765 uint32_t isacntl; 766 uint32_t dsarc; 767 uint32_t dsacntl; 768 }; 769 770 static void ocm_update_mappings (ppc405_ocm_t *ocm, 771 uint32_t isarc, uint32_t isacntl, 772 uint32_t dsarc, uint32_t dsacntl) 773 { 774 #ifdef DEBUG_OCM 775 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 776 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 777 " (%08" PRIx32 " %08" PRIx32 ")\n", 778 isarc, isacntl, dsarc, dsacntl, 779 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 780 #endif 781 if (ocm->isarc != isarc || 782 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 783 if (ocm->isacntl & 0x80000000) { 784 /* Unmap previously assigned memory region */ 785 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 786 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 787 } 788 if (isacntl & 0x80000000) { 789 /* Map new instruction memory region */ 790 #ifdef DEBUG_OCM 791 printf("OCM map ISA %08" PRIx32 "\n", isarc); 792 #endif 793 memory_region_add_subregion(get_system_memory(), isarc, 794 &ocm->isarc_ram); 795 } 796 } 797 if (ocm->dsarc != dsarc || 798 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 799 if (ocm->dsacntl & 0x80000000) { 800 /* Beware not to unmap the region we just mapped */ 801 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 802 /* Unmap previously assigned memory region */ 803 #ifdef DEBUG_OCM 804 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 805 #endif 806 memory_region_del_subregion(get_system_memory(), 807 &ocm->dsarc_ram); 808 } 809 } 810 if (dsacntl & 0x80000000) { 811 /* Beware not to remap the region we just mapped */ 812 if (!(isacntl & 0x80000000) || dsarc != isarc) { 813 /* Map new data memory region */ 814 #ifdef DEBUG_OCM 815 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 816 #endif 817 memory_region_add_subregion(get_system_memory(), dsarc, 818 &ocm->dsarc_ram); 819 } 820 } 821 } 822 } 823 824 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 825 { 826 ppc405_ocm_t *ocm; 827 uint32_t ret; 828 829 ocm = opaque; 830 switch (dcrn) { 831 case OCM0_ISARC: 832 ret = ocm->isarc; 833 break; 834 case OCM0_ISACNTL: 835 ret = ocm->isacntl; 836 break; 837 case OCM0_DSARC: 838 ret = ocm->dsarc; 839 break; 840 case OCM0_DSACNTL: 841 ret = ocm->dsacntl; 842 break; 843 default: 844 ret = 0; 845 break; 846 } 847 848 return ret; 849 } 850 851 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 852 { 853 ppc405_ocm_t *ocm; 854 uint32_t isarc, dsarc, isacntl, dsacntl; 855 856 ocm = opaque; 857 isarc = ocm->isarc; 858 dsarc = ocm->dsarc; 859 isacntl = ocm->isacntl; 860 dsacntl = ocm->dsacntl; 861 switch (dcrn) { 862 case OCM0_ISARC: 863 isarc = val & 0xFC000000; 864 break; 865 case OCM0_ISACNTL: 866 isacntl = val & 0xC0000000; 867 break; 868 case OCM0_DSARC: 869 isarc = val & 0xFC000000; 870 break; 871 case OCM0_DSACNTL: 872 isacntl = val & 0xC0000000; 873 break; 874 } 875 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 876 ocm->isarc = isarc; 877 ocm->dsarc = dsarc; 878 ocm->isacntl = isacntl; 879 ocm->dsacntl = dsacntl; 880 } 881 882 static void ocm_reset (void *opaque) 883 { 884 ppc405_ocm_t *ocm; 885 uint32_t isarc, dsarc, isacntl, dsacntl; 886 887 ocm = opaque; 888 isarc = 0x00000000; 889 isacntl = 0x00000000; 890 dsarc = 0x00000000; 891 dsacntl = 0x00000000; 892 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 893 ocm->isarc = isarc; 894 ocm->dsarc = dsarc; 895 ocm->isacntl = isacntl; 896 ocm->dsacntl = dsacntl; 897 } 898 899 static void ppc405_ocm_init(CPUPPCState *env) 900 { 901 ppc405_ocm_t *ocm; 902 903 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 904 /* XXX: Size is 4096 or 0x04000000 */ 905 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 906 &error_fatal); 907 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 908 &ocm->isarc_ram, 0, 4 * KiB); 909 qemu_register_reset(&ocm_reset, ocm); 910 ppc_dcr_register(env, OCM0_ISARC, 911 ocm, &dcr_read_ocm, &dcr_write_ocm); 912 ppc_dcr_register(env, OCM0_ISACNTL, 913 ocm, &dcr_read_ocm, &dcr_write_ocm); 914 ppc_dcr_register(env, OCM0_DSARC, 915 ocm, &dcr_read_ocm, &dcr_write_ocm); 916 ppc_dcr_register(env, OCM0_DSACNTL, 917 ocm, &dcr_read_ocm, &dcr_write_ocm); 918 } 919 920 /*****************************************************************************/ 921 /* General purpose timers */ 922 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 923 struct ppc4xx_gpt_t { 924 MemoryRegion iomem; 925 int64_t tb_offset; 926 uint32_t tb_freq; 927 QEMUTimer *timer; 928 qemu_irq irqs[5]; 929 uint32_t oe; 930 uint32_t ol; 931 uint32_t im; 932 uint32_t is; 933 uint32_t ie; 934 uint32_t comp[5]; 935 uint32_t mask[5]; 936 }; 937 938 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 939 { 940 /* XXX: TODO */ 941 return 0; 942 } 943 944 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 945 { 946 /* XXX: TODO */ 947 } 948 949 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 950 { 951 uint32_t mask; 952 int i; 953 954 mask = 0x80000000; 955 for (i = 0; i < 5; i++) { 956 if (gpt->oe & mask) { 957 /* Output is enabled */ 958 if (ppc4xx_gpt_compare(gpt, i)) { 959 /* Comparison is OK */ 960 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 961 } else { 962 /* Comparison is KO */ 963 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 964 } 965 } 966 mask = mask >> 1; 967 } 968 } 969 970 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 971 { 972 uint32_t mask; 973 int i; 974 975 mask = 0x00008000; 976 for (i = 0; i < 5; i++) { 977 if (gpt->is & gpt->im & mask) 978 qemu_irq_raise(gpt->irqs[i]); 979 else 980 qemu_irq_lower(gpt->irqs[i]); 981 mask = mask >> 1; 982 } 983 } 984 985 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 986 { 987 /* XXX: TODO */ 988 } 989 990 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 991 { 992 ppc4xx_gpt_t *gpt; 993 uint32_t ret; 994 int idx; 995 996 #ifdef DEBUG_GPT 997 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 998 #endif 999 gpt = opaque; 1000 switch (addr) { 1001 case 0x00: 1002 /* Time base counter */ 1003 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1004 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1005 break; 1006 case 0x10: 1007 /* Output enable */ 1008 ret = gpt->oe; 1009 break; 1010 case 0x14: 1011 /* Output level */ 1012 ret = gpt->ol; 1013 break; 1014 case 0x18: 1015 /* Interrupt mask */ 1016 ret = gpt->im; 1017 break; 1018 case 0x1C: 1019 case 0x20: 1020 /* Interrupt status */ 1021 ret = gpt->is; 1022 break; 1023 case 0x24: 1024 /* Interrupt enable */ 1025 ret = gpt->ie; 1026 break; 1027 case 0x80 ... 0x90: 1028 /* Compare timer */ 1029 idx = (addr - 0x80) >> 2; 1030 ret = gpt->comp[idx]; 1031 break; 1032 case 0xC0 ... 0xD0: 1033 /* Compare mask */ 1034 idx = (addr - 0xC0) >> 2; 1035 ret = gpt->mask[idx]; 1036 break; 1037 default: 1038 ret = -1; 1039 break; 1040 } 1041 1042 return ret; 1043 } 1044 1045 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1046 unsigned size) 1047 { 1048 ppc4xx_gpt_t *gpt; 1049 int idx; 1050 1051 #ifdef DEBUG_I2C 1052 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1053 value); 1054 #endif 1055 gpt = opaque; 1056 switch (addr) { 1057 case 0x00: 1058 /* Time base counter */ 1059 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1060 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1061 ppc4xx_gpt_compute_timer(gpt); 1062 break; 1063 case 0x10: 1064 /* Output enable */ 1065 gpt->oe = value & 0xF8000000; 1066 ppc4xx_gpt_set_outputs(gpt); 1067 break; 1068 case 0x14: 1069 /* Output level */ 1070 gpt->ol = value & 0xF8000000; 1071 ppc4xx_gpt_set_outputs(gpt); 1072 break; 1073 case 0x18: 1074 /* Interrupt mask */ 1075 gpt->im = value & 0x0000F800; 1076 break; 1077 case 0x1C: 1078 /* Interrupt status set */ 1079 gpt->is |= value & 0x0000F800; 1080 ppc4xx_gpt_set_irqs(gpt); 1081 break; 1082 case 0x20: 1083 /* Interrupt status clear */ 1084 gpt->is &= ~(value & 0x0000F800); 1085 ppc4xx_gpt_set_irqs(gpt); 1086 break; 1087 case 0x24: 1088 /* Interrupt enable */ 1089 gpt->ie = value & 0x0000F800; 1090 ppc4xx_gpt_set_irqs(gpt); 1091 break; 1092 case 0x80 ... 0x90: 1093 /* Compare timer */ 1094 idx = (addr - 0x80) >> 2; 1095 gpt->comp[idx] = value & 0xF8000000; 1096 ppc4xx_gpt_compute_timer(gpt); 1097 break; 1098 case 0xC0 ... 0xD0: 1099 /* Compare mask */ 1100 idx = (addr - 0xC0) >> 2; 1101 gpt->mask[idx] = value & 0xF8000000; 1102 ppc4xx_gpt_compute_timer(gpt); 1103 break; 1104 } 1105 } 1106 1107 static const MemoryRegionOps gpt_ops = { 1108 .read = ppc4xx_gpt_read, 1109 .write = ppc4xx_gpt_write, 1110 .valid.min_access_size = 4, 1111 .valid.max_access_size = 4, 1112 .endianness = DEVICE_NATIVE_ENDIAN, 1113 }; 1114 1115 static void ppc4xx_gpt_cb (void *opaque) 1116 { 1117 ppc4xx_gpt_t *gpt; 1118 1119 gpt = opaque; 1120 ppc4xx_gpt_set_irqs(gpt); 1121 ppc4xx_gpt_set_outputs(gpt); 1122 ppc4xx_gpt_compute_timer(gpt); 1123 } 1124 1125 static void ppc4xx_gpt_reset (void *opaque) 1126 { 1127 ppc4xx_gpt_t *gpt; 1128 int i; 1129 1130 gpt = opaque; 1131 timer_del(gpt->timer); 1132 gpt->oe = 0x00000000; 1133 gpt->ol = 0x00000000; 1134 gpt->im = 0x00000000; 1135 gpt->is = 0x00000000; 1136 gpt->ie = 0x00000000; 1137 for (i = 0; i < 5; i++) { 1138 gpt->comp[i] = 0x00000000; 1139 gpt->mask[i] = 0x00000000; 1140 } 1141 } 1142 1143 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1144 { 1145 ppc4xx_gpt_t *gpt; 1146 int i; 1147 1148 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1149 for (i = 0; i < 5; i++) { 1150 gpt->irqs[i] = irqs[i]; 1151 } 1152 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1153 #ifdef DEBUG_GPT 1154 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1155 #endif 1156 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1157 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1158 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1159 } 1160 1161 /*****************************************************************************/ 1162 /* PowerPC 405EP */ 1163 /* CPU control */ 1164 enum { 1165 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1166 PPC405EP_CPC0_BOOT = 0x0F1, 1167 PPC405EP_CPC0_EPCTL = 0x0F3, 1168 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1169 PPC405EP_CPC0_UCR = 0x0F5, 1170 PPC405EP_CPC0_SRR = 0x0F6, 1171 PPC405EP_CPC0_JTAGID = 0x0F7, 1172 PPC405EP_CPC0_PCI = 0x0F9, 1173 #if 0 1174 PPC405EP_CPC0_ER = xxx, 1175 PPC405EP_CPC0_FR = xxx, 1176 PPC405EP_CPC0_SR = xxx, 1177 #endif 1178 }; 1179 1180 enum { 1181 PPC405EP_CPU_CLK = 0, 1182 PPC405EP_PLB_CLK = 1, 1183 PPC405EP_OPB_CLK = 2, 1184 PPC405EP_EBC_CLK = 3, 1185 PPC405EP_MAL_CLK = 4, 1186 PPC405EP_PCI_CLK = 5, 1187 PPC405EP_UART0_CLK = 6, 1188 PPC405EP_UART1_CLK = 7, 1189 PPC405EP_CLK_NB = 8, 1190 }; 1191 1192 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1193 struct ppc405ep_cpc_t { 1194 uint32_t sysclk; 1195 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1196 uint32_t boot; 1197 uint32_t epctl; 1198 uint32_t pllmr[2]; 1199 uint32_t ucr; 1200 uint32_t srr; 1201 uint32_t jtagid; 1202 uint32_t pci; 1203 /* Clock and power management */ 1204 uint32_t er; 1205 uint32_t fr; 1206 uint32_t sr; 1207 }; 1208 1209 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1210 { 1211 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1212 uint32_t UART0_clk, UART1_clk; 1213 uint64_t VCO_out, PLL_out; 1214 int M, D; 1215 1216 VCO_out = 0; 1217 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1218 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1219 #ifdef DEBUG_CLOCKS_LL 1220 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 1221 #endif 1222 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1223 #ifdef DEBUG_CLOCKS_LL 1224 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 1225 #endif 1226 VCO_out = (uint64_t)cpc->sysclk * M * D; 1227 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1228 /* Error - unlock the PLL */ 1229 printf("VCO out of range %" PRIu64 "\n", VCO_out); 1230 #if 0 1231 cpc->pllmr[1] &= ~0x80000000; 1232 goto pll_bypass; 1233 #endif 1234 } 1235 PLL_out = VCO_out / D; 1236 /* Pretend the PLL is locked */ 1237 cpc->boot |= 0x00000001; 1238 } else { 1239 #if 0 1240 pll_bypass: 1241 #endif 1242 PLL_out = cpc->sysclk; 1243 if (cpc->pllmr[1] & 0x40000000) { 1244 /* Pretend the PLL is not locked */ 1245 cpc->boot &= ~0x00000001; 1246 } 1247 } 1248 /* Now, compute all other clocks */ 1249 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1250 #ifdef DEBUG_CLOCKS_LL 1251 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 1252 #endif 1253 CPU_clk = PLL_out / D; 1254 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1255 #ifdef DEBUG_CLOCKS_LL 1256 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 1257 #endif 1258 PLB_clk = CPU_clk / D; 1259 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1260 #ifdef DEBUG_CLOCKS_LL 1261 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 1262 #endif 1263 OPB_clk = PLB_clk / D; 1264 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1265 #ifdef DEBUG_CLOCKS_LL 1266 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 1267 #endif 1268 EBC_clk = PLB_clk / D; 1269 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1270 #ifdef DEBUG_CLOCKS_LL 1271 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 1272 #endif 1273 MAL_clk = PLB_clk / D; 1274 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1275 #ifdef DEBUG_CLOCKS_LL 1276 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 1277 #endif 1278 PCI_clk = PLB_clk / D; 1279 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1280 #ifdef DEBUG_CLOCKS_LL 1281 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 1282 #endif 1283 UART0_clk = PLL_out / D; 1284 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1285 #ifdef DEBUG_CLOCKS_LL 1286 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 1287 #endif 1288 UART1_clk = PLL_out / D; 1289 #ifdef DEBUG_CLOCKS 1290 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1291 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 1292 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1293 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1294 " UART1 %" PRIu32 "\n", 1295 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1296 UART0_clk, UART1_clk); 1297 #endif 1298 /* Setup CPU clocks */ 1299 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1300 /* Setup PLB clock */ 1301 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1302 /* Setup OPB clock */ 1303 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1304 /* Setup external clock */ 1305 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1306 /* Setup MAL clock */ 1307 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1308 /* Setup PCI clock */ 1309 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1310 /* Setup UART0 clock */ 1311 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1312 /* Setup UART1 clock */ 1313 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1314 } 1315 1316 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1317 { 1318 ppc405ep_cpc_t *cpc; 1319 uint32_t ret; 1320 1321 cpc = opaque; 1322 switch (dcrn) { 1323 case PPC405EP_CPC0_BOOT: 1324 ret = cpc->boot; 1325 break; 1326 case PPC405EP_CPC0_EPCTL: 1327 ret = cpc->epctl; 1328 break; 1329 case PPC405EP_CPC0_PLLMR0: 1330 ret = cpc->pllmr[0]; 1331 break; 1332 case PPC405EP_CPC0_PLLMR1: 1333 ret = cpc->pllmr[1]; 1334 break; 1335 case PPC405EP_CPC0_UCR: 1336 ret = cpc->ucr; 1337 break; 1338 case PPC405EP_CPC0_SRR: 1339 ret = cpc->srr; 1340 break; 1341 case PPC405EP_CPC0_JTAGID: 1342 ret = cpc->jtagid; 1343 break; 1344 case PPC405EP_CPC0_PCI: 1345 ret = cpc->pci; 1346 break; 1347 default: 1348 /* Avoid gcc warning */ 1349 ret = 0; 1350 break; 1351 } 1352 1353 return ret; 1354 } 1355 1356 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1357 { 1358 ppc405ep_cpc_t *cpc; 1359 1360 cpc = opaque; 1361 switch (dcrn) { 1362 case PPC405EP_CPC0_BOOT: 1363 /* Read-only register */ 1364 break; 1365 case PPC405EP_CPC0_EPCTL: 1366 /* Don't care for now */ 1367 cpc->epctl = val & 0xC00000F3; 1368 break; 1369 case PPC405EP_CPC0_PLLMR0: 1370 cpc->pllmr[0] = val & 0x00633333; 1371 ppc405ep_compute_clocks(cpc); 1372 break; 1373 case PPC405EP_CPC0_PLLMR1: 1374 cpc->pllmr[1] = val & 0xC0F73FFF; 1375 ppc405ep_compute_clocks(cpc); 1376 break; 1377 case PPC405EP_CPC0_UCR: 1378 /* UART control - don't care for now */ 1379 cpc->ucr = val & 0x003F7F7F; 1380 break; 1381 case PPC405EP_CPC0_SRR: 1382 cpc->srr = val; 1383 break; 1384 case PPC405EP_CPC0_JTAGID: 1385 /* Read-only */ 1386 break; 1387 case PPC405EP_CPC0_PCI: 1388 cpc->pci = val; 1389 break; 1390 } 1391 } 1392 1393 static void ppc405ep_cpc_reset (void *opaque) 1394 { 1395 ppc405ep_cpc_t *cpc = opaque; 1396 1397 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1398 cpc->epctl = 0x00000000; 1399 cpc->pllmr[0] = 0x00011010; 1400 cpc->pllmr[1] = 0x40000000; 1401 cpc->ucr = 0x00000000; 1402 cpc->srr = 0x00040000; 1403 cpc->pci = 0x00000000; 1404 cpc->er = 0x00000000; 1405 cpc->fr = 0x00000000; 1406 cpc->sr = 0x00000000; 1407 ppc405ep_compute_clocks(cpc); 1408 } 1409 1410 /* XXX: sysclk should be between 25 and 100 MHz */ 1411 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1412 uint32_t sysclk) 1413 { 1414 ppc405ep_cpc_t *cpc; 1415 1416 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1417 memcpy(cpc->clk_setup, clk_setup, 1418 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1419 cpc->jtagid = 0x20267049; 1420 cpc->sysclk = sysclk; 1421 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1422 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1423 &dcr_read_epcpc, &dcr_write_epcpc); 1424 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1425 &dcr_read_epcpc, &dcr_write_epcpc); 1426 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1427 &dcr_read_epcpc, &dcr_write_epcpc); 1428 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1429 &dcr_read_epcpc, &dcr_write_epcpc); 1430 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1431 &dcr_read_epcpc, &dcr_write_epcpc); 1432 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1433 &dcr_read_epcpc, &dcr_write_epcpc); 1434 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1435 &dcr_read_epcpc, &dcr_write_epcpc); 1436 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1437 &dcr_read_epcpc, &dcr_write_epcpc); 1438 #if 0 1439 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1440 &dcr_read_epcpc, &dcr_write_epcpc); 1441 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1442 &dcr_read_epcpc, &dcr_write_epcpc); 1443 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1444 &dcr_read_epcpc, &dcr_write_epcpc); 1445 #endif 1446 } 1447 1448 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1449 MemoryRegion ram_memories[2], 1450 hwaddr ram_bases[2], 1451 hwaddr ram_sizes[2], 1452 uint32_t sysclk, DeviceState **uicdevp, 1453 int do_init) 1454 { 1455 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1456 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1457 PowerPCCPU *cpu; 1458 CPUPPCState *env; 1459 DeviceState *uicdev; 1460 SysBusDevice *uicsbd; 1461 1462 memset(clk_setup, 0, sizeof(clk_setup)); 1463 /* init CPUs */ 1464 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1465 &clk_setup[PPC405EP_CPU_CLK], 1466 &tlb_clk_setup, sysclk); 1467 env = &cpu->env; 1468 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1469 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1470 /* Internal devices init */ 1471 /* Memory mapped devices registers */ 1472 /* PLB arbitrer */ 1473 ppc4xx_plb_init(env); 1474 /* PLB to OPB bridge */ 1475 ppc4xx_pob_init(env); 1476 /* OBP arbitrer */ 1477 ppc4xx_opba_init(0xef600600); 1478 /* Initialize timers */ 1479 ppc_booke_timers_init(cpu, sysclk, 0); 1480 /* Universal interrupt controller */ 1481 uicdev = qdev_new(TYPE_PPC_UIC); 1482 uicsbd = SYS_BUS_DEVICE(uicdev); 1483 1484 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 1485 &error_fatal); 1486 sysbus_realize_and_unref(uicsbd, &error_fatal); 1487 1488 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 1489 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 1490 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 1491 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 1492 1493 *uicdevp = uicdev; 1494 1495 /* SDRAM controller */ 1496 /* XXX 405EP has no ECC interrupt */ 1497 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, 1498 ram_bases, ram_sizes, do_init); 1499 /* External bus controller */ 1500 ppc405_ebc_init(env); 1501 /* DMA controller */ 1502 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5); 1503 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6); 1504 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7); 1505 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8); 1506 ppc405_dma_init(env, dma_irqs); 1507 /* IIC controller */ 1508 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, 1509 qdev_get_gpio_in(uicdev, 2)); 1510 /* GPIO */ 1511 ppc405_gpio_init(0xef600700); 1512 /* Serial ports */ 1513 if (serial_hd(0) != NULL) { 1514 serial_mm_init(address_space_mem, 0xef600300, 0, 1515 qdev_get_gpio_in(uicdev, 0), 1516 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1517 DEVICE_BIG_ENDIAN); 1518 } 1519 if (serial_hd(1) != NULL) { 1520 serial_mm_init(address_space_mem, 0xef600400, 0, 1521 qdev_get_gpio_in(uicdev, 1), 1522 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1523 DEVICE_BIG_ENDIAN); 1524 } 1525 /* OCM */ 1526 ppc405_ocm_init(env); 1527 /* GPT */ 1528 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19); 1529 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20); 1530 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21); 1531 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22); 1532 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23); 1533 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1534 /* PCI */ 1535 /* Uses UIC IRQs 3, 16, 18 */ 1536 /* MAL */ 1537 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11); 1538 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12); 1539 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13); 1540 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14); 1541 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1542 /* Ethernet */ 1543 /* Uses UIC IRQs 9, 15, 17 */ 1544 /* CPU control */ 1545 ppc405ep_cpc_init(env, clk_setup, sysclk); 1546 1547 return env; 1548 } 1549