1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "cpu.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "ppc405.h" 35 #include "hw/rtc/m48t59.h" 36 #include "hw/block/flash.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/block-backend.h" 40 #include "hw/boards.h" 41 #include "qemu/error-report.h" 42 #include "hw/loader.h" 43 #include "qemu/cutils.h" 44 #include "elf.h" 45 46 #define BIOS_FILENAME "ppc405_rom.bin" 47 #define BIOS_SIZE (2 * MiB) 48 49 #define KERNEL_LOAD_ADDR 0x01000000 50 #define INITRD_LOAD_ADDR 0x01800000 51 52 #define USE_FLASH_BIOS 53 54 /*****************************************************************************/ 55 /* PPC405EP reference board (IBM) */ 56 /* Standalone board with: 57 * - PowerPC 405EP CPU 58 * - SDRAM (0x00000000) 59 * - Flash (0xFFF80000) 60 * - SRAM (0xFFF00000) 61 * - NVRAM (0xF0000000) 62 * - FPGA (0xF0300000) 63 */ 64 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 65 struct ref405ep_fpga_t { 66 uint8_t reg0; 67 uint8_t reg1; 68 }; 69 70 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) 71 { 72 ref405ep_fpga_t *fpga; 73 uint32_t ret; 74 75 fpga = opaque; 76 switch (addr) { 77 case 0x0: 78 ret = fpga->reg0; 79 break; 80 case 0x1: 81 ret = fpga->reg1; 82 break; 83 default: 84 ret = 0; 85 break; 86 } 87 88 return ret; 89 } 90 91 static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, 92 unsigned size) 93 { 94 ref405ep_fpga_t *fpga; 95 96 fpga = opaque; 97 switch (addr) { 98 case 0x0: 99 /* Read only */ 100 break; 101 case 0x1: 102 fpga->reg1 = value; 103 break; 104 default: 105 break; 106 } 107 } 108 109 static const MemoryRegionOps ref405ep_fpga_ops = { 110 .read = ref405ep_fpga_readb, 111 .write = ref405ep_fpga_writeb, 112 .impl.min_access_size = 1, 113 .impl.max_access_size = 1, 114 .valid.min_access_size = 1, 115 .valid.max_access_size = 4, 116 .endianness = DEVICE_BIG_ENDIAN, 117 }; 118 119 static void ref405ep_fpga_reset (void *opaque) 120 { 121 ref405ep_fpga_t *fpga; 122 123 fpga = opaque; 124 fpga->reg0 = 0x00; 125 fpga->reg1 = 0x0F; 126 } 127 128 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 129 { 130 ref405ep_fpga_t *fpga; 131 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 132 133 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 134 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 135 "fpga", 0x00000100); 136 memory_region_add_subregion(sysmem, base, fpga_memory); 137 qemu_register_reset(&ref405ep_fpga_reset, fpga); 138 } 139 140 /* 141 * CPU reset handler when booting directly from a loaded kernel 142 */ 143 static struct boot_info { 144 uint32_t entry; 145 uint32_t bdloc; 146 uint32_t initrd_base; 147 uint32_t initrd_size; 148 uint32_t cmdline_base; 149 uint32_t cmdline_size; 150 } boot_info; 151 152 static void main_cpu_reset(void *opaque) 153 { 154 PowerPCCPU *cpu = opaque; 155 CPUPPCState *env = &cpu->env; 156 struct boot_info *bi = env->load_info; 157 158 cpu_reset(CPU(cpu)); 159 160 /* stack: top of sram */ 161 env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8; 162 163 /* Tune our boot state */ 164 env->gpr[3] = bi->bdloc; 165 env->gpr[4] = bi->initrd_base; 166 env->gpr[5] = bi->initrd_base + bi->initrd_size; 167 env->gpr[6] = bi->cmdline_base; 168 env->gpr[7] = bi->cmdline_size; 169 170 env->nip = bi->entry; 171 } 172 173 static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu) 174 { 175 CPUPPCState *env = &cpu->env; 176 hwaddr boot_entry; 177 hwaddr kernel_base; 178 int kernel_size; 179 hwaddr initrd_base; 180 int initrd_size; 181 ram_addr_t bdloc; 182 int len; 183 184 bdloc = ppc405_set_bootinfo(env, machine->ram_size); 185 boot_info.bdloc = bdloc; 186 187 kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL, 188 &boot_entry, &kernel_base, NULL, NULL, 189 1, PPC_ELF_MACHINE, 0, 0); 190 if (kernel_size < 0) { 191 error_report("Could not load kernel '%s' : %s", 192 machine->kernel_filename, load_elf_strerror(kernel_size)); 193 exit(1); 194 } 195 boot_info.entry = boot_entry; 196 197 /* load initrd */ 198 if (machine->initrd_filename) { 199 initrd_base = INITRD_LOAD_ADDR; 200 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 201 machine->ram_size - initrd_base); 202 if (initrd_size < 0) { 203 error_report("could not load initial ram disk '%s'", 204 machine->initrd_filename); 205 exit(1); 206 } 207 208 boot_info.initrd_base = initrd_base; 209 boot_info.initrd_size = initrd_size; 210 } 211 212 if (machine->kernel_cmdline) { 213 len = strlen(machine->kernel_cmdline); 214 bdloc -= ((len + 255) & ~255); 215 cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1); 216 boot_info.cmdline_base = bdloc; 217 boot_info.cmdline_size = bdloc + len; 218 } 219 220 /* Install our custom reset handler to start from Linux */ 221 qemu_register_reset(main_cpu_reset, cpu); 222 env->load_info = &boot_info; 223 } 224 225 static void ref405ep_init(MachineState *machine) 226 { 227 MachineClass *mc = MACHINE_GET_CLASS(machine); 228 const char *kernel_filename = machine->kernel_filename; 229 PowerPCCPU *cpu; 230 DeviceState *dev; 231 SysBusDevice *s; 232 MemoryRegion *sram = g_new(MemoryRegion, 1); 233 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 234 hwaddr ram_bases[2], ram_sizes[2]; 235 MemoryRegion *sysmem = get_system_memory(); 236 DeviceState *uicdev; 237 238 if (machine->ram_size != mc->default_ram_size) { 239 char *sz = size_to_str(mc->default_ram_size); 240 error_report("Invalid RAM size, should be %s", sz); 241 g_free(sz); 242 exit(EXIT_FAILURE); 243 } 244 245 /* XXX: fix this */ 246 memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias", 247 machine->ram, 0, machine->ram_size); 248 ram_bases[0] = 0; 249 ram_sizes[0] = machine->ram_size; 250 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 251 ram_bases[1] = 0x00000000; 252 ram_sizes[1] = 0x00000000; 253 254 cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 255 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); 256 257 /* allocate SRAM */ 258 memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, 259 &error_fatal); 260 memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); 261 262 /* allocate and load BIOS */ 263 if (machine->firmware) { 264 MemoryRegion *bios = g_new(MemoryRegion, 1); 265 g_autofree char *filename; 266 long bios_size; 267 268 memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, 269 &error_fatal); 270 271 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 272 if (!filename) { 273 error_report("Could not find firmware '%s'", machine->firmware); 274 exit(1); 275 } 276 277 bios_size = load_image_size(filename, 278 memory_region_get_ram_ptr(bios), 279 BIOS_SIZE); 280 if (bios_size < 0) { 281 error_report("Could not load PowerPC BIOS '%s'", machine->firmware); 282 exit(1); 283 } 284 285 bios_size = (bios_size + 0xfff) & ~0xfff; 286 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 287 } 288 289 /* Register FPGA */ 290 ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE); 291 /* Register NVRAM */ 292 dev = qdev_new("sysbus-m48t08"); 293 qdev_prop_set_int32(dev, "base-year", 1968); 294 s = SYS_BUS_DEVICE(dev); 295 sysbus_realize_and_unref(s, &error_fatal); 296 sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); 297 298 /* Load kernel and initrd using U-Boot images */ 299 if (kernel_filename && machine->firmware) { 300 target_ulong kernel_base, initrd_base; 301 long kernel_size, initrd_size; 302 303 kernel_base = KERNEL_LOAD_ADDR; 304 kernel_size = load_image_targphys(kernel_filename, kernel_base, 305 machine->ram_size - kernel_base); 306 if (kernel_size < 0) { 307 error_report("could not load kernel '%s'", kernel_filename); 308 exit(1); 309 } 310 311 /* load initrd */ 312 if (machine->initrd_filename) { 313 initrd_base = INITRD_LOAD_ADDR; 314 initrd_size = load_image_targphys(machine->initrd_filename, 315 initrd_base, 316 machine->ram_size - initrd_base); 317 if (initrd_size < 0) { 318 error_report("could not load initial ram disk '%s'", 319 machine->initrd_filename); 320 exit(1); 321 } 322 } 323 324 /* Load ELF kernel and rootfs.cpio */ 325 } else if (kernel_filename && !machine->firmware) { 326 boot_from_kernel(machine, cpu); 327 } 328 } 329 330 static void ref405ep_class_init(ObjectClass *oc, void *data) 331 { 332 MachineClass *mc = MACHINE_CLASS(oc); 333 334 mc->desc = "ref405ep"; 335 mc->init = ref405ep_init; 336 mc->default_ram_size = 0x08000000; 337 mc->default_ram_id = "ef405ep.ram"; 338 } 339 340 static const TypeInfo ref405ep_type = { 341 .name = MACHINE_TYPE_NAME("ref405ep"), 342 .parent = TYPE_MACHINE, 343 .class_init = ref405ep_class_init, 344 }; 345 346 /*****************************************************************************/ 347 /* AMCC Taihu evaluation board */ 348 /* - PowerPC 405EP processor 349 * - SDRAM 128 MB at 0x00000000 350 * - Boot flash 2 MB at 0xFFE00000 351 * - Application flash 32 MB at 0xFC000000 352 * - 2 serial ports 353 * - 2 ethernet PHY 354 * - 1 USB 1.1 device 0x50000000 355 * - 1 LCD display 0x50100000 356 * - 1 CPLD 0x50100000 357 * - 1 I2C EEPROM 358 * - 1 I2C thermal sensor 359 * - a set of LEDs 360 * - bit-bang SPI port using GPIOs 361 * - 1 EBC interface connector 0 0x50200000 362 * - 1 cardbus controller + expansion slot. 363 * - 1 PCI expansion slot. 364 */ 365 typedef struct taihu_cpld_t taihu_cpld_t; 366 struct taihu_cpld_t { 367 uint8_t reg0; 368 uint8_t reg1; 369 }; 370 371 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 372 { 373 taihu_cpld_t *cpld; 374 uint32_t ret; 375 376 cpld = opaque; 377 switch (addr) { 378 case 0x0: 379 ret = cpld->reg0; 380 break; 381 case 0x1: 382 ret = cpld->reg1; 383 break; 384 default: 385 ret = 0; 386 break; 387 } 388 389 return ret; 390 } 391 392 static void taihu_cpld_write(void *opaque, hwaddr addr, 393 uint64_t value, unsigned size) 394 { 395 taihu_cpld_t *cpld; 396 397 cpld = opaque; 398 switch (addr) { 399 case 0x0: 400 /* Read only */ 401 break; 402 case 0x1: 403 cpld->reg1 = value; 404 break; 405 default: 406 break; 407 } 408 } 409 410 static const MemoryRegionOps taihu_cpld_ops = { 411 .read = taihu_cpld_read, 412 .write = taihu_cpld_write, 413 .impl = { 414 .min_access_size = 1, 415 .max_access_size = 1, 416 }, 417 .endianness = DEVICE_NATIVE_ENDIAN, 418 }; 419 420 static void taihu_cpld_reset (void *opaque) 421 { 422 taihu_cpld_t *cpld; 423 424 cpld = opaque; 425 cpld->reg0 = 0x01; 426 cpld->reg1 = 0x80; 427 } 428 429 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 430 { 431 taihu_cpld_t *cpld; 432 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 433 434 cpld = g_malloc0(sizeof(taihu_cpld_t)); 435 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 436 memory_region_add_subregion(sysmem, base, cpld_memory); 437 qemu_register_reset(&taihu_cpld_reset, cpld); 438 } 439 440 static void taihu_405ep_init(MachineState *machine) 441 { 442 MachineClass *mc = MACHINE_GET_CLASS(machine); 443 const char *bios_name = machine->firmware ?: BIOS_FILENAME; 444 const char *kernel_filename = machine->kernel_filename; 445 const char *initrd_filename = machine->initrd_filename; 446 char *filename; 447 MemoryRegion *sysmem = get_system_memory(); 448 MemoryRegion *bios; 449 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 450 hwaddr ram_bases[2], ram_sizes[2]; 451 long bios_size; 452 target_ulong kernel_base, initrd_base; 453 long kernel_size, initrd_size; 454 int linux_boot; 455 int fl_idx; 456 DriveInfo *dinfo; 457 DeviceState *uicdev; 458 459 if (machine->ram_size != mc->default_ram_size) { 460 char *sz = size_to_str(mc->default_ram_size); 461 error_report("Invalid RAM size, should be %s", sz); 462 g_free(sz); 463 exit(EXIT_FAILURE); 464 } 465 466 ram_bases[0] = 0; 467 ram_sizes[0] = 0x04000000; 468 memory_region_init_alias(&ram_memories[0], NULL, 469 "taihu_405ep.ram-0", machine->ram, ram_bases[0], 470 ram_sizes[0]); 471 ram_bases[1] = 0x04000000; 472 ram_sizes[1] = 0x04000000; 473 memory_region_init_alias(&ram_memories[1], NULL, 474 "taihu_405ep.ram-1", machine->ram, ram_bases[1], 475 ram_sizes[1]); 476 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 477 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); 478 /* allocate and load BIOS */ 479 fl_idx = 0; 480 #if defined(USE_FLASH_BIOS) 481 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 482 if (dinfo) { 483 bios_size = 2 * MiB; 484 pflash_cfi02_register(0xFFE00000, 485 "taihu_405ep.bios", bios_size, 486 blk_by_legacy_dinfo(dinfo), 487 64 * KiB, 1, 488 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 489 1); 490 fl_idx++; 491 } else 492 #endif 493 { 494 bios = g_new(MemoryRegion, 1); 495 memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 496 &error_fatal); 497 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 498 if (filename) { 499 bios_size = load_image_size(filename, 500 memory_region_get_ram_ptr(bios), 501 BIOS_SIZE); 502 g_free(filename); 503 if (bios_size < 0) { 504 error_report("Could not load PowerPC BIOS '%s'", bios_name); 505 exit(1); 506 } 507 bios_size = (bios_size + 0xfff) & ~0xfff; 508 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 509 } else if (!qtest_enabled()) { 510 error_report("Could not load PowerPC BIOS '%s'", bios_name); 511 exit(1); 512 } 513 } 514 /* Register Linux flash */ 515 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 516 if (dinfo) { 517 bios_size = 32 * MiB; 518 pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size, 519 blk_by_legacy_dinfo(dinfo), 520 64 * KiB, 1, 521 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 522 1); 523 fl_idx++; 524 } 525 /* Register CLPD & LCD display */ 526 taihu_cpld_init(sysmem, 0x50100000); 527 /* Load kernel */ 528 linux_boot = (kernel_filename != NULL); 529 if (linux_boot) { 530 kernel_base = KERNEL_LOAD_ADDR; 531 /* now we can load the kernel */ 532 kernel_size = load_image_targphys(kernel_filename, kernel_base, 533 machine->ram_size - kernel_base); 534 if (kernel_size < 0) { 535 error_report("could not load kernel '%s'", kernel_filename); 536 exit(1); 537 } 538 /* load initrd */ 539 if (initrd_filename) { 540 initrd_base = INITRD_LOAD_ADDR; 541 initrd_size = load_image_targphys(initrd_filename, initrd_base, 542 machine->ram_size - initrd_base); 543 if (initrd_size < 0) { 544 error_report("could not load initial ram disk '%s'", 545 initrd_filename); 546 exit(1); 547 } 548 } else { 549 initrd_base = 0; 550 initrd_size = 0; 551 } 552 } else { 553 kernel_base = 0; 554 kernel_size = 0; 555 initrd_base = 0; 556 initrd_size = 0; 557 } 558 } 559 560 static void taihu_class_init(ObjectClass *oc, void *data) 561 { 562 MachineClass *mc = MACHINE_CLASS(oc); 563 564 mc->desc = "taihu"; 565 mc->init = taihu_405ep_init; 566 mc->default_ram_size = 0x08000000; 567 mc->default_ram_id = "taihu_405ep.ram"; 568 mc->deprecation_reason = "incomplete, use 'ref405ep' instead"; 569 } 570 571 static const TypeInfo taihu_type = { 572 .name = MACHINE_TYPE_NAME("taihu"), 573 .parent = TYPE_MACHINE, 574 .class_init = taihu_class_init, 575 }; 576 577 static void ppc405_machine_init(void) 578 { 579 type_register_static(&ref405ep_type); 580 type_register_static(&taihu_type); 581 } 582 583 type_init(ppc405_machine_init) 584