1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "ppc405.h" 31 #include "hw/timer/m48t59.h" 32 #include "hw/block/flash.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/block-backend.h" 36 #include "hw/boards.h" 37 #include "qemu/log.h" 38 #include "qemu/error-report.h" 39 #include "hw/loader.h" 40 #include "sysemu/block-backend.h" 41 #include "sysemu/blockdev.h" 42 #include "exec/address-spaces.h" 43 44 #define BIOS_FILENAME "ppc405_rom.bin" 45 #define BIOS_SIZE (2048 * 1024) 46 47 #define KERNEL_LOAD_ADDR 0x00000000 48 #define INITRD_LOAD_ADDR 0x01800000 49 50 #define USE_FLASH_BIOS 51 52 //#define DEBUG_BOARD_INIT 53 54 /*****************************************************************************/ 55 /* PPC405EP reference board (IBM) */ 56 /* Standalone board with: 57 * - PowerPC 405EP CPU 58 * - SDRAM (0x00000000) 59 * - Flash (0xFFF80000) 60 * - SRAM (0xFFF00000) 61 * - NVRAM (0xF0000000) 62 * - FPGA (0xF0300000) 63 */ 64 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 65 struct ref405ep_fpga_t { 66 uint8_t reg0; 67 uint8_t reg1; 68 }; 69 70 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 71 { 72 ref405ep_fpga_t *fpga; 73 uint32_t ret; 74 75 fpga = opaque; 76 switch (addr) { 77 case 0x0: 78 ret = fpga->reg0; 79 break; 80 case 0x1: 81 ret = fpga->reg1; 82 break; 83 default: 84 ret = 0; 85 break; 86 } 87 88 return ret; 89 } 90 91 static void ref405ep_fpga_writeb (void *opaque, 92 hwaddr addr, uint32_t value) 93 { 94 ref405ep_fpga_t *fpga; 95 96 fpga = opaque; 97 switch (addr) { 98 case 0x0: 99 /* Read only */ 100 break; 101 case 0x1: 102 fpga->reg1 = value; 103 break; 104 default: 105 break; 106 } 107 } 108 109 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 110 { 111 uint32_t ret; 112 113 ret = ref405ep_fpga_readb(opaque, addr) << 8; 114 ret |= ref405ep_fpga_readb(opaque, addr + 1); 115 116 return ret; 117 } 118 119 static void ref405ep_fpga_writew (void *opaque, 120 hwaddr addr, uint32_t value) 121 { 122 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 123 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 124 } 125 126 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 127 { 128 uint32_t ret; 129 130 ret = ref405ep_fpga_readb(opaque, addr) << 24; 131 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 132 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 133 ret |= ref405ep_fpga_readb(opaque, addr + 3); 134 135 return ret; 136 } 137 138 static void ref405ep_fpga_writel (void *opaque, 139 hwaddr addr, uint32_t value) 140 { 141 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 142 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 143 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 144 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 145 } 146 147 static const MemoryRegionOps ref405ep_fpga_ops = { 148 .old_mmio = { 149 .read = { 150 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 151 }, 152 .write = { 153 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 154 }, 155 }, 156 .endianness = DEVICE_NATIVE_ENDIAN, 157 }; 158 159 static void ref405ep_fpga_reset (void *opaque) 160 { 161 ref405ep_fpga_t *fpga; 162 163 fpga = opaque; 164 fpga->reg0 = 0x00; 165 fpga->reg1 = 0x0F; 166 } 167 168 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 169 { 170 ref405ep_fpga_t *fpga; 171 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 172 173 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 174 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 175 "fpga", 0x00000100); 176 memory_region_add_subregion(sysmem, base, fpga_memory); 177 qemu_register_reset(&ref405ep_fpga_reset, fpga); 178 } 179 180 static void ref405ep_init(MachineState *machine) 181 { 182 ram_addr_t ram_size = machine->ram_size; 183 const char *kernel_filename = machine->kernel_filename; 184 const char *kernel_cmdline = machine->kernel_cmdline; 185 const char *initrd_filename = machine->initrd_filename; 186 char *filename; 187 ppc4xx_bd_info_t bd; 188 CPUPPCState *env; 189 qemu_irq *pic; 190 MemoryRegion *bios; 191 MemoryRegion *sram = g_new(MemoryRegion, 1); 192 ram_addr_t bdloc; 193 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 194 hwaddr ram_bases[2], ram_sizes[2]; 195 target_ulong sram_size; 196 long bios_size; 197 //int phy_addr = 0; 198 //static int phy_addr = 1; 199 target_ulong kernel_base, initrd_base; 200 long kernel_size, initrd_size; 201 int linux_boot; 202 int fl_idx, fl_sectors, len; 203 DriveInfo *dinfo; 204 MemoryRegion *sysmem = get_system_memory(); 205 206 /* XXX: fix this */ 207 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 208 0x08000000); 209 ram_bases[0] = 0; 210 ram_sizes[0] = 0x08000000; 211 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 212 ram_bases[1] = 0x00000000; 213 ram_sizes[1] = 0x00000000; 214 ram_size = 128 * 1024 * 1024; 215 #ifdef DEBUG_BOARD_INIT 216 printf("%s: register cpu\n", __func__); 217 #endif 218 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 219 33333333, &pic, kernel_filename == NULL ? 0 : 1); 220 /* allocate SRAM */ 221 sram_size = 512 * 1024; 222 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 223 &error_fatal); 224 vmstate_register_ram_global(sram); 225 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 226 /* allocate and load BIOS */ 227 #ifdef DEBUG_BOARD_INIT 228 printf("%s: register BIOS\n", __func__); 229 #endif 230 fl_idx = 0; 231 #ifdef USE_FLASH_BIOS 232 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 233 if (dinfo) { 234 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 235 236 bios_size = blk_getlength(blk); 237 fl_sectors = (bios_size + 65535) >> 16; 238 #ifdef DEBUG_BOARD_INIT 239 printf("Register parallel flash %d size %lx" 240 " at addr %lx '%s' %d\n", 241 fl_idx, bios_size, -bios_size, 242 blk_name(blk), fl_sectors); 243 #endif 244 pflash_cfi02_register((uint32_t)(-bios_size), 245 NULL, "ef405ep.bios", bios_size, 246 blk, 65536, fl_sectors, 1, 247 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 248 1); 249 fl_idx++; 250 } else 251 #endif 252 { 253 #ifdef DEBUG_BOARD_INIT 254 printf("Load BIOS from file\n"); 255 #endif 256 bios = g_new(MemoryRegion, 1); 257 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 258 &error_fatal); 259 vmstate_register_ram_global(bios); 260 261 if (bios_name == NULL) 262 bios_name = BIOS_FILENAME; 263 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 264 if (filename) { 265 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 266 g_free(filename); 267 if (bios_size < 0 || bios_size > BIOS_SIZE) { 268 error_report("Could not load PowerPC BIOS '%s'", bios_name); 269 exit(1); 270 } 271 bios_size = (bios_size + 0xfff) & ~0xfff; 272 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 273 } else if (!qtest_enabled() || kernel_filename != NULL) { 274 error_report("Could not load PowerPC BIOS '%s'", bios_name); 275 exit(1); 276 } else { 277 /* Avoid an uninitialized variable warning */ 278 bios_size = -1; 279 } 280 memory_region_set_readonly(bios, true); 281 } 282 /* Register FPGA */ 283 #ifdef DEBUG_BOARD_INIT 284 printf("%s: register FPGA\n", __func__); 285 #endif 286 ref405ep_fpga_init(sysmem, 0xF0300000); 287 /* Register NVRAM */ 288 #ifdef DEBUG_BOARD_INIT 289 printf("%s: register NVRAM\n", __func__); 290 #endif 291 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 292 /* Load kernel */ 293 linux_boot = (kernel_filename != NULL); 294 if (linux_boot) { 295 #ifdef DEBUG_BOARD_INIT 296 printf("%s: load kernel\n", __func__); 297 #endif 298 memset(&bd, 0, sizeof(bd)); 299 bd.bi_memstart = 0x00000000; 300 bd.bi_memsize = ram_size; 301 bd.bi_flashstart = -bios_size; 302 bd.bi_flashsize = -bios_size; 303 bd.bi_flashoffset = 0; 304 bd.bi_sramstart = 0xFFF00000; 305 bd.bi_sramsize = sram_size; 306 bd.bi_bootflags = 0; 307 bd.bi_intfreq = 133333333; 308 bd.bi_busfreq = 33333333; 309 bd.bi_baudrate = 115200; 310 bd.bi_s_version[0] = 'Q'; 311 bd.bi_s_version[1] = 'M'; 312 bd.bi_s_version[2] = 'U'; 313 bd.bi_s_version[3] = '\0'; 314 bd.bi_r_version[0] = 'Q'; 315 bd.bi_r_version[1] = 'E'; 316 bd.bi_r_version[2] = 'M'; 317 bd.bi_r_version[3] = 'U'; 318 bd.bi_r_version[4] = '\0'; 319 bd.bi_procfreq = 133333333; 320 bd.bi_plb_busfreq = 33333333; 321 bd.bi_pci_busfreq = 33333333; 322 bd.bi_opbfreq = 33333333; 323 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 324 env->gpr[3] = bdloc; 325 kernel_base = KERNEL_LOAD_ADDR; 326 /* now we can load the kernel */ 327 kernel_size = load_image_targphys(kernel_filename, kernel_base, 328 ram_size - kernel_base); 329 if (kernel_size < 0) { 330 fprintf(stderr, "qemu: could not load kernel '%s'\n", 331 kernel_filename); 332 exit(1); 333 } 334 printf("Load kernel size %ld at " TARGET_FMT_lx, 335 kernel_size, kernel_base); 336 /* load initrd */ 337 if (initrd_filename) { 338 initrd_base = INITRD_LOAD_ADDR; 339 initrd_size = load_image_targphys(initrd_filename, initrd_base, 340 ram_size - initrd_base); 341 if (initrd_size < 0) { 342 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 343 initrd_filename); 344 exit(1); 345 } 346 } else { 347 initrd_base = 0; 348 initrd_size = 0; 349 } 350 env->gpr[4] = initrd_base; 351 env->gpr[5] = initrd_size; 352 if (kernel_cmdline != NULL) { 353 len = strlen(kernel_cmdline); 354 bdloc -= ((len + 255) & ~255); 355 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 356 env->gpr[6] = bdloc; 357 env->gpr[7] = bdloc + len; 358 } else { 359 env->gpr[6] = 0; 360 env->gpr[7] = 0; 361 } 362 env->nip = KERNEL_LOAD_ADDR; 363 } else { 364 kernel_base = 0; 365 kernel_size = 0; 366 initrd_base = 0; 367 initrd_size = 0; 368 bdloc = 0; 369 } 370 #ifdef DEBUG_BOARD_INIT 371 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 372 printf("%s: Done\n", __func__); 373 #endif 374 } 375 376 static void ref405ep_class_init(ObjectClass *oc, void *data) 377 { 378 MachineClass *mc = MACHINE_CLASS(oc); 379 380 mc->desc = "ref405ep"; 381 mc->init = ref405ep_init; 382 } 383 384 static const TypeInfo ref405ep_type = { 385 .name = MACHINE_TYPE_NAME("ref405ep"), 386 .parent = TYPE_MACHINE, 387 .class_init = ref405ep_class_init, 388 }; 389 390 /*****************************************************************************/ 391 /* AMCC Taihu evaluation board */ 392 /* - PowerPC 405EP processor 393 * - SDRAM 128 MB at 0x00000000 394 * - Boot flash 2 MB at 0xFFE00000 395 * - Application flash 32 MB at 0xFC000000 396 * - 2 serial ports 397 * - 2 ethernet PHY 398 * - 1 USB 1.1 device 0x50000000 399 * - 1 LCD display 0x50100000 400 * - 1 CPLD 0x50100000 401 * - 1 I2C EEPROM 402 * - 1 I2C thermal sensor 403 * - a set of LEDs 404 * - bit-bang SPI port using GPIOs 405 * - 1 EBC interface connector 0 0x50200000 406 * - 1 cardbus controller + expansion slot. 407 * - 1 PCI expansion slot. 408 */ 409 typedef struct taihu_cpld_t taihu_cpld_t; 410 struct taihu_cpld_t { 411 uint8_t reg0; 412 uint8_t reg1; 413 }; 414 415 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 416 { 417 taihu_cpld_t *cpld; 418 uint32_t ret; 419 420 cpld = opaque; 421 switch (addr) { 422 case 0x0: 423 ret = cpld->reg0; 424 break; 425 case 0x1: 426 ret = cpld->reg1; 427 break; 428 default: 429 ret = 0; 430 break; 431 } 432 433 return ret; 434 } 435 436 static void taihu_cpld_write(void *opaque, hwaddr addr, 437 uint64_t value, unsigned size) 438 { 439 taihu_cpld_t *cpld; 440 441 cpld = opaque; 442 switch (addr) { 443 case 0x0: 444 /* Read only */ 445 break; 446 case 0x1: 447 cpld->reg1 = value; 448 break; 449 default: 450 break; 451 } 452 } 453 454 static const MemoryRegionOps taihu_cpld_ops = { 455 .read = taihu_cpld_read, 456 .write = taihu_cpld_write, 457 .impl = { 458 .min_access_size = 1, 459 .max_access_size = 1, 460 }, 461 .endianness = DEVICE_NATIVE_ENDIAN, 462 }; 463 464 static void taihu_cpld_reset (void *opaque) 465 { 466 taihu_cpld_t *cpld; 467 468 cpld = opaque; 469 cpld->reg0 = 0x01; 470 cpld->reg1 = 0x80; 471 } 472 473 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 474 { 475 taihu_cpld_t *cpld; 476 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 477 478 cpld = g_malloc0(sizeof(taihu_cpld_t)); 479 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 480 memory_region_add_subregion(sysmem, base, cpld_memory); 481 qemu_register_reset(&taihu_cpld_reset, cpld); 482 } 483 484 static void taihu_405ep_init(MachineState *machine) 485 { 486 ram_addr_t ram_size = machine->ram_size; 487 const char *kernel_filename = machine->kernel_filename; 488 const char *initrd_filename = machine->initrd_filename; 489 char *filename; 490 qemu_irq *pic; 491 MemoryRegion *sysmem = get_system_memory(); 492 MemoryRegion *bios; 493 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 494 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 495 hwaddr ram_bases[2], ram_sizes[2]; 496 long bios_size; 497 target_ulong kernel_base, initrd_base; 498 long kernel_size, initrd_size; 499 int linux_boot; 500 int fl_idx, fl_sectors; 501 DriveInfo *dinfo; 502 503 /* RAM is soldered to the board so the size cannot be changed */ 504 ram_size = 0x08000000; 505 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 506 ram_size); 507 508 ram_bases[0] = 0; 509 ram_sizes[0] = 0x04000000; 510 memory_region_init_alias(&ram_memories[0], NULL, 511 "taihu_405ep.ram-0", ram, ram_bases[0], 512 ram_sizes[0]); 513 ram_bases[1] = 0x04000000; 514 ram_sizes[1] = 0x04000000; 515 memory_region_init_alias(&ram_memories[1], NULL, 516 "taihu_405ep.ram-1", ram, ram_bases[1], 517 ram_sizes[1]); 518 #ifdef DEBUG_BOARD_INIT 519 printf("%s: register cpu\n", __func__); 520 #endif 521 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 522 33333333, &pic, kernel_filename == NULL ? 0 : 1); 523 /* allocate and load BIOS */ 524 #ifdef DEBUG_BOARD_INIT 525 printf("%s: register BIOS\n", __func__); 526 #endif 527 fl_idx = 0; 528 #if defined(USE_FLASH_BIOS) 529 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 530 if (dinfo) { 531 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 532 533 bios_size = blk_getlength(blk); 534 /* XXX: should check that size is 2MB */ 535 // bios_size = 2 * 1024 * 1024; 536 fl_sectors = (bios_size + 65535) >> 16; 537 #ifdef DEBUG_BOARD_INIT 538 printf("Register parallel flash %d size %lx" 539 " at addr %lx '%s' %d\n", 540 fl_idx, bios_size, -bios_size, 541 blk_name(blk), fl_sectors); 542 #endif 543 pflash_cfi02_register((uint32_t)(-bios_size), 544 NULL, "taihu_405ep.bios", bios_size, 545 blk, 65536, fl_sectors, 1, 546 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 547 1); 548 fl_idx++; 549 } else 550 #endif 551 { 552 #ifdef DEBUG_BOARD_INIT 553 printf("Load BIOS from file\n"); 554 #endif 555 if (bios_name == NULL) 556 bios_name = BIOS_FILENAME; 557 bios = g_new(MemoryRegion, 1); 558 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 559 &error_fatal); 560 vmstate_register_ram_global(bios); 561 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 562 if (filename) { 563 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 564 g_free(filename); 565 if (bios_size < 0 || bios_size > BIOS_SIZE) { 566 error_report("Could not load PowerPC BIOS '%s'", bios_name); 567 exit(1); 568 } 569 bios_size = (bios_size + 0xfff) & ~0xfff; 570 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 571 } else if (!qtest_enabled()) { 572 error_report("Could not load PowerPC BIOS '%s'", bios_name); 573 exit(1); 574 } 575 memory_region_set_readonly(bios, true); 576 } 577 /* Register Linux flash */ 578 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 579 if (dinfo) { 580 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 581 582 bios_size = blk_getlength(blk); 583 /* XXX: should check that size is 32MB */ 584 bios_size = 32 * 1024 * 1024; 585 fl_sectors = (bios_size + 65535) >> 16; 586 #ifdef DEBUG_BOARD_INIT 587 printf("Register parallel flash %d size %lx" 588 " at addr " TARGET_FMT_lx " '%s'\n", 589 fl_idx, bios_size, (target_ulong)0xfc000000, 590 blk_name(blk)); 591 #endif 592 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 593 blk, 65536, fl_sectors, 1, 594 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 595 1); 596 fl_idx++; 597 } 598 /* Register CLPD & LCD display */ 599 #ifdef DEBUG_BOARD_INIT 600 printf("%s: register CPLD\n", __func__); 601 #endif 602 taihu_cpld_init(sysmem, 0x50100000); 603 /* Load kernel */ 604 linux_boot = (kernel_filename != NULL); 605 if (linux_boot) { 606 #ifdef DEBUG_BOARD_INIT 607 printf("%s: load kernel\n", __func__); 608 #endif 609 kernel_base = KERNEL_LOAD_ADDR; 610 /* now we can load the kernel */ 611 kernel_size = load_image_targphys(kernel_filename, kernel_base, 612 ram_size - kernel_base); 613 if (kernel_size < 0) { 614 fprintf(stderr, "qemu: could not load kernel '%s'\n", 615 kernel_filename); 616 exit(1); 617 } 618 /* load initrd */ 619 if (initrd_filename) { 620 initrd_base = INITRD_LOAD_ADDR; 621 initrd_size = load_image_targphys(initrd_filename, initrd_base, 622 ram_size - initrd_base); 623 if (initrd_size < 0) { 624 fprintf(stderr, 625 "qemu: could not load initial ram disk '%s'\n", 626 initrd_filename); 627 exit(1); 628 } 629 } else { 630 initrd_base = 0; 631 initrd_size = 0; 632 } 633 } else { 634 kernel_base = 0; 635 kernel_size = 0; 636 initrd_base = 0; 637 initrd_size = 0; 638 } 639 #ifdef DEBUG_BOARD_INIT 640 printf("%s: Done\n", __func__); 641 #endif 642 } 643 644 static void taihu_class_init(ObjectClass *oc, void *data) 645 { 646 MachineClass *mc = MACHINE_CLASS(oc); 647 648 mc->desc = "taihu"; 649 mc->init = taihu_405ep_init; 650 } 651 652 static const TypeInfo taihu_type = { 653 .name = MACHINE_TYPE_NAME("taihu"), 654 .parent = TYPE_MACHINE, 655 .class_init = taihu_class_init, 656 }; 657 658 static void ppc405_machine_init(void) 659 { 660 type_register_static(&ref405ep_type); 661 type_register_static(&taihu_type); 662 } 663 664 type_init(ppc405_machine_init) 665