1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "ppc405.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/qtest.h" 31 #include "sysemu/block-backend.h" 32 #include "hw/boards.h" 33 #include "qemu/log.h" 34 #include "qemu/error-report.h" 35 #include "hw/loader.h" 36 #include "sysemu/block-backend.h" 37 #include "sysemu/blockdev.h" 38 #include "exec/address-spaces.h" 39 40 #define BIOS_FILENAME "ppc405_rom.bin" 41 #define BIOS_SIZE (2048 * 1024) 42 43 #define KERNEL_LOAD_ADDR 0x00000000 44 #define INITRD_LOAD_ADDR 0x01800000 45 46 #define USE_FLASH_BIOS 47 48 //#define DEBUG_BOARD_INIT 49 50 /*****************************************************************************/ 51 /* PPC405EP reference board (IBM) */ 52 /* Standalone board with: 53 * - PowerPC 405EP CPU 54 * - SDRAM (0x00000000) 55 * - Flash (0xFFF80000) 56 * - SRAM (0xFFF00000) 57 * - NVRAM (0xF0000000) 58 * - FPGA (0xF0300000) 59 */ 60 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 61 struct ref405ep_fpga_t { 62 uint8_t reg0; 63 uint8_t reg1; 64 }; 65 66 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 67 { 68 ref405ep_fpga_t *fpga; 69 uint32_t ret; 70 71 fpga = opaque; 72 switch (addr) { 73 case 0x0: 74 ret = fpga->reg0; 75 break; 76 case 0x1: 77 ret = fpga->reg1; 78 break; 79 default: 80 ret = 0; 81 break; 82 } 83 84 return ret; 85 } 86 87 static void ref405ep_fpga_writeb (void *opaque, 88 hwaddr addr, uint32_t value) 89 { 90 ref405ep_fpga_t *fpga; 91 92 fpga = opaque; 93 switch (addr) { 94 case 0x0: 95 /* Read only */ 96 break; 97 case 0x1: 98 fpga->reg1 = value; 99 break; 100 default: 101 break; 102 } 103 } 104 105 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 106 { 107 uint32_t ret; 108 109 ret = ref405ep_fpga_readb(opaque, addr) << 8; 110 ret |= ref405ep_fpga_readb(opaque, addr + 1); 111 112 return ret; 113 } 114 115 static void ref405ep_fpga_writew (void *opaque, 116 hwaddr addr, uint32_t value) 117 { 118 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 119 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 120 } 121 122 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 123 { 124 uint32_t ret; 125 126 ret = ref405ep_fpga_readb(opaque, addr) << 24; 127 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 128 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 129 ret |= ref405ep_fpga_readb(opaque, addr + 3); 130 131 return ret; 132 } 133 134 static void ref405ep_fpga_writel (void *opaque, 135 hwaddr addr, uint32_t value) 136 { 137 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 138 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 139 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 140 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 141 } 142 143 static const MemoryRegionOps ref405ep_fpga_ops = { 144 .old_mmio = { 145 .read = { 146 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 147 }, 148 .write = { 149 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 150 }, 151 }, 152 .endianness = DEVICE_NATIVE_ENDIAN, 153 }; 154 155 static void ref405ep_fpga_reset (void *opaque) 156 { 157 ref405ep_fpga_t *fpga; 158 159 fpga = opaque; 160 fpga->reg0 = 0x00; 161 fpga->reg1 = 0x0F; 162 } 163 164 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 165 { 166 ref405ep_fpga_t *fpga; 167 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 168 169 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 170 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 171 "fpga", 0x00000100); 172 memory_region_add_subregion(sysmem, base, fpga_memory); 173 qemu_register_reset(&ref405ep_fpga_reset, fpga); 174 } 175 176 static void ref405ep_init(MachineState *machine) 177 { 178 ram_addr_t ram_size = machine->ram_size; 179 const char *kernel_filename = machine->kernel_filename; 180 const char *kernel_cmdline = machine->kernel_cmdline; 181 const char *initrd_filename = machine->initrd_filename; 182 char *filename; 183 ppc4xx_bd_info_t bd; 184 CPUPPCState *env; 185 qemu_irq *pic; 186 MemoryRegion *bios; 187 MemoryRegion *sram = g_new(MemoryRegion, 1); 188 ram_addr_t bdloc; 189 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 190 hwaddr ram_bases[2], ram_sizes[2]; 191 target_ulong sram_size; 192 long bios_size; 193 //int phy_addr = 0; 194 //static int phy_addr = 1; 195 target_ulong kernel_base, initrd_base; 196 long kernel_size, initrd_size; 197 int linux_boot; 198 int fl_idx, fl_sectors, len; 199 DriveInfo *dinfo; 200 MemoryRegion *sysmem = get_system_memory(); 201 202 /* XXX: fix this */ 203 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 204 0x08000000); 205 ram_bases[0] = 0; 206 ram_sizes[0] = 0x08000000; 207 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 208 ram_bases[1] = 0x00000000; 209 ram_sizes[1] = 0x00000000; 210 ram_size = 128 * 1024 * 1024; 211 #ifdef DEBUG_BOARD_INIT 212 printf("%s: register cpu\n", __func__); 213 #endif 214 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 215 33333333, &pic, kernel_filename == NULL ? 0 : 1); 216 /* allocate SRAM */ 217 sram_size = 512 * 1024; 218 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, &error_abort); 219 vmstate_register_ram_global(sram); 220 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 221 /* allocate and load BIOS */ 222 #ifdef DEBUG_BOARD_INIT 223 printf("%s: register BIOS\n", __func__); 224 #endif 225 fl_idx = 0; 226 #ifdef USE_FLASH_BIOS 227 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 228 if (dinfo) { 229 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 230 231 bios_size = blk_getlength(blk); 232 fl_sectors = (bios_size + 65535) >> 16; 233 #ifdef DEBUG_BOARD_INIT 234 printf("Register parallel flash %d size %lx" 235 " at addr %lx '%s' %d\n", 236 fl_idx, bios_size, -bios_size, 237 blk_name(blk), fl_sectors); 238 #endif 239 pflash_cfi02_register((uint32_t)(-bios_size), 240 NULL, "ef405ep.bios", bios_size, 241 blk, 65536, fl_sectors, 1, 242 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 243 1); 244 fl_idx++; 245 } else 246 #endif 247 { 248 #ifdef DEBUG_BOARD_INIT 249 printf("Load BIOS from file\n"); 250 #endif 251 bios = g_new(MemoryRegion, 1); 252 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 253 &error_abort); 254 vmstate_register_ram_global(bios); 255 256 if (bios_name == NULL) 257 bios_name = BIOS_FILENAME; 258 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 259 if (filename) { 260 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 261 g_free(filename); 262 if (bios_size < 0 || bios_size > BIOS_SIZE) { 263 error_report("Could not load PowerPC BIOS '%s'", bios_name); 264 exit(1); 265 } 266 bios_size = (bios_size + 0xfff) & ~0xfff; 267 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 268 } else if (!qtest_enabled() || kernel_filename != NULL) { 269 error_report("Could not load PowerPC BIOS '%s'", bios_name); 270 exit(1); 271 } else { 272 /* Avoid an uninitialized variable warning */ 273 bios_size = -1; 274 } 275 memory_region_set_readonly(bios, true); 276 } 277 /* Register FPGA */ 278 #ifdef DEBUG_BOARD_INIT 279 printf("%s: register FPGA\n", __func__); 280 #endif 281 ref405ep_fpga_init(sysmem, 0xF0300000); 282 /* Register NVRAM */ 283 #ifdef DEBUG_BOARD_INIT 284 printf("%s: register NVRAM\n", __func__); 285 #endif 286 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 287 /* Load kernel */ 288 linux_boot = (kernel_filename != NULL); 289 if (linux_boot) { 290 #ifdef DEBUG_BOARD_INIT 291 printf("%s: load kernel\n", __func__); 292 #endif 293 memset(&bd, 0, sizeof(bd)); 294 bd.bi_memstart = 0x00000000; 295 bd.bi_memsize = ram_size; 296 bd.bi_flashstart = -bios_size; 297 bd.bi_flashsize = -bios_size; 298 bd.bi_flashoffset = 0; 299 bd.bi_sramstart = 0xFFF00000; 300 bd.bi_sramsize = sram_size; 301 bd.bi_bootflags = 0; 302 bd.bi_intfreq = 133333333; 303 bd.bi_busfreq = 33333333; 304 bd.bi_baudrate = 115200; 305 bd.bi_s_version[0] = 'Q'; 306 bd.bi_s_version[1] = 'M'; 307 bd.bi_s_version[2] = 'U'; 308 bd.bi_s_version[3] = '\0'; 309 bd.bi_r_version[0] = 'Q'; 310 bd.bi_r_version[1] = 'E'; 311 bd.bi_r_version[2] = 'M'; 312 bd.bi_r_version[3] = 'U'; 313 bd.bi_r_version[4] = '\0'; 314 bd.bi_procfreq = 133333333; 315 bd.bi_plb_busfreq = 33333333; 316 bd.bi_pci_busfreq = 33333333; 317 bd.bi_opbfreq = 33333333; 318 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 319 env->gpr[3] = bdloc; 320 kernel_base = KERNEL_LOAD_ADDR; 321 /* now we can load the kernel */ 322 kernel_size = load_image_targphys(kernel_filename, kernel_base, 323 ram_size - kernel_base); 324 if (kernel_size < 0) { 325 fprintf(stderr, "qemu: could not load kernel '%s'\n", 326 kernel_filename); 327 exit(1); 328 } 329 printf("Load kernel size %ld at " TARGET_FMT_lx, 330 kernel_size, kernel_base); 331 /* load initrd */ 332 if (initrd_filename) { 333 initrd_base = INITRD_LOAD_ADDR; 334 initrd_size = load_image_targphys(initrd_filename, initrd_base, 335 ram_size - initrd_base); 336 if (initrd_size < 0) { 337 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 338 initrd_filename); 339 exit(1); 340 } 341 } else { 342 initrd_base = 0; 343 initrd_size = 0; 344 } 345 env->gpr[4] = initrd_base; 346 env->gpr[5] = initrd_size; 347 if (kernel_cmdline != NULL) { 348 len = strlen(kernel_cmdline); 349 bdloc -= ((len + 255) & ~255); 350 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 351 env->gpr[6] = bdloc; 352 env->gpr[7] = bdloc + len; 353 } else { 354 env->gpr[6] = 0; 355 env->gpr[7] = 0; 356 } 357 env->nip = KERNEL_LOAD_ADDR; 358 } else { 359 kernel_base = 0; 360 kernel_size = 0; 361 initrd_base = 0; 362 initrd_size = 0; 363 bdloc = 0; 364 } 365 #ifdef DEBUG_BOARD_INIT 366 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 367 printf("%s: Done\n", __func__); 368 #endif 369 } 370 371 static QEMUMachine ref405ep_machine = { 372 .name = "ref405ep", 373 .desc = "ref405ep", 374 .init = ref405ep_init, 375 }; 376 377 /*****************************************************************************/ 378 /* AMCC Taihu evaluation board */ 379 /* - PowerPC 405EP processor 380 * - SDRAM 128 MB at 0x00000000 381 * - Boot flash 2 MB at 0xFFE00000 382 * - Application flash 32 MB at 0xFC000000 383 * - 2 serial ports 384 * - 2 ethernet PHY 385 * - 1 USB 1.1 device 0x50000000 386 * - 1 LCD display 0x50100000 387 * - 1 CPLD 0x50100000 388 * - 1 I2C EEPROM 389 * - 1 I2C thermal sensor 390 * - a set of LEDs 391 * - bit-bang SPI port using GPIOs 392 * - 1 EBC interface connector 0 0x50200000 393 * - 1 cardbus controller + expansion slot. 394 * - 1 PCI expansion slot. 395 */ 396 typedef struct taihu_cpld_t taihu_cpld_t; 397 struct taihu_cpld_t { 398 uint8_t reg0; 399 uint8_t reg1; 400 }; 401 402 static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr) 403 { 404 taihu_cpld_t *cpld; 405 uint32_t ret; 406 407 cpld = opaque; 408 switch (addr) { 409 case 0x0: 410 ret = cpld->reg0; 411 break; 412 case 0x1: 413 ret = cpld->reg1; 414 break; 415 default: 416 ret = 0; 417 break; 418 } 419 420 return ret; 421 } 422 423 static void taihu_cpld_writeb (void *opaque, 424 hwaddr addr, uint32_t value) 425 { 426 taihu_cpld_t *cpld; 427 428 cpld = opaque; 429 switch (addr) { 430 case 0x0: 431 /* Read only */ 432 break; 433 case 0x1: 434 cpld->reg1 = value; 435 break; 436 default: 437 break; 438 } 439 } 440 441 static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr) 442 { 443 uint32_t ret; 444 445 ret = taihu_cpld_readb(opaque, addr) << 8; 446 ret |= taihu_cpld_readb(opaque, addr + 1); 447 448 return ret; 449 } 450 451 static void taihu_cpld_writew (void *opaque, 452 hwaddr addr, uint32_t value) 453 { 454 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); 455 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); 456 } 457 458 static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr) 459 { 460 uint32_t ret; 461 462 ret = taihu_cpld_readb(opaque, addr) << 24; 463 ret |= taihu_cpld_readb(opaque, addr + 1) << 16; 464 ret |= taihu_cpld_readb(opaque, addr + 2) << 8; 465 ret |= taihu_cpld_readb(opaque, addr + 3); 466 467 return ret; 468 } 469 470 static void taihu_cpld_writel (void *opaque, 471 hwaddr addr, uint32_t value) 472 { 473 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); 474 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); 475 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); 476 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); 477 } 478 479 static const MemoryRegionOps taihu_cpld_ops = { 480 .old_mmio = { 481 .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, 482 .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, 483 }, 484 .endianness = DEVICE_NATIVE_ENDIAN, 485 }; 486 487 static void taihu_cpld_reset (void *opaque) 488 { 489 taihu_cpld_t *cpld; 490 491 cpld = opaque; 492 cpld->reg0 = 0x01; 493 cpld->reg1 = 0x80; 494 } 495 496 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 497 { 498 taihu_cpld_t *cpld; 499 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 500 501 cpld = g_malloc0(sizeof(taihu_cpld_t)); 502 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 503 memory_region_add_subregion(sysmem, base, cpld_memory); 504 qemu_register_reset(&taihu_cpld_reset, cpld); 505 } 506 507 static void taihu_405ep_init(MachineState *machine) 508 { 509 ram_addr_t ram_size = machine->ram_size; 510 const char *kernel_filename = machine->kernel_filename; 511 const char *initrd_filename = machine->initrd_filename; 512 char *filename; 513 qemu_irq *pic; 514 MemoryRegion *sysmem = get_system_memory(); 515 MemoryRegion *bios; 516 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 517 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 518 hwaddr ram_bases[2], ram_sizes[2]; 519 long bios_size; 520 target_ulong kernel_base, initrd_base; 521 long kernel_size, initrd_size; 522 int linux_boot; 523 int fl_idx, fl_sectors; 524 DriveInfo *dinfo; 525 526 /* RAM is soldered to the board so the size cannot be changed */ 527 ram_size = 0x08000000; 528 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 529 ram_size); 530 531 ram_bases[0] = 0; 532 ram_sizes[0] = 0x04000000; 533 memory_region_init_alias(&ram_memories[0], NULL, 534 "taihu_405ep.ram-0", ram, ram_bases[0], 535 ram_sizes[0]); 536 ram_bases[1] = 0x04000000; 537 ram_sizes[1] = 0x04000000; 538 memory_region_init_alias(&ram_memories[1], NULL, 539 "taihu_405ep.ram-1", ram, ram_bases[1], 540 ram_sizes[1]); 541 #ifdef DEBUG_BOARD_INIT 542 printf("%s: register cpu\n", __func__); 543 #endif 544 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 545 33333333, &pic, kernel_filename == NULL ? 0 : 1); 546 /* allocate and load BIOS */ 547 #ifdef DEBUG_BOARD_INIT 548 printf("%s: register BIOS\n", __func__); 549 #endif 550 fl_idx = 0; 551 #if defined(USE_FLASH_BIOS) 552 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 553 if (dinfo) { 554 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 555 556 bios_size = blk_getlength(blk); 557 /* XXX: should check that size is 2MB */ 558 // bios_size = 2 * 1024 * 1024; 559 fl_sectors = (bios_size + 65535) >> 16; 560 #ifdef DEBUG_BOARD_INIT 561 printf("Register parallel flash %d size %lx" 562 " at addr %lx '%s' %d\n", 563 fl_idx, bios_size, -bios_size, 564 blk_name(blk), fl_sectors); 565 #endif 566 pflash_cfi02_register((uint32_t)(-bios_size), 567 NULL, "taihu_405ep.bios", bios_size, 568 blk, 65536, fl_sectors, 1, 569 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 570 1); 571 fl_idx++; 572 } else 573 #endif 574 { 575 #ifdef DEBUG_BOARD_INIT 576 printf("Load BIOS from file\n"); 577 #endif 578 if (bios_name == NULL) 579 bios_name = BIOS_FILENAME; 580 bios = g_new(MemoryRegion, 1); 581 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 582 &error_abort); 583 vmstate_register_ram_global(bios); 584 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 585 if (filename) { 586 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 587 g_free(filename); 588 if (bios_size < 0 || bios_size > BIOS_SIZE) { 589 error_report("Could not load PowerPC BIOS '%s'", bios_name); 590 exit(1); 591 } 592 bios_size = (bios_size + 0xfff) & ~0xfff; 593 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 594 } else if (!qtest_enabled()) { 595 error_report("Could not load PowerPC BIOS '%s'", bios_name); 596 exit(1); 597 } 598 memory_region_set_readonly(bios, true); 599 } 600 /* Register Linux flash */ 601 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 602 if (dinfo) { 603 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 604 605 bios_size = blk_getlength(blk); 606 /* XXX: should check that size is 32MB */ 607 bios_size = 32 * 1024 * 1024; 608 fl_sectors = (bios_size + 65535) >> 16; 609 #ifdef DEBUG_BOARD_INIT 610 printf("Register parallel flash %d size %lx" 611 " at addr " TARGET_FMT_lx " '%s'\n", 612 fl_idx, bios_size, (target_ulong)0xfc000000, 613 blk_name(blk)); 614 #endif 615 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 616 blk, 65536, fl_sectors, 1, 617 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 618 1); 619 fl_idx++; 620 } 621 /* Register CLPD & LCD display */ 622 #ifdef DEBUG_BOARD_INIT 623 printf("%s: register CPLD\n", __func__); 624 #endif 625 taihu_cpld_init(sysmem, 0x50100000); 626 /* Load kernel */ 627 linux_boot = (kernel_filename != NULL); 628 if (linux_boot) { 629 #ifdef DEBUG_BOARD_INIT 630 printf("%s: load kernel\n", __func__); 631 #endif 632 kernel_base = KERNEL_LOAD_ADDR; 633 /* now we can load the kernel */ 634 kernel_size = load_image_targphys(kernel_filename, kernel_base, 635 ram_size - kernel_base); 636 if (kernel_size < 0) { 637 fprintf(stderr, "qemu: could not load kernel '%s'\n", 638 kernel_filename); 639 exit(1); 640 } 641 /* load initrd */ 642 if (initrd_filename) { 643 initrd_base = INITRD_LOAD_ADDR; 644 initrd_size = load_image_targphys(initrd_filename, initrd_base, 645 ram_size - initrd_base); 646 if (initrd_size < 0) { 647 fprintf(stderr, 648 "qemu: could not load initial ram disk '%s'\n", 649 initrd_filename); 650 exit(1); 651 } 652 } else { 653 initrd_base = 0; 654 initrd_size = 0; 655 } 656 } else { 657 kernel_base = 0; 658 kernel_size = 0; 659 initrd_base = 0; 660 initrd_size = 0; 661 } 662 #ifdef DEBUG_BOARD_INIT 663 printf("%s: Done\n", __func__); 664 #endif 665 } 666 667 static QEMUMachine taihu_machine = { 668 .name = "taihu", 669 .desc = "taihu", 670 .init = taihu_405ep_init, 671 }; 672 673 static void ppc405_machine_init(void) 674 { 675 qemu_register_machine(&ref405ep_machine); 676 qemu_register_machine(&taihu_machine); 677 } 678 679 machine_init(ppc405_machine_init); 680