1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "ppc405.h" 31 #include "hw/timer/m48t59.h" 32 #include "hw/block/flash.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/block-backend.h" 36 #include "hw/boards.h" 37 #include "qemu/log.h" 38 #include "qemu/error-report.h" 39 #include "hw/loader.h" 40 #include "sysemu/blockdev.h" 41 #include "exec/address-spaces.h" 42 43 #define BIOS_FILENAME "ppc405_rom.bin" 44 #define BIOS_SIZE (2048 * 1024) 45 46 #define KERNEL_LOAD_ADDR 0x00000000 47 #define INITRD_LOAD_ADDR 0x01800000 48 49 #define USE_FLASH_BIOS 50 51 //#define DEBUG_BOARD_INIT 52 53 /*****************************************************************************/ 54 /* PPC405EP reference board (IBM) */ 55 /* Standalone board with: 56 * - PowerPC 405EP CPU 57 * - SDRAM (0x00000000) 58 * - Flash (0xFFF80000) 59 * - SRAM (0xFFF00000) 60 * - NVRAM (0xF0000000) 61 * - FPGA (0xF0300000) 62 */ 63 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 64 struct ref405ep_fpga_t { 65 uint8_t reg0; 66 uint8_t reg1; 67 }; 68 69 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 70 { 71 ref405ep_fpga_t *fpga; 72 uint32_t ret; 73 74 fpga = opaque; 75 switch (addr) { 76 case 0x0: 77 ret = fpga->reg0; 78 break; 79 case 0x1: 80 ret = fpga->reg1; 81 break; 82 default: 83 ret = 0; 84 break; 85 } 86 87 return ret; 88 } 89 90 static void ref405ep_fpga_writeb (void *opaque, 91 hwaddr addr, uint32_t value) 92 { 93 ref405ep_fpga_t *fpga; 94 95 fpga = opaque; 96 switch (addr) { 97 case 0x0: 98 /* Read only */ 99 break; 100 case 0x1: 101 fpga->reg1 = value; 102 break; 103 default: 104 break; 105 } 106 } 107 108 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 109 { 110 uint32_t ret; 111 112 ret = ref405ep_fpga_readb(opaque, addr) << 8; 113 ret |= ref405ep_fpga_readb(opaque, addr + 1); 114 115 return ret; 116 } 117 118 static void ref405ep_fpga_writew (void *opaque, 119 hwaddr addr, uint32_t value) 120 { 121 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 122 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 123 } 124 125 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 126 { 127 uint32_t ret; 128 129 ret = ref405ep_fpga_readb(opaque, addr) << 24; 130 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 131 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 132 ret |= ref405ep_fpga_readb(opaque, addr + 3); 133 134 return ret; 135 } 136 137 static void ref405ep_fpga_writel (void *opaque, 138 hwaddr addr, uint32_t value) 139 { 140 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 141 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 142 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 143 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 144 } 145 146 static const MemoryRegionOps ref405ep_fpga_ops = { 147 .old_mmio = { 148 .read = { 149 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 150 }, 151 .write = { 152 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 153 }, 154 }, 155 .endianness = DEVICE_NATIVE_ENDIAN, 156 }; 157 158 static void ref405ep_fpga_reset (void *opaque) 159 { 160 ref405ep_fpga_t *fpga; 161 162 fpga = opaque; 163 fpga->reg0 = 0x00; 164 fpga->reg1 = 0x0F; 165 } 166 167 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 168 { 169 ref405ep_fpga_t *fpga; 170 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 171 172 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 173 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 174 "fpga", 0x00000100); 175 memory_region_add_subregion(sysmem, base, fpga_memory); 176 qemu_register_reset(&ref405ep_fpga_reset, fpga); 177 } 178 179 static void ref405ep_init(MachineState *machine) 180 { 181 ram_addr_t ram_size = machine->ram_size; 182 const char *kernel_filename = machine->kernel_filename; 183 const char *kernel_cmdline = machine->kernel_cmdline; 184 const char *initrd_filename = machine->initrd_filename; 185 char *filename; 186 ppc4xx_bd_info_t bd; 187 CPUPPCState *env; 188 qemu_irq *pic; 189 MemoryRegion *bios; 190 MemoryRegion *sram = g_new(MemoryRegion, 1); 191 ram_addr_t bdloc; 192 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 193 hwaddr ram_bases[2], ram_sizes[2]; 194 target_ulong sram_size; 195 long bios_size; 196 //int phy_addr = 0; 197 //static int phy_addr = 1; 198 target_ulong kernel_base, initrd_base; 199 long kernel_size, initrd_size; 200 int linux_boot; 201 int fl_idx, fl_sectors, len; 202 DriveInfo *dinfo; 203 MemoryRegion *sysmem = get_system_memory(); 204 205 /* XXX: fix this */ 206 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 207 0x08000000); 208 ram_bases[0] = 0; 209 ram_sizes[0] = 0x08000000; 210 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 211 ram_bases[1] = 0x00000000; 212 ram_sizes[1] = 0x00000000; 213 ram_size = 128 * 1024 * 1024; 214 #ifdef DEBUG_BOARD_INIT 215 printf("%s: register cpu\n", __func__); 216 #endif 217 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 218 33333333, &pic, kernel_filename == NULL ? 0 : 1); 219 /* allocate SRAM */ 220 sram_size = 512 * 1024; 221 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 222 &error_fatal); 223 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 224 /* allocate and load BIOS */ 225 #ifdef DEBUG_BOARD_INIT 226 printf("%s: register BIOS\n", __func__); 227 #endif 228 fl_idx = 0; 229 #ifdef USE_FLASH_BIOS 230 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 231 if (dinfo) { 232 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 233 234 bios_size = blk_getlength(blk); 235 fl_sectors = (bios_size + 65535) >> 16; 236 #ifdef DEBUG_BOARD_INIT 237 printf("Register parallel flash %d size %lx" 238 " at addr %lx '%s' %d\n", 239 fl_idx, bios_size, -bios_size, 240 blk_name(blk), fl_sectors); 241 #endif 242 pflash_cfi02_register((uint32_t)(-bios_size), 243 NULL, "ef405ep.bios", bios_size, 244 blk, 65536, fl_sectors, 1, 245 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 246 1); 247 fl_idx++; 248 } else 249 #endif 250 { 251 #ifdef DEBUG_BOARD_INIT 252 printf("Load BIOS from file\n"); 253 #endif 254 bios = g_new(MemoryRegion, 1); 255 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 256 &error_fatal); 257 258 if (bios_name == NULL) 259 bios_name = BIOS_FILENAME; 260 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 261 if (filename) { 262 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 263 g_free(filename); 264 if (bios_size < 0 || bios_size > BIOS_SIZE) { 265 error_report("Could not load PowerPC BIOS '%s'", bios_name); 266 exit(1); 267 } 268 bios_size = (bios_size + 0xfff) & ~0xfff; 269 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 270 } else if (!qtest_enabled() || kernel_filename != NULL) { 271 error_report("Could not load PowerPC BIOS '%s'", bios_name); 272 exit(1); 273 } else { 274 /* Avoid an uninitialized variable warning */ 275 bios_size = -1; 276 } 277 memory_region_set_readonly(bios, true); 278 } 279 /* Register FPGA */ 280 #ifdef DEBUG_BOARD_INIT 281 printf("%s: register FPGA\n", __func__); 282 #endif 283 ref405ep_fpga_init(sysmem, 0xF0300000); 284 /* Register NVRAM */ 285 #ifdef DEBUG_BOARD_INIT 286 printf("%s: register NVRAM\n", __func__); 287 #endif 288 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 289 /* Load kernel */ 290 linux_boot = (kernel_filename != NULL); 291 if (linux_boot) { 292 #ifdef DEBUG_BOARD_INIT 293 printf("%s: load kernel\n", __func__); 294 #endif 295 memset(&bd, 0, sizeof(bd)); 296 bd.bi_memstart = 0x00000000; 297 bd.bi_memsize = ram_size; 298 bd.bi_flashstart = -bios_size; 299 bd.bi_flashsize = -bios_size; 300 bd.bi_flashoffset = 0; 301 bd.bi_sramstart = 0xFFF00000; 302 bd.bi_sramsize = sram_size; 303 bd.bi_bootflags = 0; 304 bd.bi_intfreq = 133333333; 305 bd.bi_busfreq = 33333333; 306 bd.bi_baudrate = 115200; 307 bd.bi_s_version[0] = 'Q'; 308 bd.bi_s_version[1] = 'M'; 309 bd.bi_s_version[2] = 'U'; 310 bd.bi_s_version[3] = '\0'; 311 bd.bi_r_version[0] = 'Q'; 312 bd.bi_r_version[1] = 'E'; 313 bd.bi_r_version[2] = 'M'; 314 bd.bi_r_version[3] = 'U'; 315 bd.bi_r_version[4] = '\0'; 316 bd.bi_procfreq = 133333333; 317 bd.bi_plb_busfreq = 33333333; 318 bd.bi_pci_busfreq = 33333333; 319 bd.bi_opbfreq = 33333333; 320 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 321 env->gpr[3] = bdloc; 322 kernel_base = KERNEL_LOAD_ADDR; 323 /* now we can load the kernel */ 324 kernel_size = load_image_targphys(kernel_filename, kernel_base, 325 ram_size - kernel_base); 326 if (kernel_size < 0) { 327 fprintf(stderr, "qemu: could not load kernel '%s'\n", 328 kernel_filename); 329 exit(1); 330 } 331 printf("Load kernel size %ld at " TARGET_FMT_lx, 332 kernel_size, kernel_base); 333 /* load initrd */ 334 if (initrd_filename) { 335 initrd_base = INITRD_LOAD_ADDR; 336 initrd_size = load_image_targphys(initrd_filename, initrd_base, 337 ram_size - initrd_base); 338 if (initrd_size < 0) { 339 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 340 initrd_filename); 341 exit(1); 342 } 343 } else { 344 initrd_base = 0; 345 initrd_size = 0; 346 } 347 env->gpr[4] = initrd_base; 348 env->gpr[5] = initrd_size; 349 if (kernel_cmdline != NULL) { 350 len = strlen(kernel_cmdline); 351 bdloc -= ((len + 255) & ~255); 352 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 353 env->gpr[6] = bdloc; 354 env->gpr[7] = bdloc + len; 355 } else { 356 env->gpr[6] = 0; 357 env->gpr[7] = 0; 358 } 359 env->nip = KERNEL_LOAD_ADDR; 360 } else { 361 kernel_base = 0; 362 kernel_size = 0; 363 initrd_base = 0; 364 initrd_size = 0; 365 bdloc = 0; 366 } 367 #ifdef DEBUG_BOARD_INIT 368 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 369 printf("%s: Done\n", __func__); 370 #endif 371 } 372 373 static void ref405ep_class_init(ObjectClass *oc, void *data) 374 { 375 MachineClass *mc = MACHINE_CLASS(oc); 376 377 mc->desc = "ref405ep"; 378 mc->init = ref405ep_init; 379 } 380 381 static const TypeInfo ref405ep_type = { 382 .name = MACHINE_TYPE_NAME("ref405ep"), 383 .parent = TYPE_MACHINE, 384 .class_init = ref405ep_class_init, 385 }; 386 387 /*****************************************************************************/ 388 /* AMCC Taihu evaluation board */ 389 /* - PowerPC 405EP processor 390 * - SDRAM 128 MB at 0x00000000 391 * - Boot flash 2 MB at 0xFFE00000 392 * - Application flash 32 MB at 0xFC000000 393 * - 2 serial ports 394 * - 2 ethernet PHY 395 * - 1 USB 1.1 device 0x50000000 396 * - 1 LCD display 0x50100000 397 * - 1 CPLD 0x50100000 398 * - 1 I2C EEPROM 399 * - 1 I2C thermal sensor 400 * - a set of LEDs 401 * - bit-bang SPI port using GPIOs 402 * - 1 EBC interface connector 0 0x50200000 403 * - 1 cardbus controller + expansion slot. 404 * - 1 PCI expansion slot. 405 */ 406 typedef struct taihu_cpld_t taihu_cpld_t; 407 struct taihu_cpld_t { 408 uint8_t reg0; 409 uint8_t reg1; 410 }; 411 412 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 413 { 414 taihu_cpld_t *cpld; 415 uint32_t ret; 416 417 cpld = opaque; 418 switch (addr) { 419 case 0x0: 420 ret = cpld->reg0; 421 break; 422 case 0x1: 423 ret = cpld->reg1; 424 break; 425 default: 426 ret = 0; 427 break; 428 } 429 430 return ret; 431 } 432 433 static void taihu_cpld_write(void *opaque, hwaddr addr, 434 uint64_t value, unsigned size) 435 { 436 taihu_cpld_t *cpld; 437 438 cpld = opaque; 439 switch (addr) { 440 case 0x0: 441 /* Read only */ 442 break; 443 case 0x1: 444 cpld->reg1 = value; 445 break; 446 default: 447 break; 448 } 449 } 450 451 static const MemoryRegionOps taihu_cpld_ops = { 452 .read = taihu_cpld_read, 453 .write = taihu_cpld_write, 454 .impl = { 455 .min_access_size = 1, 456 .max_access_size = 1, 457 }, 458 .endianness = DEVICE_NATIVE_ENDIAN, 459 }; 460 461 static void taihu_cpld_reset (void *opaque) 462 { 463 taihu_cpld_t *cpld; 464 465 cpld = opaque; 466 cpld->reg0 = 0x01; 467 cpld->reg1 = 0x80; 468 } 469 470 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 471 { 472 taihu_cpld_t *cpld; 473 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 474 475 cpld = g_malloc0(sizeof(taihu_cpld_t)); 476 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 477 memory_region_add_subregion(sysmem, base, cpld_memory); 478 qemu_register_reset(&taihu_cpld_reset, cpld); 479 } 480 481 static void taihu_405ep_init(MachineState *machine) 482 { 483 ram_addr_t ram_size = machine->ram_size; 484 const char *kernel_filename = machine->kernel_filename; 485 const char *initrd_filename = machine->initrd_filename; 486 char *filename; 487 qemu_irq *pic; 488 MemoryRegion *sysmem = get_system_memory(); 489 MemoryRegion *bios; 490 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 491 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 492 hwaddr ram_bases[2], ram_sizes[2]; 493 long bios_size; 494 target_ulong kernel_base, initrd_base; 495 long kernel_size, initrd_size; 496 int linux_boot; 497 int fl_idx, fl_sectors; 498 DriveInfo *dinfo; 499 500 /* RAM is soldered to the board so the size cannot be changed */ 501 ram_size = 0x08000000; 502 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 503 ram_size); 504 505 ram_bases[0] = 0; 506 ram_sizes[0] = 0x04000000; 507 memory_region_init_alias(&ram_memories[0], NULL, 508 "taihu_405ep.ram-0", ram, ram_bases[0], 509 ram_sizes[0]); 510 ram_bases[1] = 0x04000000; 511 ram_sizes[1] = 0x04000000; 512 memory_region_init_alias(&ram_memories[1], NULL, 513 "taihu_405ep.ram-1", ram, ram_bases[1], 514 ram_sizes[1]); 515 #ifdef DEBUG_BOARD_INIT 516 printf("%s: register cpu\n", __func__); 517 #endif 518 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 519 33333333, &pic, kernel_filename == NULL ? 0 : 1); 520 /* allocate and load BIOS */ 521 #ifdef DEBUG_BOARD_INIT 522 printf("%s: register BIOS\n", __func__); 523 #endif 524 fl_idx = 0; 525 #if defined(USE_FLASH_BIOS) 526 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 527 if (dinfo) { 528 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 529 530 bios_size = blk_getlength(blk); 531 /* XXX: should check that size is 2MB */ 532 // bios_size = 2 * 1024 * 1024; 533 fl_sectors = (bios_size + 65535) >> 16; 534 #ifdef DEBUG_BOARD_INIT 535 printf("Register parallel flash %d size %lx" 536 " at addr %lx '%s' %d\n", 537 fl_idx, bios_size, -bios_size, 538 blk_name(blk), fl_sectors); 539 #endif 540 pflash_cfi02_register((uint32_t)(-bios_size), 541 NULL, "taihu_405ep.bios", bios_size, 542 blk, 65536, fl_sectors, 1, 543 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 544 1); 545 fl_idx++; 546 } else 547 #endif 548 { 549 #ifdef DEBUG_BOARD_INIT 550 printf("Load BIOS from file\n"); 551 #endif 552 if (bios_name == NULL) 553 bios_name = BIOS_FILENAME; 554 bios = g_new(MemoryRegion, 1); 555 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 556 &error_fatal); 557 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 558 if (filename) { 559 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 560 g_free(filename); 561 if (bios_size < 0 || bios_size > BIOS_SIZE) { 562 error_report("Could not load PowerPC BIOS '%s'", bios_name); 563 exit(1); 564 } 565 bios_size = (bios_size + 0xfff) & ~0xfff; 566 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 567 } else if (!qtest_enabled()) { 568 error_report("Could not load PowerPC BIOS '%s'", bios_name); 569 exit(1); 570 } 571 memory_region_set_readonly(bios, true); 572 } 573 /* Register Linux flash */ 574 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 575 if (dinfo) { 576 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 577 578 bios_size = blk_getlength(blk); 579 /* XXX: should check that size is 32MB */ 580 bios_size = 32 * 1024 * 1024; 581 fl_sectors = (bios_size + 65535) >> 16; 582 #ifdef DEBUG_BOARD_INIT 583 printf("Register parallel flash %d size %lx" 584 " at addr " TARGET_FMT_lx " '%s'\n", 585 fl_idx, bios_size, (target_ulong)0xfc000000, 586 blk_name(blk)); 587 #endif 588 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 589 blk, 65536, fl_sectors, 1, 590 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 591 1); 592 fl_idx++; 593 } 594 /* Register CLPD & LCD display */ 595 #ifdef DEBUG_BOARD_INIT 596 printf("%s: register CPLD\n", __func__); 597 #endif 598 taihu_cpld_init(sysmem, 0x50100000); 599 /* Load kernel */ 600 linux_boot = (kernel_filename != NULL); 601 if (linux_boot) { 602 #ifdef DEBUG_BOARD_INIT 603 printf("%s: load kernel\n", __func__); 604 #endif 605 kernel_base = KERNEL_LOAD_ADDR; 606 /* now we can load the kernel */ 607 kernel_size = load_image_targphys(kernel_filename, kernel_base, 608 ram_size - kernel_base); 609 if (kernel_size < 0) { 610 fprintf(stderr, "qemu: could not load kernel '%s'\n", 611 kernel_filename); 612 exit(1); 613 } 614 /* load initrd */ 615 if (initrd_filename) { 616 initrd_base = INITRD_LOAD_ADDR; 617 initrd_size = load_image_targphys(initrd_filename, initrd_base, 618 ram_size - initrd_base); 619 if (initrd_size < 0) { 620 fprintf(stderr, 621 "qemu: could not load initial ram disk '%s'\n", 622 initrd_filename); 623 exit(1); 624 } 625 } else { 626 initrd_base = 0; 627 initrd_size = 0; 628 } 629 } else { 630 kernel_base = 0; 631 kernel_size = 0; 632 initrd_base = 0; 633 initrd_size = 0; 634 } 635 #ifdef DEBUG_BOARD_INIT 636 printf("%s: Done\n", __func__); 637 #endif 638 } 639 640 static void taihu_class_init(ObjectClass *oc, void *data) 641 { 642 MachineClass *mc = MACHINE_CLASS(oc); 643 644 mc->desc = "taihu"; 645 mc->init = taihu_405ep_init; 646 } 647 648 static const TypeInfo taihu_type = { 649 .name = MACHINE_TYPE_NAME("taihu"), 650 .parent = TYPE_MACHINE, 651 .class_init = taihu_class_init, 652 }; 653 654 static void ppc405_machine_init(void) 655 { 656 type_register_static(&ref405ep_type); 657 type_register_static(&taihu_type); 658 } 659 660 type_init(ppc405_machine_init) 661