1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "cpu.h" 29 #include "hw/hw.h" 30 #include "hw/ppc/ppc.h" 31 #include "ppc405.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/block/flash.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/block-backend.h" 37 #include "hw/boards.h" 38 #include "qemu/log.h" 39 #include "qemu/error-report.h" 40 #include "hw/loader.h" 41 #include "exec/address-spaces.h" 42 43 #define BIOS_FILENAME "ppc405_rom.bin" 44 #define BIOS_SIZE (2 * MiB) 45 46 #define KERNEL_LOAD_ADDR 0x00000000 47 #define INITRD_LOAD_ADDR 0x01800000 48 49 #define USE_FLASH_BIOS 50 51 //#define DEBUG_BOARD_INIT 52 53 /*****************************************************************************/ 54 /* PPC405EP reference board (IBM) */ 55 /* Standalone board with: 56 * - PowerPC 405EP CPU 57 * - SDRAM (0x00000000) 58 * - Flash (0xFFF80000) 59 * - SRAM (0xFFF00000) 60 * - NVRAM (0xF0000000) 61 * - FPGA (0xF0300000) 62 */ 63 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 64 struct ref405ep_fpga_t { 65 uint8_t reg0; 66 uint8_t reg1; 67 }; 68 69 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) 70 { 71 ref405ep_fpga_t *fpga; 72 uint32_t ret; 73 74 fpga = opaque; 75 switch (addr) { 76 case 0x0: 77 ret = fpga->reg0; 78 break; 79 case 0x1: 80 ret = fpga->reg1; 81 break; 82 default: 83 ret = 0; 84 break; 85 } 86 87 return ret; 88 } 89 90 static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, 91 unsigned size) 92 { 93 ref405ep_fpga_t *fpga; 94 95 fpga = opaque; 96 switch (addr) { 97 case 0x0: 98 /* Read only */ 99 break; 100 case 0x1: 101 fpga->reg1 = value; 102 break; 103 default: 104 break; 105 } 106 } 107 108 static const MemoryRegionOps ref405ep_fpga_ops = { 109 .read = ref405ep_fpga_readb, 110 .write = ref405ep_fpga_writeb, 111 .impl.min_access_size = 1, 112 .impl.max_access_size = 1, 113 .valid.min_access_size = 1, 114 .valid.max_access_size = 4, 115 .endianness = DEVICE_BIG_ENDIAN, 116 }; 117 118 static void ref405ep_fpga_reset (void *opaque) 119 { 120 ref405ep_fpga_t *fpga; 121 122 fpga = opaque; 123 fpga->reg0 = 0x00; 124 fpga->reg1 = 0x0F; 125 } 126 127 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 128 { 129 ref405ep_fpga_t *fpga; 130 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 131 132 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 133 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 134 "fpga", 0x00000100); 135 memory_region_add_subregion(sysmem, base, fpga_memory); 136 qemu_register_reset(&ref405ep_fpga_reset, fpga); 137 } 138 139 static void ref405ep_init(MachineState *machine) 140 { 141 ram_addr_t ram_size = machine->ram_size; 142 const char *kernel_filename = machine->kernel_filename; 143 const char *kernel_cmdline = machine->kernel_cmdline; 144 const char *initrd_filename = machine->initrd_filename; 145 char *filename; 146 ppc4xx_bd_info_t bd; 147 CPUPPCState *env; 148 qemu_irq *pic; 149 MemoryRegion *bios; 150 MemoryRegion *sram = g_new(MemoryRegion, 1); 151 ram_addr_t bdloc; 152 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 153 hwaddr ram_bases[2], ram_sizes[2]; 154 target_ulong sram_size; 155 long bios_size; 156 //int phy_addr = 0; 157 //static int phy_addr = 1; 158 target_ulong kernel_base, initrd_base; 159 long kernel_size, initrd_size; 160 int linux_boot; 161 int fl_idx, fl_sectors, len; 162 DriveInfo *dinfo; 163 MemoryRegion *sysmem = get_system_memory(); 164 165 /* XXX: fix this */ 166 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 167 0x08000000); 168 ram_bases[0] = 0; 169 ram_sizes[0] = 0x08000000; 170 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 171 ram_bases[1] = 0x00000000; 172 ram_sizes[1] = 0x00000000; 173 ram_size = 128 * MiB; 174 #ifdef DEBUG_BOARD_INIT 175 printf("%s: register cpu\n", __func__); 176 #endif 177 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 178 33333333, &pic, kernel_filename == NULL ? 0 : 1); 179 /* allocate SRAM */ 180 sram_size = 512 * KiB; 181 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 182 &error_fatal); 183 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 184 /* allocate and load BIOS */ 185 #ifdef DEBUG_BOARD_INIT 186 printf("%s: register BIOS\n", __func__); 187 #endif 188 fl_idx = 0; 189 #ifdef USE_FLASH_BIOS 190 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 191 if (dinfo) { 192 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 193 194 bios_size = blk_getlength(blk); 195 fl_sectors = (bios_size + 65535) >> 16; 196 #ifdef DEBUG_BOARD_INIT 197 printf("Register parallel flash %d size %lx" 198 " at addr %lx '%s' %d\n", 199 fl_idx, bios_size, -bios_size, 200 blk_name(blk), fl_sectors); 201 #endif 202 pflash_cfi02_register((uint32_t)(-bios_size), 203 NULL, "ef405ep.bios", bios_size, 204 blk, 65536, fl_sectors, 1, 205 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 206 1); 207 fl_idx++; 208 } else 209 #endif 210 { 211 #ifdef DEBUG_BOARD_INIT 212 printf("Load BIOS from file\n"); 213 #endif 214 bios = g_new(MemoryRegion, 1); 215 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 216 &error_fatal); 217 218 if (bios_name == NULL) 219 bios_name = BIOS_FILENAME; 220 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 221 if (filename) { 222 bios_size = load_image_size(filename, 223 memory_region_get_ram_ptr(bios), 224 BIOS_SIZE); 225 g_free(filename); 226 if (bios_size < 0) { 227 error_report("Could not load PowerPC BIOS '%s'", bios_name); 228 exit(1); 229 } 230 bios_size = (bios_size + 0xfff) & ~0xfff; 231 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 232 } else if (!qtest_enabled() || kernel_filename != NULL) { 233 error_report("Could not load PowerPC BIOS '%s'", bios_name); 234 exit(1); 235 } else { 236 /* Avoid an uninitialized variable warning */ 237 bios_size = -1; 238 } 239 memory_region_set_readonly(bios, true); 240 } 241 /* Register FPGA */ 242 #ifdef DEBUG_BOARD_INIT 243 printf("%s: register FPGA\n", __func__); 244 #endif 245 ref405ep_fpga_init(sysmem, 0xF0300000); 246 /* Register NVRAM */ 247 #ifdef DEBUG_BOARD_INIT 248 printf("%s: register NVRAM\n", __func__); 249 #endif 250 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 251 /* Load kernel */ 252 linux_boot = (kernel_filename != NULL); 253 if (linux_boot) { 254 #ifdef DEBUG_BOARD_INIT 255 printf("%s: load kernel\n", __func__); 256 #endif 257 memset(&bd, 0, sizeof(bd)); 258 bd.bi_memstart = 0x00000000; 259 bd.bi_memsize = ram_size; 260 bd.bi_flashstart = -bios_size; 261 bd.bi_flashsize = -bios_size; 262 bd.bi_flashoffset = 0; 263 bd.bi_sramstart = 0xFFF00000; 264 bd.bi_sramsize = sram_size; 265 bd.bi_bootflags = 0; 266 bd.bi_intfreq = 133333333; 267 bd.bi_busfreq = 33333333; 268 bd.bi_baudrate = 115200; 269 bd.bi_s_version[0] = 'Q'; 270 bd.bi_s_version[1] = 'M'; 271 bd.bi_s_version[2] = 'U'; 272 bd.bi_s_version[3] = '\0'; 273 bd.bi_r_version[0] = 'Q'; 274 bd.bi_r_version[1] = 'E'; 275 bd.bi_r_version[2] = 'M'; 276 bd.bi_r_version[3] = 'U'; 277 bd.bi_r_version[4] = '\0'; 278 bd.bi_procfreq = 133333333; 279 bd.bi_plb_busfreq = 33333333; 280 bd.bi_pci_busfreq = 33333333; 281 bd.bi_opbfreq = 33333333; 282 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 283 env->gpr[3] = bdloc; 284 kernel_base = KERNEL_LOAD_ADDR; 285 /* now we can load the kernel */ 286 kernel_size = load_image_targphys(kernel_filename, kernel_base, 287 ram_size - kernel_base); 288 if (kernel_size < 0) { 289 error_report("could not load kernel '%s'", kernel_filename); 290 exit(1); 291 } 292 printf("Load kernel size %ld at " TARGET_FMT_lx, 293 kernel_size, kernel_base); 294 /* load initrd */ 295 if (initrd_filename) { 296 initrd_base = INITRD_LOAD_ADDR; 297 initrd_size = load_image_targphys(initrd_filename, initrd_base, 298 ram_size - initrd_base); 299 if (initrd_size < 0) { 300 error_report("could not load initial ram disk '%s'", 301 initrd_filename); 302 exit(1); 303 } 304 } else { 305 initrd_base = 0; 306 initrd_size = 0; 307 } 308 env->gpr[4] = initrd_base; 309 env->gpr[5] = initrd_size; 310 if (kernel_cmdline != NULL) { 311 len = strlen(kernel_cmdline); 312 bdloc -= ((len + 255) & ~255); 313 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 314 env->gpr[6] = bdloc; 315 env->gpr[7] = bdloc + len; 316 } else { 317 env->gpr[6] = 0; 318 env->gpr[7] = 0; 319 } 320 env->nip = KERNEL_LOAD_ADDR; 321 } else { 322 kernel_base = 0; 323 kernel_size = 0; 324 initrd_base = 0; 325 initrd_size = 0; 326 bdloc = 0; 327 } 328 #ifdef DEBUG_BOARD_INIT 329 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 330 printf("%s: Done\n", __func__); 331 #endif 332 } 333 334 static void ref405ep_class_init(ObjectClass *oc, void *data) 335 { 336 MachineClass *mc = MACHINE_CLASS(oc); 337 338 mc->desc = "ref405ep"; 339 mc->init = ref405ep_init; 340 } 341 342 static const TypeInfo ref405ep_type = { 343 .name = MACHINE_TYPE_NAME("ref405ep"), 344 .parent = TYPE_MACHINE, 345 .class_init = ref405ep_class_init, 346 }; 347 348 /*****************************************************************************/ 349 /* AMCC Taihu evaluation board */ 350 /* - PowerPC 405EP processor 351 * - SDRAM 128 MB at 0x00000000 352 * - Boot flash 2 MB at 0xFFE00000 353 * - Application flash 32 MB at 0xFC000000 354 * - 2 serial ports 355 * - 2 ethernet PHY 356 * - 1 USB 1.1 device 0x50000000 357 * - 1 LCD display 0x50100000 358 * - 1 CPLD 0x50100000 359 * - 1 I2C EEPROM 360 * - 1 I2C thermal sensor 361 * - a set of LEDs 362 * - bit-bang SPI port using GPIOs 363 * - 1 EBC interface connector 0 0x50200000 364 * - 1 cardbus controller + expansion slot. 365 * - 1 PCI expansion slot. 366 */ 367 typedef struct taihu_cpld_t taihu_cpld_t; 368 struct taihu_cpld_t { 369 uint8_t reg0; 370 uint8_t reg1; 371 }; 372 373 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 374 { 375 taihu_cpld_t *cpld; 376 uint32_t ret; 377 378 cpld = opaque; 379 switch (addr) { 380 case 0x0: 381 ret = cpld->reg0; 382 break; 383 case 0x1: 384 ret = cpld->reg1; 385 break; 386 default: 387 ret = 0; 388 break; 389 } 390 391 return ret; 392 } 393 394 static void taihu_cpld_write(void *opaque, hwaddr addr, 395 uint64_t value, unsigned size) 396 { 397 taihu_cpld_t *cpld; 398 399 cpld = opaque; 400 switch (addr) { 401 case 0x0: 402 /* Read only */ 403 break; 404 case 0x1: 405 cpld->reg1 = value; 406 break; 407 default: 408 break; 409 } 410 } 411 412 static const MemoryRegionOps taihu_cpld_ops = { 413 .read = taihu_cpld_read, 414 .write = taihu_cpld_write, 415 .impl = { 416 .min_access_size = 1, 417 .max_access_size = 1, 418 }, 419 .endianness = DEVICE_NATIVE_ENDIAN, 420 }; 421 422 static void taihu_cpld_reset (void *opaque) 423 { 424 taihu_cpld_t *cpld; 425 426 cpld = opaque; 427 cpld->reg0 = 0x01; 428 cpld->reg1 = 0x80; 429 } 430 431 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 432 { 433 taihu_cpld_t *cpld; 434 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 435 436 cpld = g_malloc0(sizeof(taihu_cpld_t)); 437 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 438 memory_region_add_subregion(sysmem, base, cpld_memory); 439 qemu_register_reset(&taihu_cpld_reset, cpld); 440 } 441 442 static void taihu_405ep_init(MachineState *machine) 443 { 444 ram_addr_t ram_size = machine->ram_size; 445 const char *kernel_filename = machine->kernel_filename; 446 const char *initrd_filename = machine->initrd_filename; 447 char *filename; 448 qemu_irq *pic; 449 MemoryRegion *sysmem = get_system_memory(); 450 MemoryRegion *bios; 451 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 452 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 453 hwaddr ram_bases[2], ram_sizes[2]; 454 long bios_size; 455 target_ulong kernel_base, initrd_base; 456 long kernel_size, initrd_size; 457 int linux_boot; 458 int fl_idx, fl_sectors; 459 DriveInfo *dinfo; 460 461 /* RAM is soldered to the board so the size cannot be changed */ 462 ram_size = 0x08000000; 463 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 464 ram_size); 465 466 ram_bases[0] = 0; 467 ram_sizes[0] = 0x04000000; 468 memory_region_init_alias(&ram_memories[0], NULL, 469 "taihu_405ep.ram-0", ram, ram_bases[0], 470 ram_sizes[0]); 471 ram_bases[1] = 0x04000000; 472 ram_sizes[1] = 0x04000000; 473 memory_region_init_alias(&ram_memories[1], NULL, 474 "taihu_405ep.ram-1", ram, ram_bases[1], 475 ram_sizes[1]); 476 #ifdef DEBUG_BOARD_INIT 477 printf("%s: register cpu\n", __func__); 478 #endif 479 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 480 33333333, &pic, kernel_filename == NULL ? 0 : 1); 481 /* allocate and load BIOS */ 482 #ifdef DEBUG_BOARD_INIT 483 printf("%s: register BIOS\n", __func__); 484 #endif 485 fl_idx = 0; 486 #if defined(USE_FLASH_BIOS) 487 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 488 if (dinfo) { 489 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 490 491 bios_size = blk_getlength(blk); 492 /* XXX: should check that size is 2MB */ 493 // bios_size = 2 * 1024 * 1024; 494 fl_sectors = (bios_size + 65535) >> 16; 495 #ifdef DEBUG_BOARD_INIT 496 printf("Register parallel flash %d size %lx" 497 " at addr %lx '%s' %d\n", 498 fl_idx, bios_size, -bios_size, 499 blk_name(blk), fl_sectors); 500 #endif 501 pflash_cfi02_register((uint32_t)(-bios_size), 502 NULL, "taihu_405ep.bios", bios_size, 503 blk, 65536, fl_sectors, 1, 504 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 505 1); 506 fl_idx++; 507 } else 508 #endif 509 { 510 #ifdef DEBUG_BOARD_INIT 511 printf("Load BIOS from file\n"); 512 #endif 513 if (bios_name == NULL) 514 bios_name = BIOS_FILENAME; 515 bios = g_new(MemoryRegion, 1); 516 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 517 &error_fatal); 518 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 519 if (filename) { 520 bios_size = load_image_size(filename, 521 memory_region_get_ram_ptr(bios), 522 BIOS_SIZE); 523 g_free(filename); 524 if (bios_size < 0) { 525 error_report("Could not load PowerPC BIOS '%s'", bios_name); 526 exit(1); 527 } 528 bios_size = (bios_size + 0xfff) & ~0xfff; 529 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 530 } else if (!qtest_enabled()) { 531 error_report("Could not load PowerPC BIOS '%s'", bios_name); 532 exit(1); 533 } 534 memory_region_set_readonly(bios, true); 535 } 536 /* Register Linux flash */ 537 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 538 if (dinfo) { 539 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 540 541 bios_size = blk_getlength(blk); 542 /* XXX: should check that size is 32MB */ 543 bios_size = 32 * MiB; 544 fl_sectors = (bios_size + 65535) >> 16; 545 #ifdef DEBUG_BOARD_INIT 546 printf("Register parallel flash %d size %lx" 547 " at addr " TARGET_FMT_lx " '%s'\n", 548 fl_idx, bios_size, (target_ulong)0xfc000000, 549 blk_name(blk)); 550 #endif 551 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 552 blk, 65536, fl_sectors, 1, 553 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 554 1); 555 fl_idx++; 556 } 557 /* Register CLPD & LCD display */ 558 #ifdef DEBUG_BOARD_INIT 559 printf("%s: register CPLD\n", __func__); 560 #endif 561 taihu_cpld_init(sysmem, 0x50100000); 562 /* Load kernel */ 563 linux_boot = (kernel_filename != NULL); 564 if (linux_boot) { 565 #ifdef DEBUG_BOARD_INIT 566 printf("%s: load kernel\n", __func__); 567 #endif 568 kernel_base = KERNEL_LOAD_ADDR; 569 /* now we can load the kernel */ 570 kernel_size = load_image_targphys(kernel_filename, kernel_base, 571 ram_size - kernel_base); 572 if (kernel_size < 0) { 573 error_report("could not load kernel '%s'", kernel_filename); 574 exit(1); 575 } 576 /* load initrd */ 577 if (initrd_filename) { 578 initrd_base = INITRD_LOAD_ADDR; 579 initrd_size = load_image_targphys(initrd_filename, initrd_base, 580 ram_size - initrd_base); 581 if (initrd_size < 0) { 582 error_report("could not load initial ram disk '%s'", 583 initrd_filename); 584 exit(1); 585 } 586 } else { 587 initrd_base = 0; 588 initrd_size = 0; 589 } 590 } else { 591 kernel_base = 0; 592 kernel_size = 0; 593 initrd_base = 0; 594 initrd_size = 0; 595 } 596 #ifdef DEBUG_BOARD_INIT 597 printf("%s: Done\n", __func__); 598 #endif 599 } 600 601 static void taihu_class_init(ObjectClass *oc, void *data) 602 { 603 MachineClass *mc = MACHINE_CLASS(oc); 604 605 mc->desc = "taihu"; 606 mc->init = taihu_405ep_init; 607 } 608 609 static const TypeInfo taihu_type = { 610 .name = MACHINE_TYPE_NAME("taihu"), 611 .parent = TYPE_MACHINE, 612 .class_init = taihu_class_init, 613 }; 614 615 static void ppc405_machine_init(void) 616 { 617 type_register_static(&ref405ep_type); 618 type_register_static(&taihu_type); 619 } 620 621 type_init(ppc405_machine_init) 622