1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/ppc405.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "block/block.h" 31 #include "hw/boards.h" 32 #include "qemu/log.h" 33 #include "hw/loader.h" 34 #include "sysemu/blockdev.h" 35 #include "exec/address-spaces.h" 36 37 #define BIOS_FILENAME "ppc405_rom.bin" 38 #define BIOS_SIZE (2048 * 1024) 39 40 #define KERNEL_LOAD_ADDR 0x00000000 41 #define INITRD_LOAD_ADDR 0x01800000 42 43 #define USE_FLASH_BIOS 44 45 #define DEBUG_BOARD_INIT 46 47 /*****************************************************************************/ 48 /* PPC405EP reference board (IBM) */ 49 /* Standalone board with: 50 * - PowerPC 405EP CPU 51 * - SDRAM (0x00000000) 52 * - Flash (0xFFF80000) 53 * - SRAM (0xFFF00000) 54 * - NVRAM (0xF0000000) 55 * - FPGA (0xF0300000) 56 */ 57 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 58 struct ref405ep_fpga_t { 59 uint8_t reg0; 60 uint8_t reg1; 61 }; 62 63 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 64 { 65 ref405ep_fpga_t *fpga; 66 uint32_t ret; 67 68 fpga = opaque; 69 switch (addr) { 70 case 0x0: 71 ret = fpga->reg0; 72 break; 73 case 0x1: 74 ret = fpga->reg1; 75 break; 76 default: 77 ret = 0; 78 break; 79 } 80 81 return ret; 82 } 83 84 static void ref405ep_fpga_writeb (void *opaque, 85 hwaddr addr, uint32_t value) 86 { 87 ref405ep_fpga_t *fpga; 88 89 fpga = opaque; 90 switch (addr) { 91 case 0x0: 92 /* Read only */ 93 break; 94 case 0x1: 95 fpga->reg1 = value; 96 break; 97 default: 98 break; 99 } 100 } 101 102 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 103 { 104 uint32_t ret; 105 106 ret = ref405ep_fpga_readb(opaque, addr) << 8; 107 ret |= ref405ep_fpga_readb(opaque, addr + 1); 108 109 return ret; 110 } 111 112 static void ref405ep_fpga_writew (void *opaque, 113 hwaddr addr, uint32_t value) 114 { 115 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 116 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 117 } 118 119 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 120 { 121 uint32_t ret; 122 123 ret = ref405ep_fpga_readb(opaque, addr) << 24; 124 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 125 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 126 ret |= ref405ep_fpga_readb(opaque, addr + 3); 127 128 return ret; 129 } 130 131 static void ref405ep_fpga_writel (void *opaque, 132 hwaddr addr, uint32_t value) 133 { 134 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 135 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 136 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 137 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 138 } 139 140 static const MemoryRegionOps ref405ep_fpga_ops = { 141 .old_mmio = { 142 .read = { 143 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 144 }, 145 .write = { 146 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 147 }, 148 }, 149 .endianness = DEVICE_NATIVE_ENDIAN, 150 }; 151 152 static void ref405ep_fpga_reset (void *opaque) 153 { 154 ref405ep_fpga_t *fpga; 155 156 fpga = opaque; 157 fpga->reg0 = 0x00; 158 fpga->reg1 = 0x0F; 159 } 160 161 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 162 { 163 ref405ep_fpga_t *fpga; 164 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 165 166 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 167 memory_region_init_io(fpga_memory, &ref405ep_fpga_ops, fpga, 168 "fpga", 0x00000100); 169 memory_region_add_subregion(sysmem, base, fpga_memory); 170 qemu_register_reset(&ref405ep_fpga_reset, fpga); 171 } 172 173 static void ref405ep_init(QEMUMachineInitArgs *args) 174 { 175 ram_addr_t ram_size = args->ram_size; 176 const char *kernel_filename = args->kernel_filename; 177 const char *kernel_cmdline = args->kernel_cmdline; 178 const char *initrd_filename = args->initrd_filename; 179 char *filename; 180 ppc4xx_bd_info_t bd; 181 CPUPPCState *env; 182 qemu_irq *pic; 183 MemoryRegion *bios; 184 MemoryRegion *sram = g_new(MemoryRegion, 1); 185 ram_addr_t bdloc; 186 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 187 hwaddr ram_bases[2], ram_sizes[2]; 188 target_ulong sram_size; 189 long bios_size; 190 //int phy_addr = 0; 191 //static int phy_addr = 1; 192 target_ulong kernel_base, initrd_base; 193 long kernel_size, initrd_size; 194 int linux_boot; 195 int fl_idx, fl_sectors, len; 196 DriveInfo *dinfo; 197 MemoryRegion *sysmem = get_system_memory(); 198 199 /* XXX: fix this */ 200 memory_region_init_ram(&ram_memories[0], "ef405ep.ram", 0x08000000); 201 vmstate_register_ram_global(&ram_memories[0]); 202 ram_bases[0] = 0; 203 ram_sizes[0] = 0x08000000; 204 memory_region_init(&ram_memories[1], "ef405ep.ram1", 0); 205 ram_bases[1] = 0x00000000; 206 ram_sizes[1] = 0x00000000; 207 ram_size = 128 * 1024 * 1024; 208 #ifdef DEBUG_BOARD_INIT 209 printf("%s: register cpu\n", __func__); 210 #endif 211 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 212 33333333, &pic, kernel_filename == NULL ? 0 : 1); 213 /* allocate SRAM */ 214 sram_size = 512 * 1024; 215 memory_region_init_ram(sram, "ef405ep.sram", sram_size); 216 vmstate_register_ram_global(sram); 217 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 218 /* allocate and load BIOS */ 219 #ifdef DEBUG_BOARD_INIT 220 printf("%s: register BIOS\n", __func__); 221 #endif 222 fl_idx = 0; 223 #ifdef USE_FLASH_BIOS 224 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 225 if (dinfo) { 226 bios_size = bdrv_getlength(dinfo->bdrv); 227 fl_sectors = (bios_size + 65535) >> 16; 228 #ifdef DEBUG_BOARD_INIT 229 printf("Register parallel flash %d size %lx" 230 " at addr %lx '%s' %d\n", 231 fl_idx, bios_size, -bios_size, 232 bdrv_get_device_name(dinfo->bdrv), fl_sectors); 233 #endif 234 pflash_cfi02_register((uint32_t)(-bios_size), 235 NULL, "ef405ep.bios", bios_size, 236 dinfo->bdrv, 65536, fl_sectors, 1, 237 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 238 1); 239 fl_idx++; 240 } else 241 #endif 242 { 243 #ifdef DEBUG_BOARD_INIT 244 printf("Load BIOS from file\n"); 245 #endif 246 bios = g_new(MemoryRegion, 1); 247 memory_region_init_ram(bios, "ef405ep.bios", BIOS_SIZE); 248 vmstate_register_ram_global(bios); 249 if (bios_name == NULL) 250 bios_name = BIOS_FILENAME; 251 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 252 if (filename) { 253 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 254 g_free(filename); 255 } else { 256 bios_size = -1; 257 } 258 if (bios_size < 0 || bios_size > BIOS_SIZE) { 259 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", 260 bios_name); 261 exit(1); 262 } 263 bios_size = (bios_size + 0xfff) & ~0xfff; 264 memory_region_set_readonly(bios, true); 265 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 266 } 267 /* Register FPGA */ 268 #ifdef DEBUG_BOARD_INIT 269 printf("%s: register FPGA\n", __func__); 270 #endif 271 ref405ep_fpga_init(sysmem, 0xF0300000); 272 /* Register NVRAM */ 273 #ifdef DEBUG_BOARD_INIT 274 printf("%s: register NVRAM\n", __func__); 275 #endif 276 m48t59_init(NULL, 0xF0000000, 0, 8192, 8); 277 /* Load kernel */ 278 linux_boot = (kernel_filename != NULL); 279 if (linux_boot) { 280 #ifdef DEBUG_BOARD_INIT 281 printf("%s: load kernel\n", __func__); 282 #endif 283 memset(&bd, 0, sizeof(bd)); 284 bd.bi_memstart = 0x00000000; 285 bd.bi_memsize = ram_size; 286 bd.bi_flashstart = -bios_size; 287 bd.bi_flashsize = -bios_size; 288 bd.bi_flashoffset = 0; 289 bd.bi_sramstart = 0xFFF00000; 290 bd.bi_sramsize = sram_size; 291 bd.bi_bootflags = 0; 292 bd.bi_intfreq = 133333333; 293 bd.bi_busfreq = 33333333; 294 bd.bi_baudrate = 115200; 295 bd.bi_s_version[0] = 'Q'; 296 bd.bi_s_version[1] = 'M'; 297 bd.bi_s_version[2] = 'U'; 298 bd.bi_s_version[3] = '\0'; 299 bd.bi_r_version[0] = 'Q'; 300 bd.bi_r_version[1] = 'E'; 301 bd.bi_r_version[2] = 'M'; 302 bd.bi_r_version[3] = 'U'; 303 bd.bi_r_version[4] = '\0'; 304 bd.bi_procfreq = 133333333; 305 bd.bi_plb_busfreq = 33333333; 306 bd.bi_pci_busfreq = 33333333; 307 bd.bi_opbfreq = 33333333; 308 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 309 env->gpr[3] = bdloc; 310 kernel_base = KERNEL_LOAD_ADDR; 311 /* now we can load the kernel */ 312 kernel_size = load_image_targphys(kernel_filename, kernel_base, 313 ram_size - kernel_base); 314 if (kernel_size < 0) { 315 fprintf(stderr, "qemu: could not load kernel '%s'\n", 316 kernel_filename); 317 exit(1); 318 } 319 printf("Load kernel size %ld at " TARGET_FMT_lx, 320 kernel_size, kernel_base); 321 /* load initrd */ 322 if (initrd_filename) { 323 initrd_base = INITRD_LOAD_ADDR; 324 initrd_size = load_image_targphys(initrd_filename, initrd_base, 325 ram_size - initrd_base); 326 if (initrd_size < 0) { 327 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 328 initrd_filename); 329 exit(1); 330 } 331 } else { 332 initrd_base = 0; 333 initrd_size = 0; 334 } 335 env->gpr[4] = initrd_base; 336 env->gpr[5] = initrd_size; 337 if (kernel_cmdline != NULL) { 338 len = strlen(kernel_cmdline); 339 bdloc -= ((len + 255) & ~255); 340 cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1); 341 env->gpr[6] = bdloc; 342 env->gpr[7] = bdloc + len; 343 } else { 344 env->gpr[6] = 0; 345 env->gpr[7] = 0; 346 } 347 env->nip = KERNEL_LOAD_ADDR; 348 } else { 349 kernel_base = 0; 350 kernel_size = 0; 351 initrd_base = 0; 352 initrd_size = 0; 353 bdloc = 0; 354 } 355 #ifdef DEBUG_BOARD_INIT 356 printf("%s: Done\n", __func__); 357 #endif 358 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 359 } 360 361 static QEMUMachine ref405ep_machine = { 362 .name = "ref405ep", 363 .desc = "ref405ep", 364 .init = ref405ep_init, 365 DEFAULT_MACHINE_OPTIONS, 366 }; 367 368 /*****************************************************************************/ 369 /* AMCC Taihu evaluation board */ 370 /* - PowerPC 405EP processor 371 * - SDRAM 128 MB at 0x00000000 372 * - Boot flash 2 MB at 0xFFE00000 373 * - Application flash 32 MB at 0xFC000000 374 * - 2 serial ports 375 * - 2 ethernet PHY 376 * - 1 USB 1.1 device 0x50000000 377 * - 1 LCD display 0x50100000 378 * - 1 CPLD 0x50100000 379 * - 1 I2C EEPROM 380 * - 1 I2C thermal sensor 381 * - a set of LEDs 382 * - bit-bang SPI port using GPIOs 383 * - 1 EBC interface connector 0 0x50200000 384 * - 1 cardbus controller + expansion slot. 385 * - 1 PCI expansion slot. 386 */ 387 typedef struct taihu_cpld_t taihu_cpld_t; 388 struct taihu_cpld_t { 389 uint8_t reg0; 390 uint8_t reg1; 391 }; 392 393 static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr) 394 { 395 taihu_cpld_t *cpld; 396 uint32_t ret; 397 398 cpld = opaque; 399 switch (addr) { 400 case 0x0: 401 ret = cpld->reg0; 402 break; 403 case 0x1: 404 ret = cpld->reg1; 405 break; 406 default: 407 ret = 0; 408 break; 409 } 410 411 return ret; 412 } 413 414 static void taihu_cpld_writeb (void *opaque, 415 hwaddr addr, uint32_t value) 416 { 417 taihu_cpld_t *cpld; 418 419 cpld = opaque; 420 switch (addr) { 421 case 0x0: 422 /* Read only */ 423 break; 424 case 0x1: 425 cpld->reg1 = value; 426 break; 427 default: 428 break; 429 } 430 } 431 432 static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr) 433 { 434 uint32_t ret; 435 436 ret = taihu_cpld_readb(opaque, addr) << 8; 437 ret |= taihu_cpld_readb(opaque, addr + 1); 438 439 return ret; 440 } 441 442 static void taihu_cpld_writew (void *opaque, 443 hwaddr addr, uint32_t value) 444 { 445 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); 446 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); 447 } 448 449 static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr) 450 { 451 uint32_t ret; 452 453 ret = taihu_cpld_readb(opaque, addr) << 24; 454 ret |= taihu_cpld_readb(opaque, addr + 1) << 16; 455 ret |= taihu_cpld_readb(opaque, addr + 2) << 8; 456 ret |= taihu_cpld_readb(opaque, addr + 3); 457 458 return ret; 459 } 460 461 static void taihu_cpld_writel (void *opaque, 462 hwaddr addr, uint32_t value) 463 { 464 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); 465 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); 466 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); 467 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); 468 } 469 470 static const MemoryRegionOps taihu_cpld_ops = { 471 .old_mmio = { 472 .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, 473 .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, 474 }, 475 .endianness = DEVICE_NATIVE_ENDIAN, 476 }; 477 478 static void taihu_cpld_reset (void *opaque) 479 { 480 taihu_cpld_t *cpld; 481 482 cpld = opaque; 483 cpld->reg0 = 0x01; 484 cpld->reg1 = 0x80; 485 } 486 487 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 488 { 489 taihu_cpld_t *cpld; 490 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 491 492 cpld = g_malloc0(sizeof(taihu_cpld_t)); 493 memory_region_init_io(cpld_memory, &taihu_cpld_ops, cpld, "cpld", 0x100); 494 memory_region_add_subregion(sysmem, base, cpld_memory); 495 qemu_register_reset(&taihu_cpld_reset, cpld); 496 } 497 498 static void taihu_405ep_init(QEMUMachineInitArgs *args) 499 { 500 ram_addr_t ram_size = args->ram_size; 501 const char *kernel_filename = args->kernel_filename; 502 const char *initrd_filename = args->initrd_filename; 503 char *filename; 504 qemu_irq *pic; 505 MemoryRegion *sysmem = get_system_memory(); 506 MemoryRegion *bios; 507 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 508 hwaddr ram_bases[2], ram_sizes[2]; 509 long bios_size; 510 target_ulong kernel_base, initrd_base; 511 long kernel_size, initrd_size; 512 int linux_boot; 513 int fl_idx, fl_sectors; 514 DriveInfo *dinfo; 515 516 /* RAM is soldered to the board so the size cannot be changed */ 517 memory_region_init_ram(&ram_memories[0], 518 "taihu_405ep.ram-0", 0x04000000); 519 vmstate_register_ram_global(&ram_memories[0]); 520 ram_bases[0] = 0; 521 ram_sizes[0] = 0x04000000; 522 memory_region_init_ram(&ram_memories[1], 523 "taihu_405ep.ram-1", 0x04000000); 524 vmstate_register_ram_global(&ram_memories[1]); 525 ram_bases[1] = 0x04000000; 526 ram_sizes[1] = 0x04000000; 527 ram_size = 0x08000000; 528 #ifdef DEBUG_BOARD_INIT 529 printf("%s: register cpu\n", __func__); 530 #endif 531 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 532 33333333, &pic, kernel_filename == NULL ? 0 : 1); 533 /* allocate and load BIOS */ 534 #ifdef DEBUG_BOARD_INIT 535 printf("%s: register BIOS\n", __func__); 536 #endif 537 fl_idx = 0; 538 #if defined(USE_FLASH_BIOS) 539 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 540 if (dinfo) { 541 bios_size = bdrv_getlength(dinfo->bdrv); 542 /* XXX: should check that size is 2MB */ 543 // bios_size = 2 * 1024 * 1024; 544 fl_sectors = (bios_size + 65535) >> 16; 545 #ifdef DEBUG_BOARD_INIT 546 printf("Register parallel flash %d size %lx" 547 " at addr %lx '%s' %d\n", 548 fl_idx, bios_size, -bios_size, 549 bdrv_get_device_name(dinfo->bdrv), fl_sectors); 550 #endif 551 pflash_cfi02_register((uint32_t)(-bios_size), 552 NULL, "taihu_405ep.bios", bios_size, 553 dinfo->bdrv, 65536, fl_sectors, 1, 554 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 555 1); 556 fl_idx++; 557 } else 558 #endif 559 { 560 #ifdef DEBUG_BOARD_INIT 561 printf("Load BIOS from file\n"); 562 #endif 563 if (bios_name == NULL) 564 bios_name = BIOS_FILENAME; 565 bios = g_new(MemoryRegion, 1); 566 memory_region_init_ram(bios, "taihu_405ep.bios", BIOS_SIZE); 567 vmstate_register_ram_global(bios); 568 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 569 if (filename) { 570 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 571 g_free(filename); 572 } else { 573 bios_size = -1; 574 } 575 if (bios_size < 0 || bios_size > BIOS_SIZE) { 576 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", 577 bios_name); 578 exit(1); 579 } 580 bios_size = (bios_size + 0xfff) & ~0xfff; 581 memory_region_set_readonly(bios, true); 582 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 583 } 584 /* Register Linux flash */ 585 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 586 if (dinfo) { 587 bios_size = bdrv_getlength(dinfo->bdrv); 588 /* XXX: should check that size is 32MB */ 589 bios_size = 32 * 1024 * 1024; 590 fl_sectors = (bios_size + 65535) >> 16; 591 #ifdef DEBUG_BOARD_INIT 592 printf("Register parallel flash %d size %lx" 593 " at addr " TARGET_FMT_lx " '%s'\n", 594 fl_idx, bios_size, (target_ulong)0xfc000000, 595 bdrv_get_device_name(dinfo->bdrv)); 596 #endif 597 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 598 dinfo->bdrv, 65536, fl_sectors, 1, 599 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 600 1); 601 fl_idx++; 602 } 603 /* Register CLPD & LCD display */ 604 #ifdef DEBUG_BOARD_INIT 605 printf("%s: register CPLD\n", __func__); 606 #endif 607 taihu_cpld_init(sysmem, 0x50100000); 608 /* Load kernel */ 609 linux_boot = (kernel_filename != NULL); 610 if (linux_boot) { 611 #ifdef DEBUG_BOARD_INIT 612 printf("%s: load kernel\n", __func__); 613 #endif 614 kernel_base = KERNEL_LOAD_ADDR; 615 /* now we can load the kernel */ 616 kernel_size = load_image_targphys(kernel_filename, kernel_base, 617 ram_size - kernel_base); 618 if (kernel_size < 0) { 619 fprintf(stderr, "qemu: could not load kernel '%s'\n", 620 kernel_filename); 621 exit(1); 622 } 623 /* load initrd */ 624 if (initrd_filename) { 625 initrd_base = INITRD_LOAD_ADDR; 626 initrd_size = load_image_targphys(initrd_filename, initrd_base, 627 ram_size - initrd_base); 628 if (initrd_size < 0) { 629 fprintf(stderr, 630 "qemu: could not load initial ram disk '%s'\n", 631 initrd_filename); 632 exit(1); 633 } 634 } else { 635 initrd_base = 0; 636 initrd_size = 0; 637 } 638 } else { 639 kernel_base = 0; 640 kernel_size = 0; 641 initrd_base = 0; 642 initrd_size = 0; 643 } 644 #ifdef DEBUG_BOARD_INIT 645 printf("%s: Done\n", __func__); 646 #endif 647 } 648 649 static QEMUMachine taihu_machine = { 650 .name = "taihu", 651 .desc = "taihu", 652 .init = taihu_405ep_init, 653 DEFAULT_MACHINE_OPTIONS, 654 }; 655 656 static void ppc405_machine_init(void) 657 { 658 qemu_register_machine(&ref405ep_machine); 659 qemu_register_machine(&taihu_machine); 660 } 661 662 machine_init(ppc405_machine_init); 663