1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "cpu.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "ppc405.h" 35 #include "hw/rtc/m48t59.h" 36 #include "hw/block/flash.h" 37 #include "sysemu/sysemu.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/block-backend.h" 41 #include "hw/boards.h" 42 #include "qemu/error-report.h" 43 #include "hw/loader.h" 44 #include "exec/address-spaces.h" 45 #include "qemu/cutils.h" 46 47 #define BIOS_FILENAME "ppc405_rom.bin" 48 #define BIOS_SIZE (2 * MiB) 49 50 #define KERNEL_LOAD_ADDR 0x00000000 51 #define INITRD_LOAD_ADDR 0x01800000 52 53 #define USE_FLASH_BIOS 54 55 /*****************************************************************************/ 56 /* PPC405EP reference board (IBM) */ 57 /* Standalone board with: 58 * - PowerPC 405EP CPU 59 * - SDRAM (0x00000000) 60 * - Flash (0xFFF80000) 61 * - SRAM (0xFFF00000) 62 * - NVRAM (0xF0000000) 63 * - FPGA (0xF0300000) 64 */ 65 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 66 struct ref405ep_fpga_t { 67 uint8_t reg0; 68 uint8_t reg1; 69 }; 70 71 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) 72 { 73 ref405ep_fpga_t *fpga; 74 uint32_t ret; 75 76 fpga = opaque; 77 switch (addr) { 78 case 0x0: 79 ret = fpga->reg0; 80 break; 81 case 0x1: 82 ret = fpga->reg1; 83 break; 84 default: 85 ret = 0; 86 break; 87 } 88 89 return ret; 90 } 91 92 static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, 93 unsigned size) 94 { 95 ref405ep_fpga_t *fpga; 96 97 fpga = opaque; 98 switch (addr) { 99 case 0x0: 100 /* Read only */ 101 break; 102 case 0x1: 103 fpga->reg1 = value; 104 break; 105 default: 106 break; 107 } 108 } 109 110 static const MemoryRegionOps ref405ep_fpga_ops = { 111 .read = ref405ep_fpga_readb, 112 .write = ref405ep_fpga_writeb, 113 .impl.min_access_size = 1, 114 .impl.max_access_size = 1, 115 .valid.min_access_size = 1, 116 .valid.max_access_size = 4, 117 .endianness = DEVICE_BIG_ENDIAN, 118 }; 119 120 static void ref405ep_fpga_reset (void *opaque) 121 { 122 ref405ep_fpga_t *fpga; 123 124 fpga = opaque; 125 fpga->reg0 = 0x00; 126 fpga->reg1 = 0x0F; 127 } 128 129 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 130 { 131 ref405ep_fpga_t *fpga; 132 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 133 134 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 135 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 136 "fpga", 0x00000100); 137 memory_region_add_subregion(sysmem, base, fpga_memory); 138 qemu_register_reset(&ref405ep_fpga_reset, fpga); 139 } 140 141 static void ref405ep_init(MachineState *machine) 142 { 143 MachineClass *mc = MACHINE_GET_CLASS(machine); 144 const char *bios_name = machine->firmware ?: BIOS_FILENAME; 145 const char *kernel_filename = machine->kernel_filename; 146 const char *kernel_cmdline = machine->kernel_cmdline; 147 const char *initrd_filename = machine->initrd_filename; 148 char *filename; 149 ppc4xx_bd_info_t bd; 150 CPUPPCState *env; 151 DeviceState *dev; 152 SysBusDevice *s; 153 MemoryRegion *bios; 154 MemoryRegion *sram = g_new(MemoryRegion, 1); 155 ram_addr_t bdloc; 156 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 157 hwaddr ram_bases[2], ram_sizes[2]; 158 target_ulong sram_size; 159 long bios_size; 160 //int phy_addr = 0; 161 //static int phy_addr = 1; 162 target_ulong kernel_base, initrd_base; 163 long kernel_size, initrd_size; 164 int linux_boot; 165 int len; 166 DriveInfo *dinfo; 167 MemoryRegion *sysmem = get_system_memory(); 168 DeviceState *uicdev; 169 170 if (machine->ram_size != mc->default_ram_size) { 171 char *sz = size_to_str(mc->default_ram_size); 172 error_report("Invalid RAM size, should be %s", sz); 173 g_free(sz); 174 exit(EXIT_FAILURE); 175 } 176 177 /* XXX: fix this */ 178 memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias", 179 machine->ram, 0, machine->ram_size); 180 ram_bases[0] = 0; 181 ram_sizes[0] = machine->ram_size; 182 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 183 ram_bases[1] = 0x00000000; 184 ram_sizes[1] = 0x00000000; 185 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 186 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); 187 /* allocate SRAM */ 188 sram_size = 512 * KiB; 189 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 190 &error_fatal); 191 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 192 /* allocate and load BIOS */ 193 #ifdef USE_FLASH_BIOS 194 dinfo = drive_get(IF_PFLASH, 0, 0); 195 if (dinfo) { 196 bios_size = 8 * MiB; 197 pflash_cfi02_register((uint32_t)(-bios_size), 198 "ef405ep.bios", bios_size, 199 blk_by_legacy_dinfo(dinfo), 200 64 * KiB, 1, 201 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 202 1); 203 } else 204 #endif 205 { 206 bios = g_new(MemoryRegion, 1); 207 memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, 208 &error_fatal); 209 210 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 211 if (filename) { 212 bios_size = load_image_size(filename, 213 memory_region_get_ram_ptr(bios), 214 BIOS_SIZE); 215 g_free(filename); 216 if (bios_size < 0) { 217 error_report("Could not load PowerPC BIOS '%s'", bios_name); 218 exit(1); 219 } 220 bios_size = (bios_size + 0xfff) & ~0xfff; 221 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 222 } else if (!qtest_enabled() || kernel_filename != NULL) { 223 error_report("Could not load PowerPC BIOS '%s'", bios_name); 224 exit(1); 225 } else { 226 /* Avoid an uninitialized variable warning */ 227 bios_size = -1; 228 } 229 } 230 /* Register FPGA */ 231 ref405ep_fpga_init(sysmem, 0xF0300000); 232 /* Register NVRAM */ 233 dev = qdev_new("sysbus-m48t08"); 234 qdev_prop_set_int32(dev, "base-year", 1968); 235 s = SYS_BUS_DEVICE(dev); 236 sysbus_realize_and_unref(s, &error_fatal); 237 sysbus_mmio_map(s, 0, 0xF0000000); 238 /* Load kernel */ 239 linux_boot = (kernel_filename != NULL); 240 if (linux_boot) { 241 memset(&bd, 0, sizeof(bd)); 242 bd.bi_memstart = 0x00000000; 243 bd.bi_memsize = machine->ram_size; 244 bd.bi_flashstart = -bios_size; 245 bd.bi_flashsize = -bios_size; 246 bd.bi_flashoffset = 0; 247 bd.bi_sramstart = 0xFFF00000; 248 bd.bi_sramsize = sram_size; 249 bd.bi_bootflags = 0; 250 bd.bi_intfreq = 133333333; 251 bd.bi_busfreq = 33333333; 252 bd.bi_baudrate = 115200; 253 bd.bi_s_version[0] = 'Q'; 254 bd.bi_s_version[1] = 'M'; 255 bd.bi_s_version[2] = 'U'; 256 bd.bi_s_version[3] = '\0'; 257 bd.bi_r_version[0] = 'Q'; 258 bd.bi_r_version[1] = 'E'; 259 bd.bi_r_version[2] = 'M'; 260 bd.bi_r_version[3] = 'U'; 261 bd.bi_r_version[4] = '\0'; 262 bd.bi_procfreq = 133333333; 263 bd.bi_plb_busfreq = 33333333; 264 bd.bi_pci_busfreq = 33333333; 265 bd.bi_opbfreq = 33333333; 266 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 267 env->gpr[3] = bdloc; 268 kernel_base = KERNEL_LOAD_ADDR; 269 /* now we can load the kernel */ 270 kernel_size = load_image_targphys(kernel_filename, kernel_base, 271 machine->ram_size - kernel_base); 272 if (kernel_size < 0) { 273 error_report("could not load kernel '%s'", kernel_filename); 274 exit(1); 275 } 276 printf("Load kernel size %ld at " TARGET_FMT_lx, 277 kernel_size, kernel_base); 278 /* load initrd */ 279 if (initrd_filename) { 280 initrd_base = INITRD_LOAD_ADDR; 281 initrd_size = load_image_targphys(initrd_filename, initrd_base, 282 machine->ram_size - initrd_base); 283 if (initrd_size < 0) { 284 error_report("could not load initial ram disk '%s'", 285 initrd_filename); 286 exit(1); 287 } 288 } else { 289 initrd_base = 0; 290 initrd_size = 0; 291 } 292 env->gpr[4] = initrd_base; 293 env->gpr[5] = initrd_size; 294 if (kernel_cmdline != NULL) { 295 len = strlen(kernel_cmdline); 296 bdloc -= ((len + 255) & ~255); 297 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 298 env->gpr[6] = bdloc; 299 env->gpr[7] = bdloc + len; 300 } else { 301 env->gpr[6] = 0; 302 env->gpr[7] = 0; 303 } 304 env->nip = KERNEL_LOAD_ADDR; 305 } else { 306 kernel_base = 0; 307 kernel_size = 0; 308 initrd_base = 0; 309 initrd_size = 0; 310 bdloc = 0; 311 } 312 } 313 314 static void ref405ep_class_init(ObjectClass *oc, void *data) 315 { 316 MachineClass *mc = MACHINE_CLASS(oc); 317 318 mc->desc = "ref405ep"; 319 mc->init = ref405ep_init; 320 mc->default_ram_size = 0x08000000; 321 mc->default_ram_id = "ef405ep.ram"; 322 } 323 324 static const TypeInfo ref405ep_type = { 325 .name = MACHINE_TYPE_NAME("ref405ep"), 326 .parent = TYPE_MACHINE, 327 .class_init = ref405ep_class_init, 328 }; 329 330 /*****************************************************************************/ 331 /* AMCC Taihu evaluation board */ 332 /* - PowerPC 405EP processor 333 * - SDRAM 128 MB at 0x00000000 334 * - Boot flash 2 MB at 0xFFE00000 335 * - Application flash 32 MB at 0xFC000000 336 * - 2 serial ports 337 * - 2 ethernet PHY 338 * - 1 USB 1.1 device 0x50000000 339 * - 1 LCD display 0x50100000 340 * - 1 CPLD 0x50100000 341 * - 1 I2C EEPROM 342 * - 1 I2C thermal sensor 343 * - a set of LEDs 344 * - bit-bang SPI port using GPIOs 345 * - 1 EBC interface connector 0 0x50200000 346 * - 1 cardbus controller + expansion slot. 347 * - 1 PCI expansion slot. 348 */ 349 typedef struct taihu_cpld_t taihu_cpld_t; 350 struct taihu_cpld_t { 351 uint8_t reg0; 352 uint8_t reg1; 353 }; 354 355 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 356 { 357 taihu_cpld_t *cpld; 358 uint32_t ret; 359 360 cpld = opaque; 361 switch (addr) { 362 case 0x0: 363 ret = cpld->reg0; 364 break; 365 case 0x1: 366 ret = cpld->reg1; 367 break; 368 default: 369 ret = 0; 370 break; 371 } 372 373 return ret; 374 } 375 376 static void taihu_cpld_write(void *opaque, hwaddr addr, 377 uint64_t value, unsigned size) 378 { 379 taihu_cpld_t *cpld; 380 381 cpld = opaque; 382 switch (addr) { 383 case 0x0: 384 /* Read only */ 385 break; 386 case 0x1: 387 cpld->reg1 = value; 388 break; 389 default: 390 break; 391 } 392 } 393 394 static const MemoryRegionOps taihu_cpld_ops = { 395 .read = taihu_cpld_read, 396 .write = taihu_cpld_write, 397 .impl = { 398 .min_access_size = 1, 399 .max_access_size = 1, 400 }, 401 .endianness = DEVICE_NATIVE_ENDIAN, 402 }; 403 404 static void taihu_cpld_reset (void *opaque) 405 { 406 taihu_cpld_t *cpld; 407 408 cpld = opaque; 409 cpld->reg0 = 0x01; 410 cpld->reg1 = 0x80; 411 } 412 413 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 414 { 415 taihu_cpld_t *cpld; 416 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 417 418 cpld = g_malloc0(sizeof(taihu_cpld_t)); 419 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 420 memory_region_add_subregion(sysmem, base, cpld_memory); 421 qemu_register_reset(&taihu_cpld_reset, cpld); 422 } 423 424 static void taihu_405ep_init(MachineState *machine) 425 { 426 MachineClass *mc = MACHINE_GET_CLASS(machine); 427 const char *bios_name = machine->firmware ?: BIOS_FILENAME; 428 const char *kernel_filename = machine->kernel_filename; 429 const char *initrd_filename = machine->initrd_filename; 430 char *filename; 431 MemoryRegion *sysmem = get_system_memory(); 432 MemoryRegion *bios; 433 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 434 hwaddr ram_bases[2], ram_sizes[2]; 435 long bios_size; 436 target_ulong kernel_base, initrd_base; 437 long kernel_size, initrd_size; 438 int linux_boot; 439 int fl_idx; 440 DriveInfo *dinfo; 441 DeviceState *uicdev; 442 443 if (machine->ram_size != mc->default_ram_size) { 444 char *sz = size_to_str(mc->default_ram_size); 445 error_report("Invalid RAM size, should be %s", sz); 446 g_free(sz); 447 exit(EXIT_FAILURE); 448 } 449 450 ram_bases[0] = 0; 451 ram_sizes[0] = 0x04000000; 452 memory_region_init_alias(&ram_memories[0], NULL, 453 "taihu_405ep.ram-0", machine->ram, ram_bases[0], 454 ram_sizes[0]); 455 ram_bases[1] = 0x04000000; 456 ram_sizes[1] = 0x04000000; 457 memory_region_init_alias(&ram_memories[1], NULL, 458 "taihu_405ep.ram-1", machine->ram, ram_bases[1], 459 ram_sizes[1]); 460 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 461 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); 462 /* allocate and load BIOS */ 463 fl_idx = 0; 464 #if defined(USE_FLASH_BIOS) 465 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 466 if (dinfo) { 467 bios_size = 2 * MiB; 468 pflash_cfi02_register(0xFFE00000, 469 "taihu_405ep.bios", bios_size, 470 blk_by_legacy_dinfo(dinfo), 471 64 * KiB, 1, 472 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 473 1); 474 fl_idx++; 475 } else 476 #endif 477 { 478 bios = g_new(MemoryRegion, 1); 479 memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 480 &error_fatal); 481 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 482 if (filename) { 483 bios_size = load_image_size(filename, 484 memory_region_get_ram_ptr(bios), 485 BIOS_SIZE); 486 g_free(filename); 487 if (bios_size < 0) { 488 error_report("Could not load PowerPC BIOS '%s'", bios_name); 489 exit(1); 490 } 491 bios_size = (bios_size + 0xfff) & ~0xfff; 492 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 493 } else if (!qtest_enabled()) { 494 error_report("Could not load PowerPC BIOS '%s'", bios_name); 495 exit(1); 496 } 497 } 498 /* Register Linux flash */ 499 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 500 if (dinfo) { 501 bios_size = 32 * MiB; 502 pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size, 503 blk_by_legacy_dinfo(dinfo), 504 64 * KiB, 1, 505 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 506 1); 507 fl_idx++; 508 } 509 /* Register CLPD & LCD display */ 510 taihu_cpld_init(sysmem, 0x50100000); 511 /* Load kernel */ 512 linux_boot = (kernel_filename != NULL); 513 if (linux_boot) { 514 kernel_base = KERNEL_LOAD_ADDR; 515 /* now we can load the kernel */ 516 kernel_size = load_image_targphys(kernel_filename, kernel_base, 517 machine->ram_size - kernel_base); 518 if (kernel_size < 0) { 519 error_report("could not load kernel '%s'", kernel_filename); 520 exit(1); 521 } 522 /* load initrd */ 523 if (initrd_filename) { 524 initrd_base = INITRD_LOAD_ADDR; 525 initrd_size = load_image_targphys(initrd_filename, initrd_base, 526 machine->ram_size - initrd_base); 527 if (initrd_size < 0) { 528 error_report("could not load initial ram disk '%s'", 529 initrd_filename); 530 exit(1); 531 } 532 } else { 533 initrd_base = 0; 534 initrd_size = 0; 535 } 536 } else { 537 kernel_base = 0; 538 kernel_size = 0; 539 initrd_base = 0; 540 initrd_size = 0; 541 } 542 } 543 544 static void taihu_class_init(ObjectClass *oc, void *data) 545 { 546 MachineClass *mc = MACHINE_CLASS(oc); 547 548 mc->desc = "taihu"; 549 mc->init = taihu_405ep_init; 550 mc->default_ram_size = 0x08000000; 551 mc->default_ram_id = "taihu_405ep.ram"; 552 } 553 554 static const TypeInfo taihu_type = { 555 .name = MACHINE_TYPE_NAME("taihu"), 556 .parent = TYPE_MACHINE, 557 .class_init = taihu_class_init, 558 }; 559 560 static void ppc405_machine_init(void) 561 { 562 type_register_static(&ref405ep_type); 563 type_register_static(&taihu_type); 564 } 565 566 type_init(ppc405_machine_init) 567