1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "hw/hw.h" 27 #include "hw/ppc/ppc.h" 28 #include "ppc405.h" 29 #include "hw/timer/m48t59.h" 30 #include "hw/block/flash.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/qtest.h" 33 #include "sysemu/block-backend.h" 34 #include "hw/boards.h" 35 #include "qemu/log.h" 36 #include "qemu/error-report.h" 37 #include "hw/loader.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/blockdev.h" 40 #include "exec/address-spaces.h" 41 42 #define BIOS_FILENAME "ppc405_rom.bin" 43 #define BIOS_SIZE (2048 * 1024) 44 45 #define KERNEL_LOAD_ADDR 0x00000000 46 #define INITRD_LOAD_ADDR 0x01800000 47 48 #define USE_FLASH_BIOS 49 50 //#define DEBUG_BOARD_INIT 51 52 /*****************************************************************************/ 53 /* PPC405EP reference board (IBM) */ 54 /* Standalone board with: 55 * - PowerPC 405EP CPU 56 * - SDRAM (0x00000000) 57 * - Flash (0xFFF80000) 58 * - SRAM (0xFFF00000) 59 * - NVRAM (0xF0000000) 60 * - FPGA (0xF0300000) 61 */ 62 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 63 struct ref405ep_fpga_t { 64 uint8_t reg0; 65 uint8_t reg1; 66 }; 67 68 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 69 { 70 ref405ep_fpga_t *fpga; 71 uint32_t ret; 72 73 fpga = opaque; 74 switch (addr) { 75 case 0x0: 76 ret = fpga->reg0; 77 break; 78 case 0x1: 79 ret = fpga->reg1; 80 break; 81 default: 82 ret = 0; 83 break; 84 } 85 86 return ret; 87 } 88 89 static void ref405ep_fpga_writeb (void *opaque, 90 hwaddr addr, uint32_t value) 91 { 92 ref405ep_fpga_t *fpga; 93 94 fpga = opaque; 95 switch (addr) { 96 case 0x0: 97 /* Read only */ 98 break; 99 case 0x1: 100 fpga->reg1 = value; 101 break; 102 default: 103 break; 104 } 105 } 106 107 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 108 { 109 uint32_t ret; 110 111 ret = ref405ep_fpga_readb(opaque, addr) << 8; 112 ret |= ref405ep_fpga_readb(opaque, addr + 1); 113 114 return ret; 115 } 116 117 static void ref405ep_fpga_writew (void *opaque, 118 hwaddr addr, uint32_t value) 119 { 120 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 121 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 122 } 123 124 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 125 { 126 uint32_t ret; 127 128 ret = ref405ep_fpga_readb(opaque, addr) << 24; 129 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 130 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 131 ret |= ref405ep_fpga_readb(opaque, addr + 3); 132 133 return ret; 134 } 135 136 static void ref405ep_fpga_writel (void *opaque, 137 hwaddr addr, uint32_t value) 138 { 139 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 140 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 141 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 142 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 143 } 144 145 static const MemoryRegionOps ref405ep_fpga_ops = { 146 .old_mmio = { 147 .read = { 148 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 149 }, 150 .write = { 151 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 152 }, 153 }, 154 .endianness = DEVICE_NATIVE_ENDIAN, 155 }; 156 157 static void ref405ep_fpga_reset (void *opaque) 158 { 159 ref405ep_fpga_t *fpga; 160 161 fpga = opaque; 162 fpga->reg0 = 0x00; 163 fpga->reg1 = 0x0F; 164 } 165 166 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 167 { 168 ref405ep_fpga_t *fpga; 169 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 170 171 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 172 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 173 "fpga", 0x00000100); 174 memory_region_add_subregion(sysmem, base, fpga_memory); 175 qemu_register_reset(&ref405ep_fpga_reset, fpga); 176 } 177 178 static void ref405ep_init(MachineState *machine) 179 { 180 ram_addr_t ram_size = machine->ram_size; 181 const char *kernel_filename = machine->kernel_filename; 182 const char *kernel_cmdline = machine->kernel_cmdline; 183 const char *initrd_filename = machine->initrd_filename; 184 char *filename; 185 ppc4xx_bd_info_t bd; 186 CPUPPCState *env; 187 qemu_irq *pic; 188 MemoryRegion *bios; 189 MemoryRegion *sram = g_new(MemoryRegion, 1); 190 ram_addr_t bdloc; 191 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 192 hwaddr ram_bases[2], ram_sizes[2]; 193 target_ulong sram_size; 194 long bios_size; 195 //int phy_addr = 0; 196 //static int phy_addr = 1; 197 target_ulong kernel_base, initrd_base; 198 long kernel_size, initrd_size; 199 int linux_boot; 200 int fl_idx, fl_sectors, len; 201 DriveInfo *dinfo; 202 MemoryRegion *sysmem = get_system_memory(); 203 204 /* XXX: fix this */ 205 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 206 0x08000000); 207 ram_bases[0] = 0; 208 ram_sizes[0] = 0x08000000; 209 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 210 ram_bases[1] = 0x00000000; 211 ram_sizes[1] = 0x00000000; 212 ram_size = 128 * 1024 * 1024; 213 #ifdef DEBUG_BOARD_INIT 214 printf("%s: register cpu\n", __func__); 215 #endif 216 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 217 33333333, &pic, kernel_filename == NULL ? 0 : 1); 218 /* allocate SRAM */ 219 sram_size = 512 * 1024; 220 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 221 &error_fatal); 222 vmstate_register_ram_global(sram); 223 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 224 /* allocate and load BIOS */ 225 #ifdef DEBUG_BOARD_INIT 226 printf("%s: register BIOS\n", __func__); 227 #endif 228 fl_idx = 0; 229 #ifdef USE_FLASH_BIOS 230 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 231 if (dinfo) { 232 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 233 234 bios_size = blk_getlength(blk); 235 fl_sectors = (bios_size + 65535) >> 16; 236 #ifdef DEBUG_BOARD_INIT 237 printf("Register parallel flash %d size %lx" 238 " at addr %lx '%s' %d\n", 239 fl_idx, bios_size, -bios_size, 240 blk_name(blk), fl_sectors); 241 #endif 242 pflash_cfi02_register((uint32_t)(-bios_size), 243 NULL, "ef405ep.bios", bios_size, 244 blk, 65536, fl_sectors, 1, 245 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 246 1); 247 fl_idx++; 248 } else 249 #endif 250 { 251 #ifdef DEBUG_BOARD_INIT 252 printf("Load BIOS from file\n"); 253 #endif 254 bios = g_new(MemoryRegion, 1); 255 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 256 &error_fatal); 257 vmstate_register_ram_global(bios); 258 259 if (bios_name == NULL) 260 bios_name = BIOS_FILENAME; 261 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 262 if (filename) { 263 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 264 g_free(filename); 265 if (bios_size < 0 || bios_size > BIOS_SIZE) { 266 error_report("Could not load PowerPC BIOS '%s'", bios_name); 267 exit(1); 268 } 269 bios_size = (bios_size + 0xfff) & ~0xfff; 270 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 271 } else if (!qtest_enabled() || kernel_filename != NULL) { 272 error_report("Could not load PowerPC BIOS '%s'", bios_name); 273 exit(1); 274 } else { 275 /* Avoid an uninitialized variable warning */ 276 bios_size = -1; 277 } 278 memory_region_set_readonly(bios, true); 279 } 280 /* Register FPGA */ 281 #ifdef DEBUG_BOARD_INIT 282 printf("%s: register FPGA\n", __func__); 283 #endif 284 ref405ep_fpga_init(sysmem, 0xF0300000); 285 /* Register NVRAM */ 286 #ifdef DEBUG_BOARD_INIT 287 printf("%s: register NVRAM\n", __func__); 288 #endif 289 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 290 /* Load kernel */ 291 linux_boot = (kernel_filename != NULL); 292 if (linux_boot) { 293 #ifdef DEBUG_BOARD_INIT 294 printf("%s: load kernel\n", __func__); 295 #endif 296 memset(&bd, 0, sizeof(bd)); 297 bd.bi_memstart = 0x00000000; 298 bd.bi_memsize = ram_size; 299 bd.bi_flashstart = -bios_size; 300 bd.bi_flashsize = -bios_size; 301 bd.bi_flashoffset = 0; 302 bd.bi_sramstart = 0xFFF00000; 303 bd.bi_sramsize = sram_size; 304 bd.bi_bootflags = 0; 305 bd.bi_intfreq = 133333333; 306 bd.bi_busfreq = 33333333; 307 bd.bi_baudrate = 115200; 308 bd.bi_s_version[0] = 'Q'; 309 bd.bi_s_version[1] = 'M'; 310 bd.bi_s_version[2] = 'U'; 311 bd.bi_s_version[3] = '\0'; 312 bd.bi_r_version[0] = 'Q'; 313 bd.bi_r_version[1] = 'E'; 314 bd.bi_r_version[2] = 'M'; 315 bd.bi_r_version[3] = 'U'; 316 bd.bi_r_version[4] = '\0'; 317 bd.bi_procfreq = 133333333; 318 bd.bi_plb_busfreq = 33333333; 319 bd.bi_pci_busfreq = 33333333; 320 bd.bi_opbfreq = 33333333; 321 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 322 env->gpr[3] = bdloc; 323 kernel_base = KERNEL_LOAD_ADDR; 324 /* now we can load the kernel */ 325 kernel_size = load_image_targphys(kernel_filename, kernel_base, 326 ram_size - kernel_base); 327 if (kernel_size < 0) { 328 fprintf(stderr, "qemu: could not load kernel '%s'\n", 329 kernel_filename); 330 exit(1); 331 } 332 printf("Load kernel size %ld at " TARGET_FMT_lx, 333 kernel_size, kernel_base); 334 /* load initrd */ 335 if (initrd_filename) { 336 initrd_base = INITRD_LOAD_ADDR; 337 initrd_size = load_image_targphys(initrd_filename, initrd_base, 338 ram_size - initrd_base); 339 if (initrd_size < 0) { 340 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 341 initrd_filename); 342 exit(1); 343 } 344 } else { 345 initrd_base = 0; 346 initrd_size = 0; 347 } 348 env->gpr[4] = initrd_base; 349 env->gpr[5] = initrd_size; 350 if (kernel_cmdline != NULL) { 351 len = strlen(kernel_cmdline); 352 bdloc -= ((len + 255) & ~255); 353 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 354 env->gpr[6] = bdloc; 355 env->gpr[7] = bdloc + len; 356 } else { 357 env->gpr[6] = 0; 358 env->gpr[7] = 0; 359 } 360 env->nip = KERNEL_LOAD_ADDR; 361 } else { 362 kernel_base = 0; 363 kernel_size = 0; 364 initrd_base = 0; 365 initrd_size = 0; 366 bdloc = 0; 367 } 368 #ifdef DEBUG_BOARD_INIT 369 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 370 printf("%s: Done\n", __func__); 371 #endif 372 } 373 374 static void ref405ep_class_init(ObjectClass *oc, void *data) 375 { 376 MachineClass *mc = MACHINE_CLASS(oc); 377 378 mc->desc = "ref405ep"; 379 mc->init = ref405ep_init; 380 } 381 382 static const TypeInfo ref405ep_type = { 383 .name = MACHINE_TYPE_NAME("ref405ep"), 384 .parent = TYPE_MACHINE, 385 .class_init = ref405ep_class_init, 386 }; 387 388 /*****************************************************************************/ 389 /* AMCC Taihu evaluation board */ 390 /* - PowerPC 405EP processor 391 * - SDRAM 128 MB at 0x00000000 392 * - Boot flash 2 MB at 0xFFE00000 393 * - Application flash 32 MB at 0xFC000000 394 * - 2 serial ports 395 * - 2 ethernet PHY 396 * - 1 USB 1.1 device 0x50000000 397 * - 1 LCD display 0x50100000 398 * - 1 CPLD 0x50100000 399 * - 1 I2C EEPROM 400 * - 1 I2C thermal sensor 401 * - a set of LEDs 402 * - bit-bang SPI port using GPIOs 403 * - 1 EBC interface connector 0 0x50200000 404 * - 1 cardbus controller + expansion slot. 405 * - 1 PCI expansion slot. 406 */ 407 typedef struct taihu_cpld_t taihu_cpld_t; 408 struct taihu_cpld_t { 409 uint8_t reg0; 410 uint8_t reg1; 411 }; 412 413 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 414 { 415 taihu_cpld_t *cpld; 416 uint32_t ret; 417 418 cpld = opaque; 419 switch (addr) { 420 case 0x0: 421 ret = cpld->reg0; 422 break; 423 case 0x1: 424 ret = cpld->reg1; 425 break; 426 default: 427 ret = 0; 428 break; 429 } 430 431 return ret; 432 } 433 434 static void taihu_cpld_write(void *opaque, hwaddr addr, 435 uint64_t value, unsigned size) 436 { 437 taihu_cpld_t *cpld; 438 439 cpld = opaque; 440 switch (addr) { 441 case 0x0: 442 /* Read only */ 443 break; 444 case 0x1: 445 cpld->reg1 = value; 446 break; 447 default: 448 break; 449 } 450 } 451 452 static const MemoryRegionOps taihu_cpld_ops = { 453 .read = taihu_cpld_read, 454 .write = taihu_cpld_write, 455 .impl = { 456 .min_access_size = 1, 457 .max_access_size = 1, 458 }, 459 .endianness = DEVICE_NATIVE_ENDIAN, 460 }; 461 462 static void taihu_cpld_reset (void *opaque) 463 { 464 taihu_cpld_t *cpld; 465 466 cpld = opaque; 467 cpld->reg0 = 0x01; 468 cpld->reg1 = 0x80; 469 } 470 471 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 472 { 473 taihu_cpld_t *cpld; 474 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 475 476 cpld = g_malloc0(sizeof(taihu_cpld_t)); 477 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 478 memory_region_add_subregion(sysmem, base, cpld_memory); 479 qemu_register_reset(&taihu_cpld_reset, cpld); 480 } 481 482 static void taihu_405ep_init(MachineState *machine) 483 { 484 ram_addr_t ram_size = machine->ram_size; 485 const char *kernel_filename = machine->kernel_filename; 486 const char *initrd_filename = machine->initrd_filename; 487 char *filename; 488 qemu_irq *pic; 489 MemoryRegion *sysmem = get_system_memory(); 490 MemoryRegion *bios; 491 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 492 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 493 hwaddr ram_bases[2], ram_sizes[2]; 494 long bios_size; 495 target_ulong kernel_base, initrd_base; 496 long kernel_size, initrd_size; 497 int linux_boot; 498 int fl_idx, fl_sectors; 499 DriveInfo *dinfo; 500 501 /* RAM is soldered to the board so the size cannot be changed */ 502 ram_size = 0x08000000; 503 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 504 ram_size); 505 506 ram_bases[0] = 0; 507 ram_sizes[0] = 0x04000000; 508 memory_region_init_alias(&ram_memories[0], NULL, 509 "taihu_405ep.ram-0", ram, ram_bases[0], 510 ram_sizes[0]); 511 ram_bases[1] = 0x04000000; 512 ram_sizes[1] = 0x04000000; 513 memory_region_init_alias(&ram_memories[1], NULL, 514 "taihu_405ep.ram-1", ram, ram_bases[1], 515 ram_sizes[1]); 516 #ifdef DEBUG_BOARD_INIT 517 printf("%s: register cpu\n", __func__); 518 #endif 519 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 520 33333333, &pic, kernel_filename == NULL ? 0 : 1); 521 /* allocate and load BIOS */ 522 #ifdef DEBUG_BOARD_INIT 523 printf("%s: register BIOS\n", __func__); 524 #endif 525 fl_idx = 0; 526 #if defined(USE_FLASH_BIOS) 527 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 528 if (dinfo) { 529 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 530 531 bios_size = blk_getlength(blk); 532 /* XXX: should check that size is 2MB */ 533 // bios_size = 2 * 1024 * 1024; 534 fl_sectors = (bios_size + 65535) >> 16; 535 #ifdef DEBUG_BOARD_INIT 536 printf("Register parallel flash %d size %lx" 537 " at addr %lx '%s' %d\n", 538 fl_idx, bios_size, -bios_size, 539 blk_name(blk), fl_sectors); 540 #endif 541 pflash_cfi02_register((uint32_t)(-bios_size), 542 NULL, "taihu_405ep.bios", bios_size, 543 blk, 65536, fl_sectors, 1, 544 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 545 1); 546 fl_idx++; 547 } else 548 #endif 549 { 550 #ifdef DEBUG_BOARD_INIT 551 printf("Load BIOS from file\n"); 552 #endif 553 if (bios_name == NULL) 554 bios_name = BIOS_FILENAME; 555 bios = g_new(MemoryRegion, 1); 556 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 557 &error_fatal); 558 vmstate_register_ram_global(bios); 559 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 560 if (filename) { 561 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 562 g_free(filename); 563 if (bios_size < 0 || bios_size > BIOS_SIZE) { 564 error_report("Could not load PowerPC BIOS '%s'", bios_name); 565 exit(1); 566 } 567 bios_size = (bios_size + 0xfff) & ~0xfff; 568 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 569 } else if (!qtest_enabled()) { 570 error_report("Could not load PowerPC BIOS '%s'", bios_name); 571 exit(1); 572 } 573 memory_region_set_readonly(bios, true); 574 } 575 /* Register Linux flash */ 576 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 577 if (dinfo) { 578 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 579 580 bios_size = blk_getlength(blk); 581 /* XXX: should check that size is 32MB */ 582 bios_size = 32 * 1024 * 1024; 583 fl_sectors = (bios_size + 65535) >> 16; 584 #ifdef DEBUG_BOARD_INIT 585 printf("Register parallel flash %d size %lx" 586 " at addr " TARGET_FMT_lx " '%s'\n", 587 fl_idx, bios_size, (target_ulong)0xfc000000, 588 blk_name(blk)); 589 #endif 590 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 591 blk, 65536, fl_sectors, 1, 592 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 593 1); 594 fl_idx++; 595 } 596 /* Register CLPD & LCD display */ 597 #ifdef DEBUG_BOARD_INIT 598 printf("%s: register CPLD\n", __func__); 599 #endif 600 taihu_cpld_init(sysmem, 0x50100000); 601 /* Load kernel */ 602 linux_boot = (kernel_filename != NULL); 603 if (linux_boot) { 604 #ifdef DEBUG_BOARD_INIT 605 printf("%s: load kernel\n", __func__); 606 #endif 607 kernel_base = KERNEL_LOAD_ADDR; 608 /* now we can load the kernel */ 609 kernel_size = load_image_targphys(kernel_filename, kernel_base, 610 ram_size - kernel_base); 611 if (kernel_size < 0) { 612 fprintf(stderr, "qemu: could not load kernel '%s'\n", 613 kernel_filename); 614 exit(1); 615 } 616 /* load initrd */ 617 if (initrd_filename) { 618 initrd_base = INITRD_LOAD_ADDR; 619 initrd_size = load_image_targphys(initrd_filename, initrd_base, 620 ram_size - initrd_base); 621 if (initrd_size < 0) { 622 fprintf(stderr, 623 "qemu: could not load initial ram disk '%s'\n", 624 initrd_filename); 625 exit(1); 626 } 627 } else { 628 initrd_base = 0; 629 initrd_size = 0; 630 } 631 } else { 632 kernel_base = 0; 633 kernel_size = 0; 634 initrd_base = 0; 635 initrd_size = 0; 636 } 637 #ifdef DEBUG_BOARD_INIT 638 printf("%s: Done\n", __func__); 639 #endif 640 } 641 642 static void taihu_class_init(ObjectClass *oc, void *data) 643 { 644 MachineClass *mc = MACHINE_CLASS(oc); 645 646 mc->desc = "taihu"; 647 mc->init = taihu_405ep_init; 648 } 649 650 static const TypeInfo taihu_type = { 651 .name = MACHINE_TYPE_NAME("taihu"), 652 .parent = TYPE_MACHINE, 653 .class_init = taihu_class_init, 654 }; 655 656 static void ppc405_machine_init(void) 657 { 658 type_register_static(&ref405ep_type); 659 type_register_static(&taihu_type); 660 } 661 662 type_init(ppc405_machine_init) 663