1 /* 2 * QEMU PowerPC 405 evaluation boards emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "ppc405.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/qtest.h" 31 #include "sysemu/block-backend.h" 32 #include "hw/boards.h" 33 #include "qemu/log.h" 34 #include "qemu/error-report.h" 35 #include "hw/loader.h" 36 #include "sysemu/block-backend.h" 37 #include "sysemu/blockdev.h" 38 #include "exec/address-spaces.h" 39 40 #define BIOS_FILENAME "ppc405_rom.bin" 41 #define BIOS_SIZE (2048 * 1024) 42 43 #define KERNEL_LOAD_ADDR 0x00000000 44 #define INITRD_LOAD_ADDR 0x01800000 45 46 #define USE_FLASH_BIOS 47 48 //#define DEBUG_BOARD_INIT 49 50 /*****************************************************************************/ 51 /* PPC405EP reference board (IBM) */ 52 /* Standalone board with: 53 * - PowerPC 405EP CPU 54 * - SDRAM (0x00000000) 55 * - Flash (0xFFF80000) 56 * - SRAM (0xFFF00000) 57 * - NVRAM (0xF0000000) 58 * - FPGA (0xF0300000) 59 */ 60 typedef struct ref405ep_fpga_t ref405ep_fpga_t; 61 struct ref405ep_fpga_t { 62 uint8_t reg0; 63 uint8_t reg1; 64 }; 65 66 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 67 { 68 ref405ep_fpga_t *fpga; 69 uint32_t ret; 70 71 fpga = opaque; 72 switch (addr) { 73 case 0x0: 74 ret = fpga->reg0; 75 break; 76 case 0x1: 77 ret = fpga->reg1; 78 break; 79 default: 80 ret = 0; 81 break; 82 } 83 84 return ret; 85 } 86 87 static void ref405ep_fpga_writeb (void *opaque, 88 hwaddr addr, uint32_t value) 89 { 90 ref405ep_fpga_t *fpga; 91 92 fpga = opaque; 93 switch (addr) { 94 case 0x0: 95 /* Read only */ 96 break; 97 case 0x1: 98 fpga->reg1 = value; 99 break; 100 default: 101 break; 102 } 103 } 104 105 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) 106 { 107 uint32_t ret; 108 109 ret = ref405ep_fpga_readb(opaque, addr) << 8; 110 ret |= ref405ep_fpga_readb(opaque, addr + 1); 111 112 return ret; 113 } 114 115 static void ref405ep_fpga_writew (void *opaque, 116 hwaddr addr, uint32_t value) 117 { 118 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); 119 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); 120 } 121 122 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) 123 { 124 uint32_t ret; 125 126 ret = ref405ep_fpga_readb(opaque, addr) << 24; 127 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; 128 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; 129 ret |= ref405ep_fpga_readb(opaque, addr + 3); 130 131 return ret; 132 } 133 134 static void ref405ep_fpga_writel (void *opaque, 135 hwaddr addr, uint32_t value) 136 { 137 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); 138 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); 139 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); 140 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); 141 } 142 143 static const MemoryRegionOps ref405ep_fpga_ops = { 144 .old_mmio = { 145 .read = { 146 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, 147 }, 148 .write = { 149 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, 150 }, 151 }, 152 .endianness = DEVICE_NATIVE_ENDIAN, 153 }; 154 155 static void ref405ep_fpga_reset (void *opaque) 156 { 157 ref405ep_fpga_t *fpga; 158 159 fpga = opaque; 160 fpga->reg0 = 0x00; 161 fpga->reg1 = 0x0F; 162 } 163 164 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) 165 { 166 ref405ep_fpga_t *fpga; 167 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); 168 169 fpga = g_malloc0(sizeof(ref405ep_fpga_t)); 170 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, 171 "fpga", 0x00000100); 172 memory_region_add_subregion(sysmem, base, fpga_memory); 173 qemu_register_reset(&ref405ep_fpga_reset, fpga); 174 } 175 176 static void ref405ep_init(MachineState *machine) 177 { 178 ram_addr_t ram_size = machine->ram_size; 179 const char *kernel_filename = machine->kernel_filename; 180 const char *kernel_cmdline = machine->kernel_cmdline; 181 const char *initrd_filename = machine->initrd_filename; 182 char *filename; 183 ppc4xx_bd_info_t bd; 184 CPUPPCState *env; 185 qemu_irq *pic; 186 MemoryRegion *bios; 187 MemoryRegion *sram = g_new(MemoryRegion, 1); 188 ram_addr_t bdloc; 189 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 190 hwaddr ram_bases[2], ram_sizes[2]; 191 target_ulong sram_size; 192 long bios_size; 193 //int phy_addr = 0; 194 //static int phy_addr = 1; 195 target_ulong kernel_base, initrd_base; 196 long kernel_size, initrd_size; 197 int linux_boot; 198 int fl_idx, fl_sectors, len; 199 DriveInfo *dinfo; 200 MemoryRegion *sysmem = get_system_memory(); 201 202 /* XXX: fix this */ 203 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 204 0x08000000); 205 ram_bases[0] = 0; 206 ram_sizes[0] = 0x08000000; 207 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 208 ram_bases[1] = 0x00000000; 209 ram_sizes[1] = 0x00000000; 210 ram_size = 128 * 1024 * 1024; 211 #ifdef DEBUG_BOARD_INIT 212 printf("%s: register cpu\n", __func__); 213 #endif 214 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 215 33333333, &pic, kernel_filename == NULL ? 0 : 1); 216 /* allocate SRAM */ 217 sram_size = 512 * 1024; 218 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, 219 &error_fatal); 220 vmstate_register_ram_global(sram); 221 memory_region_add_subregion(sysmem, 0xFFF00000, sram); 222 /* allocate and load BIOS */ 223 #ifdef DEBUG_BOARD_INIT 224 printf("%s: register BIOS\n", __func__); 225 #endif 226 fl_idx = 0; 227 #ifdef USE_FLASH_BIOS 228 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 229 if (dinfo) { 230 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 231 232 bios_size = blk_getlength(blk); 233 fl_sectors = (bios_size + 65535) >> 16; 234 #ifdef DEBUG_BOARD_INIT 235 printf("Register parallel flash %d size %lx" 236 " at addr %lx '%s' %d\n", 237 fl_idx, bios_size, -bios_size, 238 blk_name(blk), fl_sectors); 239 #endif 240 pflash_cfi02_register((uint32_t)(-bios_size), 241 NULL, "ef405ep.bios", bios_size, 242 blk, 65536, fl_sectors, 1, 243 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 244 1); 245 fl_idx++; 246 } else 247 #endif 248 { 249 #ifdef DEBUG_BOARD_INIT 250 printf("Load BIOS from file\n"); 251 #endif 252 bios = g_new(MemoryRegion, 1); 253 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, 254 &error_fatal); 255 vmstate_register_ram_global(bios); 256 257 if (bios_name == NULL) 258 bios_name = BIOS_FILENAME; 259 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 260 if (filename) { 261 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 262 g_free(filename); 263 if (bios_size < 0 || bios_size > BIOS_SIZE) { 264 error_report("Could not load PowerPC BIOS '%s'", bios_name); 265 exit(1); 266 } 267 bios_size = (bios_size + 0xfff) & ~0xfff; 268 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 269 } else if (!qtest_enabled() || kernel_filename != NULL) { 270 error_report("Could not load PowerPC BIOS '%s'", bios_name); 271 exit(1); 272 } else { 273 /* Avoid an uninitialized variable warning */ 274 bios_size = -1; 275 } 276 memory_region_set_readonly(bios, true); 277 } 278 /* Register FPGA */ 279 #ifdef DEBUG_BOARD_INIT 280 printf("%s: register FPGA\n", __func__); 281 #endif 282 ref405ep_fpga_init(sysmem, 0xF0300000); 283 /* Register NVRAM */ 284 #ifdef DEBUG_BOARD_INIT 285 printf("%s: register NVRAM\n", __func__); 286 #endif 287 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8); 288 /* Load kernel */ 289 linux_boot = (kernel_filename != NULL); 290 if (linux_boot) { 291 #ifdef DEBUG_BOARD_INIT 292 printf("%s: load kernel\n", __func__); 293 #endif 294 memset(&bd, 0, sizeof(bd)); 295 bd.bi_memstart = 0x00000000; 296 bd.bi_memsize = ram_size; 297 bd.bi_flashstart = -bios_size; 298 bd.bi_flashsize = -bios_size; 299 bd.bi_flashoffset = 0; 300 bd.bi_sramstart = 0xFFF00000; 301 bd.bi_sramsize = sram_size; 302 bd.bi_bootflags = 0; 303 bd.bi_intfreq = 133333333; 304 bd.bi_busfreq = 33333333; 305 bd.bi_baudrate = 115200; 306 bd.bi_s_version[0] = 'Q'; 307 bd.bi_s_version[1] = 'M'; 308 bd.bi_s_version[2] = 'U'; 309 bd.bi_s_version[3] = '\0'; 310 bd.bi_r_version[0] = 'Q'; 311 bd.bi_r_version[1] = 'E'; 312 bd.bi_r_version[2] = 'M'; 313 bd.bi_r_version[3] = 'U'; 314 bd.bi_r_version[4] = '\0'; 315 bd.bi_procfreq = 133333333; 316 bd.bi_plb_busfreq = 33333333; 317 bd.bi_pci_busfreq = 33333333; 318 bd.bi_opbfreq = 33333333; 319 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); 320 env->gpr[3] = bdloc; 321 kernel_base = KERNEL_LOAD_ADDR; 322 /* now we can load the kernel */ 323 kernel_size = load_image_targphys(kernel_filename, kernel_base, 324 ram_size - kernel_base); 325 if (kernel_size < 0) { 326 fprintf(stderr, "qemu: could not load kernel '%s'\n", 327 kernel_filename); 328 exit(1); 329 } 330 printf("Load kernel size %ld at " TARGET_FMT_lx, 331 kernel_size, kernel_base); 332 /* load initrd */ 333 if (initrd_filename) { 334 initrd_base = INITRD_LOAD_ADDR; 335 initrd_size = load_image_targphys(initrd_filename, initrd_base, 336 ram_size - initrd_base); 337 if (initrd_size < 0) { 338 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 339 initrd_filename); 340 exit(1); 341 } 342 } else { 343 initrd_base = 0; 344 initrd_size = 0; 345 } 346 env->gpr[4] = initrd_base; 347 env->gpr[5] = initrd_size; 348 if (kernel_cmdline != NULL) { 349 len = strlen(kernel_cmdline); 350 bdloc -= ((len + 255) & ~255); 351 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); 352 env->gpr[6] = bdloc; 353 env->gpr[7] = bdloc + len; 354 } else { 355 env->gpr[6] = 0; 356 env->gpr[7] = 0; 357 } 358 env->nip = KERNEL_LOAD_ADDR; 359 } else { 360 kernel_base = 0; 361 kernel_size = 0; 362 initrd_base = 0; 363 initrd_size = 0; 364 bdloc = 0; 365 } 366 #ifdef DEBUG_BOARD_INIT 367 printf("bdloc " RAM_ADDR_FMT "\n", bdloc); 368 printf("%s: Done\n", __func__); 369 #endif 370 } 371 372 static void ref405ep_class_init(ObjectClass *oc, void *data) 373 { 374 MachineClass *mc = MACHINE_CLASS(oc); 375 376 mc->desc = "ref405ep"; 377 mc->init = ref405ep_init; 378 } 379 380 static const TypeInfo ref405ep_type = { 381 .name = MACHINE_TYPE_NAME("ref405ep"), 382 .parent = TYPE_MACHINE, 383 .class_init = ref405ep_class_init, 384 }; 385 386 /*****************************************************************************/ 387 /* AMCC Taihu evaluation board */ 388 /* - PowerPC 405EP processor 389 * - SDRAM 128 MB at 0x00000000 390 * - Boot flash 2 MB at 0xFFE00000 391 * - Application flash 32 MB at 0xFC000000 392 * - 2 serial ports 393 * - 2 ethernet PHY 394 * - 1 USB 1.1 device 0x50000000 395 * - 1 LCD display 0x50100000 396 * - 1 CPLD 0x50100000 397 * - 1 I2C EEPROM 398 * - 1 I2C thermal sensor 399 * - a set of LEDs 400 * - bit-bang SPI port using GPIOs 401 * - 1 EBC interface connector 0 0x50200000 402 * - 1 cardbus controller + expansion slot. 403 * - 1 PCI expansion slot. 404 */ 405 typedef struct taihu_cpld_t taihu_cpld_t; 406 struct taihu_cpld_t { 407 uint8_t reg0; 408 uint8_t reg1; 409 }; 410 411 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size) 412 { 413 taihu_cpld_t *cpld; 414 uint32_t ret; 415 416 cpld = opaque; 417 switch (addr) { 418 case 0x0: 419 ret = cpld->reg0; 420 break; 421 case 0x1: 422 ret = cpld->reg1; 423 break; 424 default: 425 ret = 0; 426 break; 427 } 428 429 return ret; 430 } 431 432 static void taihu_cpld_write(void *opaque, hwaddr addr, 433 uint64_t value, unsigned size) 434 { 435 taihu_cpld_t *cpld; 436 437 cpld = opaque; 438 switch (addr) { 439 case 0x0: 440 /* Read only */ 441 break; 442 case 0x1: 443 cpld->reg1 = value; 444 break; 445 default: 446 break; 447 } 448 } 449 450 static const MemoryRegionOps taihu_cpld_ops = { 451 .read = taihu_cpld_read, 452 .write = taihu_cpld_write, 453 .impl = { 454 .min_access_size = 1, 455 .max_access_size = 1, 456 }, 457 .endianness = DEVICE_NATIVE_ENDIAN, 458 }; 459 460 static void taihu_cpld_reset (void *opaque) 461 { 462 taihu_cpld_t *cpld; 463 464 cpld = opaque; 465 cpld->reg0 = 0x01; 466 cpld->reg1 = 0x80; 467 } 468 469 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) 470 { 471 taihu_cpld_t *cpld; 472 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); 473 474 cpld = g_malloc0(sizeof(taihu_cpld_t)); 475 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100); 476 memory_region_add_subregion(sysmem, base, cpld_memory); 477 qemu_register_reset(&taihu_cpld_reset, cpld); 478 } 479 480 static void taihu_405ep_init(MachineState *machine) 481 { 482 ram_addr_t ram_size = machine->ram_size; 483 const char *kernel_filename = machine->kernel_filename; 484 const char *initrd_filename = machine->initrd_filename; 485 char *filename; 486 qemu_irq *pic; 487 MemoryRegion *sysmem = get_system_memory(); 488 MemoryRegion *bios; 489 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); 490 MemoryRegion *ram = g_malloc0(sizeof(*ram)); 491 hwaddr ram_bases[2], ram_sizes[2]; 492 long bios_size; 493 target_ulong kernel_base, initrd_base; 494 long kernel_size, initrd_size; 495 int linux_boot; 496 int fl_idx, fl_sectors; 497 DriveInfo *dinfo; 498 499 /* RAM is soldered to the board so the size cannot be changed */ 500 ram_size = 0x08000000; 501 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 502 ram_size); 503 504 ram_bases[0] = 0; 505 ram_sizes[0] = 0x04000000; 506 memory_region_init_alias(&ram_memories[0], NULL, 507 "taihu_405ep.ram-0", ram, ram_bases[0], 508 ram_sizes[0]); 509 ram_bases[1] = 0x04000000; 510 ram_sizes[1] = 0x04000000; 511 memory_region_init_alias(&ram_memories[1], NULL, 512 "taihu_405ep.ram-1", ram, ram_bases[1], 513 ram_sizes[1]); 514 #ifdef DEBUG_BOARD_INIT 515 printf("%s: register cpu\n", __func__); 516 #endif 517 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 518 33333333, &pic, kernel_filename == NULL ? 0 : 1); 519 /* allocate and load BIOS */ 520 #ifdef DEBUG_BOARD_INIT 521 printf("%s: register BIOS\n", __func__); 522 #endif 523 fl_idx = 0; 524 #if defined(USE_FLASH_BIOS) 525 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 526 if (dinfo) { 527 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 528 529 bios_size = blk_getlength(blk); 530 /* XXX: should check that size is 2MB */ 531 // bios_size = 2 * 1024 * 1024; 532 fl_sectors = (bios_size + 65535) >> 16; 533 #ifdef DEBUG_BOARD_INIT 534 printf("Register parallel flash %d size %lx" 535 " at addr %lx '%s' %d\n", 536 fl_idx, bios_size, -bios_size, 537 blk_name(blk), fl_sectors); 538 #endif 539 pflash_cfi02_register((uint32_t)(-bios_size), 540 NULL, "taihu_405ep.bios", bios_size, 541 blk, 65536, fl_sectors, 1, 542 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 543 1); 544 fl_idx++; 545 } else 546 #endif 547 { 548 #ifdef DEBUG_BOARD_INIT 549 printf("Load BIOS from file\n"); 550 #endif 551 if (bios_name == NULL) 552 bios_name = BIOS_FILENAME; 553 bios = g_new(MemoryRegion, 1); 554 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, 555 &error_fatal); 556 vmstate_register_ram_global(bios); 557 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 558 if (filename) { 559 bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); 560 g_free(filename); 561 if (bios_size < 0 || bios_size > BIOS_SIZE) { 562 error_report("Could not load PowerPC BIOS '%s'", bios_name); 563 exit(1); 564 } 565 bios_size = (bios_size + 0xfff) & ~0xfff; 566 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); 567 } else if (!qtest_enabled()) { 568 error_report("Could not load PowerPC BIOS '%s'", bios_name); 569 exit(1); 570 } 571 memory_region_set_readonly(bios, true); 572 } 573 /* Register Linux flash */ 574 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 575 if (dinfo) { 576 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 577 578 bios_size = blk_getlength(blk); 579 /* XXX: should check that size is 32MB */ 580 bios_size = 32 * 1024 * 1024; 581 fl_sectors = (bios_size + 65535) >> 16; 582 #ifdef DEBUG_BOARD_INIT 583 printf("Register parallel flash %d size %lx" 584 " at addr " TARGET_FMT_lx " '%s'\n", 585 fl_idx, bios_size, (target_ulong)0xfc000000, 586 blk_name(blk)); 587 #endif 588 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, 589 blk, 65536, fl_sectors, 1, 590 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 591 1); 592 fl_idx++; 593 } 594 /* Register CLPD & LCD display */ 595 #ifdef DEBUG_BOARD_INIT 596 printf("%s: register CPLD\n", __func__); 597 #endif 598 taihu_cpld_init(sysmem, 0x50100000); 599 /* Load kernel */ 600 linux_boot = (kernel_filename != NULL); 601 if (linux_boot) { 602 #ifdef DEBUG_BOARD_INIT 603 printf("%s: load kernel\n", __func__); 604 #endif 605 kernel_base = KERNEL_LOAD_ADDR; 606 /* now we can load the kernel */ 607 kernel_size = load_image_targphys(kernel_filename, kernel_base, 608 ram_size - kernel_base); 609 if (kernel_size < 0) { 610 fprintf(stderr, "qemu: could not load kernel '%s'\n", 611 kernel_filename); 612 exit(1); 613 } 614 /* load initrd */ 615 if (initrd_filename) { 616 initrd_base = INITRD_LOAD_ADDR; 617 initrd_size = load_image_targphys(initrd_filename, initrd_base, 618 ram_size - initrd_base); 619 if (initrd_size < 0) { 620 fprintf(stderr, 621 "qemu: could not load initial ram disk '%s'\n", 622 initrd_filename); 623 exit(1); 624 } 625 } else { 626 initrd_base = 0; 627 initrd_size = 0; 628 } 629 } else { 630 kernel_base = 0; 631 kernel_size = 0; 632 initrd_base = 0; 633 initrd_size = 0; 634 } 635 #ifdef DEBUG_BOARD_INIT 636 printf("%s: Done\n", __func__); 637 #endif 638 } 639 640 static void taihu_class_init(ObjectClass *oc, void *data) 641 { 642 MachineClass *mc = MACHINE_CLASS(oc); 643 644 mc->desc = "taihu"; 645 mc->init = taihu_405ep_init; 646 } 647 648 static const TypeInfo taihu_type = { 649 .name = MACHINE_TYPE_NAME("taihu"), 650 .parent = TYPE_MACHINE, 651 .class_init = taihu_class_init, 652 }; 653 654 static void ppc405_machine_init(void) 655 { 656 type_register_static(&ref405ep_type); 657 type_register_static(&taihu_type); 658 } 659 660 machine_init(ppc405_machine_init) 661