1 /* 2 * QEMU PowerPC 405 shared definitions 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC405_H 26 #define PPC405_H 27 28 #include "hw/ppc/ppc4xx.h" 29 30 #define PPC405EP_SDRAM_BASE 0x00000000 31 #define PPC405EP_NVRAM_BASE 0xF0000000 32 #define PPC405EP_FPGA_BASE 0xF0300000 33 #define PPC405EP_SRAM_BASE 0xFFF00000 34 #define PPC405EP_SRAM_SIZE (512 * KiB) 35 #define PPC405EP_FLASH_BASE 0xFFF80000 36 37 /* Bootinfo as set-up by u-boot */ 38 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; 39 struct ppc4xx_bd_info_t { 40 uint32_t bi_memstart; 41 uint32_t bi_memsize; 42 uint32_t bi_flashstart; 43 uint32_t bi_flashsize; 44 uint32_t bi_flashoffset; /* 0x10 */ 45 uint32_t bi_sramstart; 46 uint32_t bi_sramsize; 47 uint32_t bi_bootflags; 48 uint32_t bi_ipaddr; /* 0x20 */ 49 uint8_t bi_enetaddr[6]; 50 uint16_t bi_ethspeed; 51 uint32_t bi_intfreq; 52 uint32_t bi_busfreq; /* 0x30 */ 53 uint32_t bi_baudrate; 54 uint8_t bi_s_version[4]; 55 uint8_t bi_r_version[32]; 56 uint32_t bi_procfreq; 57 uint32_t bi_plb_busfreq; 58 uint32_t bi_pci_busfreq; 59 uint8_t bi_pci_enetaddr[6]; 60 uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ 61 uint32_t bi_opbfreq; 62 uint32_t bi_iic_fast[2]; 63 }; 64 65 /* PowerPC 405 core */ 66 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); 67 68 void ppc4xx_plb_init(CPUPPCState *env); 69 void ppc405_ebc_init(CPUPPCState *env); 70 71 PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, 72 MemoryRegion ram_memories[2], 73 hwaddr ram_bases[2], 74 hwaddr ram_sizes[2], 75 uint32_t sysclk, DeviceState **uicdev, 76 int do_init); 77 78 #endif /* PPC405_H */ 79