1 /* 2 * QEMU generic PowerPC hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/ppc/ppc_e500.h" 27 #include "qemu/timer.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/cpus.h" 30 #include "hw/timer/m48t59.h" 31 #include "qemu/log.h" 32 #include "qemu/error-report.h" 33 #include "hw/loader.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "trace.h" 37 38 //#define PPC_DEBUG_IRQ 39 //#define PPC_DEBUG_TB 40 41 #ifdef PPC_DEBUG_IRQ 42 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 43 #else 44 # define LOG_IRQ(...) do { } while (0) 45 #endif 46 47 48 #ifdef PPC_DEBUG_TB 49 # define LOG_TB(...) qemu_log(__VA_ARGS__) 50 #else 51 # define LOG_TB(...) do { } while (0) 52 #endif 53 54 #define NSEC_PER_SEC 1000000000LL 55 56 static void cpu_ppc_tb_stop (CPUPPCState *env); 57 static void cpu_ppc_tb_start (CPUPPCState *env); 58 59 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 60 { 61 CPUState *cs = CPU(cpu); 62 CPUPPCState *env = &cpu->env; 63 unsigned int old_pending = env->pending_interrupts; 64 65 if (level) { 66 env->pending_interrupts |= 1 << n_IRQ; 67 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 68 } else { 69 env->pending_interrupts &= ~(1 << n_IRQ); 70 if (env->pending_interrupts == 0) { 71 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 72 } 73 } 74 75 if (old_pending != env->pending_interrupts) { 76 #ifdef CONFIG_KVM 77 kvmppc_set_interrupt(cpu, n_IRQ, level); 78 #endif 79 } 80 81 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 82 "req %08x\n", __func__, env, n_IRQ, level, 83 env->pending_interrupts, CPU(cpu)->interrupt_request); 84 } 85 86 /* PowerPC 6xx / 7xx internal IRQ controller */ 87 static void ppc6xx_set_irq(void *opaque, int pin, int level) 88 { 89 PowerPCCPU *cpu = opaque; 90 CPUPPCState *env = &cpu->env; 91 int cur_level; 92 93 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 94 env, pin, level); 95 cur_level = (env->irq_input_state >> pin) & 1; 96 /* Don't generate spurious events */ 97 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 98 CPUState *cs = CPU(cpu); 99 100 switch (pin) { 101 case PPC6xx_INPUT_TBEN: 102 /* Level sensitive - active high */ 103 LOG_IRQ("%s: %s the time base\n", 104 __func__, level ? "start" : "stop"); 105 if (level) { 106 cpu_ppc_tb_start(env); 107 } else { 108 cpu_ppc_tb_stop(env); 109 } 110 case PPC6xx_INPUT_INT: 111 /* Level sensitive - active high */ 112 LOG_IRQ("%s: set the external IRQ state to %d\n", 113 __func__, level); 114 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 115 break; 116 case PPC6xx_INPUT_SMI: 117 /* Level sensitive - active high */ 118 LOG_IRQ("%s: set the SMI IRQ state to %d\n", 119 __func__, level); 120 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 121 break; 122 case PPC6xx_INPUT_MCP: 123 /* Negative edge sensitive */ 124 /* XXX: TODO: actual reaction may depends on HID0 status 125 * 603/604/740/750: check HID0[EMCP] 126 */ 127 if (cur_level == 1 && level == 0) { 128 LOG_IRQ("%s: raise machine check state\n", 129 __func__); 130 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 131 } 132 break; 133 case PPC6xx_INPUT_CKSTP_IN: 134 /* Level sensitive - active low */ 135 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 136 /* XXX: Note that the only way to restart the CPU is to reset it */ 137 if (level) { 138 LOG_IRQ("%s: stop the CPU\n", __func__); 139 cs->halted = 1; 140 } 141 break; 142 case PPC6xx_INPUT_HRESET: 143 /* Level sensitive - active low */ 144 if (level) { 145 LOG_IRQ("%s: reset the CPU\n", __func__); 146 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 147 } 148 break; 149 case PPC6xx_INPUT_SRESET: 150 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 151 __func__, level); 152 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 153 break; 154 default: 155 /* Unknown pin - do nothing */ 156 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 157 return; 158 } 159 if (level) 160 env->irq_input_state |= 1 << pin; 161 else 162 env->irq_input_state &= ~(1 << pin); 163 } 164 } 165 166 void ppc6xx_irq_init(CPUPPCState *env) 167 { 168 PowerPCCPU *cpu = ppc_env_get_cpu(env); 169 170 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 171 PPC6xx_INPUT_NB); 172 } 173 174 #if defined(TARGET_PPC64) 175 /* PowerPC 970 internal IRQ controller */ 176 static void ppc970_set_irq(void *opaque, int pin, int level) 177 { 178 PowerPCCPU *cpu = opaque; 179 CPUPPCState *env = &cpu->env; 180 int cur_level; 181 182 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 183 env, pin, level); 184 cur_level = (env->irq_input_state >> pin) & 1; 185 /* Don't generate spurious events */ 186 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 187 CPUState *cs = CPU(cpu); 188 189 switch (pin) { 190 case PPC970_INPUT_INT: 191 /* Level sensitive - active high */ 192 LOG_IRQ("%s: set the external IRQ state to %d\n", 193 __func__, level); 194 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 195 break; 196 case PPC970_INPUT_THINT: 197 /* Level sensitive - active high */ 198 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 199 level); 200 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 201 break; 202 case PPC970_INPUT_MCP: 203 /* Negative edge sensitive */ 204 /* XXX: TODO: actual reaction may depends on HID0 status 205 * 603/604/740/750: check HID0[EMCP] 206 */ 207 if (cur_level == 1 && level == 0) { 208 LOG_IRQ("%s: raise machine check state\n", 209 __func__); 210 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 211 } 212 break; 213 case PPC970_INPUT_CKSTP: 214 /* Level sensitive - active low */ 215 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 216 if (level) { 217 LOG_IRQ("%s: stop the CPU\n", __func__); 218 cs->halted = 1; 219 } else { 220 LOG_IRQ("%s: restart the CPU\n", __func__); 221 cs->halted = 0; 222 qemu_cpu_kick(cs); 223 } 224 break; 225 case PPC970_INPUT_HRESET: 226 /* Level sensitive - active low */ 227 if (level) { 228 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 229 } 230 break; 231 case PPC970_INPUT_SRESET: 232 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 233 __func__, level); 234 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 235 break; 236 case PPC970_INPUT_TBEN: 237 LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 238 level); 239 /* XXX: TODO */ 240 break; 241 default: 242 /* Unknown pin - do nothing */ 243 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 244 return; 245 } 246 if (level) 247 env->irq_input_state |= 1 << pin; 248 else 249 env->irq_input_state &= ~(1 << pin); 250 } 251 } 252 253 void ppc970_irq_init(CPUPPCState *env) 254 { 255 PowerPCCPU *cpu = ppc_env_get_cpu(env); 256 257 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 258 PPC970_INPUT_NB); 259 } 260 261 /* POWER7 internal IRQ controller */ 262 static void power7_set_irq(void *opaque, int pin, int level) 263 { 264 PowerPCCPU *cpu = opaque; 265 CPUPPCState *env = &cpu->env; 266 267 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 268 env, pin, level); 269 270 switch (pin) { 271 case POWER7_INPUT_INT: 272 /* Level sensitive - active high */ 273 LOG_IRQ("%s: set the external IRQ state to %d\n", 274 __func__, level); 275 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 276 break; 277 default: 278 /* Unknown pin - do nothing */ 279 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 280 return; 281 } 282 if (level) { 283 env->irq_input_state |= 1 << pin; 284 } else { 285 env->irq_input_state &= ~(1 << pin); 286 } 287 } 288 289 void ppcPOWER7_irq_init(CPUPPCState *env) 290 { 291 PowerPCCPU *cpu = ppc_env_get_cpu(env); 292 293 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 294 POWER7_INPUT_NB); 295 } 296 #endif /* defined(TARGET_PPC64) */ 297 298 /* PowerPC 40x internal IRQ controller */ 299 static void ppc40x_set_irq(void *opaque, int pin, int level) 300 { 301 PowerPCCPU *cpu = opaque; 302 CPUPPCState *env = &cpu->env; 303 int cur_level; 304 305 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 306 env, pin, level); 307 cur_level = (env->irq_input_state >> pin) & 1; 308 /* Don't generate spurious events */ 309 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 310 CPUState *cs = CPU(cpu); 311 312 switch (pin) { 313 case PPC40x_INPUT_RESET_SYS: 314 if (level) { 315 LOG_IRQ("%s: reset the PowerPC system\n", 316 __func__); 317 ppc40x_system_reset(cpu); 318 } 319 break; 320 case PPC40x_INPUT_RESET_CHIP: 321 if (level) { 322 LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 323 ppc40x_chip_reset(cpu); 324 } 325 break; 326 case PPC40x_INPUT_RESET_CORE: 327 /* XXX: TODO: update DBSR[MRR] */ 328 if (level) { 329 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 330 ppc40x_core_reset(cpu); 331 } 332 break; 333 case PPC40x_INPUT_CINT: 334 /* Level sensitive - active high */ 335 LOG_IRQ("%s: set the critical IRQ state to %d\n", 336 __func__, level); 337 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 338 break; 339 case PPC40x_INPUT_INT: 340 /* Level sensitive - active high */ 341 LOG_IRQ("%s: set the external IRQ state to %d\n", 342 __func__, level); 343 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 344 break; 345 case PPC40x_INPUT_HALT: 346 /* Level sensitive - active low */ 347 if (level) { 348 LOG_IRQ("%s: stop the CPU\n", __func__); 349 cs->halted = 1; 350 } else { 351 LOG_IRQ("%s: restart the CPU\n", __func__); 352 cs->halted = 0; 353 qemu_cpu_kick(cs); 354 } 355 break; 356 case PPC40x_INPUT_DEBUG: 357 /* Level sensitive - active high */ 358 LOG_IRQ("%s: set the debug pin state to %d\n", 359 __func__, level); 360 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 361 break; 362 default: 363 /* Unknown pin - do nothing */ 364 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 365 return; 366 } 367 if (level) 368 env->irq_input_state |= 1 << pin; 369 else 370 env->irq_input_state &= ~(1 << pin); 371 } 372 } 373 374 void ppc40x_irq_init(CPUPPCState *env) 375 { 376 PowerPCCPU *cpu = ppc_env_get_cpu(env); 377 378 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 379 cpu, PPC40x_INPUT_NB); 380 } 381 382 /* PowerPC E500 internal IRQ controller */ 383 static void ppce500_set_irq(void *opaque, int pin, int level) 384 { 385 PowerPCCPU *cpu = opaque; 386 CPUPPCState *env = &cpu->env; 387 int cur_level; 388 389 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 390 env, pin, level); 391 cur_level = (env->irq_input_state >> pin) & 1; 392 /* Don't generate spurious events */ 393 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 394 switch (pin) { 395 case PPCE500_INPUT_MCK: 396 if (level) { 397 LOG_IRQ("%s: reset the PowerPC system\n", 398 __func__); 399 qemu_system_reset_request(); 400 } 401 break; 402 case PPCE500_INPUT_RESET_CORE: 403 if (level) { 404 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 405 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 406 } 407 break; 408 case PPCE500_INPUT_CINT: 409 /* Level sensitive - active high */ 410 LOG_IRQ("%s: set the critical IRQ state to %d\n", 411 __func__, level); 412 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 413 break; 414 case PPCE500_INPUT_INT: 415 /* Level sensitive - active high */ 416 LOG_IRQ("%s: set the core IRQ state to %d\n", 417 __func__, level); 418 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 419 break; 420 case PPCE500_INPUT_DEBUG: 421 /* Level sensitive - active high */ 422 LOG_IRQ("%s: set the debug pin state to %d\n", 423 __func__, level); 424 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 425 break; 426 default: 427 /* Unknown pin - do nothing */ 428 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 429 return; 430 } 431 if (level) 432 env->irq_input_state |= 1 << pin; 433 else 434 env->irq_input_state &= ~(1 << pin); 435 } 436 } 437 438 void ppce500_irq_init(CPUPPCState *env) 439 { 440 PowerPCCPU *cpu = ppc_env_get_cpu(env); 441 442 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 443 cpu, PPCE500_INPUT_NB); 444 } 445 446 /* Enable or Disable the E500 EPR capability */ 447 void ppce500_set_mpic_proxy(bool enabled) 448 { 449 CPUState *cs; 450 451 CPU_FOREACH(cs) { 452 PowerPCCPU *cpu = POWERPC_CPU(cs); 453 454 cpu->env.mpic_proxy = enabled; 455 if (kvm_enabled()) { 456 kvmppc_set_mpic_proxy(cpu, enabled); 457 } 458 } 459 } 460 461 /*****************************************************************************/ 462 /* PowerPC time base and decrementer emulation */ 463 464 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 465 { 466 /* TB time in tb periods */ 467 return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; 468 } 469 470 uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 471 { 472 ppc_tb_t *tb_env = env->tb_env; 473 uint64_t tb; 474 475 if (kvm_enabled()) { 476 return env->spr[SPR_TBL]; 477 } 478 479 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 480 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 481 482 return tb; 483 } 484 485 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 486 { 487 ppc_tb_t *tb_env = env->tb_env; 488 uint64_t tb; 489 490 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 491 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 492 493 return tb >> 32; 494 } 495 496 uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 497 { 498 if (kvm_enabled()) { 499 return env->spr[SPR_TBU]; 500 } 501 502 return _cpu_ppc_load_tbu(env); 503 } 504 505 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 506 int64_t *tb_offsetp, uint64_t value) 507 { 508 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); 509 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 510 __func__, value, *tb_offsetp); 511 } 512 513 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 514 { 515 ppc_tb_t *tb_env = env->tb_env; 516 uint64_t tb; 517 518 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 519 tb &= 0xFFFFFFFF00000000ULL; 520 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 521 &tb_env->tb_offset, tb | (uint64_t)value); 522 } 523 524 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 525 { 526 ppc_tb_t *tb_env = env->tb_env; 527 uint64_t tb; 528 529 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 530 tb &= 0x00000000FFFFFFFFULL; 531 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 532 &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 533 } 534 535 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 536 { 537 _cpu_ppc_store_tbu(env, value); 538 } 539 540 uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 541 { 542 ppc_tb_t *tb_env = env->tb_env; 543 uint64_t tb; 544 545 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 546 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 547 548 return tb; 549 } 550 551 uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 552 { 553 ppc_tb_t *tb_env = env->tb_env; 554 uint64_t tb; 555 556 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 557 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 558 559 return tb >> 32; 560 } 561 562 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 563 { 564 ppc_tb_t *tb_env = env->tb_env; 565 uint64_t tb; 566 567 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 568 tb &= 0xFFFFFFFF00000000ULL; 569 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 570 &tb_env->atb_offset, tb | (uint64_t)value); 571 } 572 573 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 574 { 575 ppc_tb_t *tb_env = env->tb_env; 576 uint64_t tb; 577 578 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 579 tb &= 0x00000000FFFFFFFFULL; 580 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 581 &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 582 } 583 584 static void cpu_ppc_tb_stop (CPUPPCState *env) 585 { 586 ppc_tb_t *tb_env = env->tb_env; 587 uint64_t tb, atb, vmclk; 588 589 /* If the time base is already frozen, do nothing */ 590 if (tb_env->tb_freq != 0) { 591 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 592 /* Get the time base */ 593 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 594 /* Get the alternate time base */ 595 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 596 /* Store the time base value (ie compute the current offset) */ 597 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 598 /* Store the alternate time base value (compute the current offset) */ 599 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 600 /* Set the time base frequency to zero */ 601 tb_env->tb_freq = 0; 602 /* Now, the time bases are frozen to tb_offset / atb_offset value */ 603 } 604 } 605 606 static void cpu_ppc_tb_start (CPUPPCState *env) 607 { 608 ppc_tb_t *tb_env = env->tb_env; 609 uint64_t tb, atb, vmclk; 610 611 /* If the time base is not frozen, do nothing */ 612 if (tb_env->tb_freq == 0) { 613 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 614 /* Get the time base from tb_offset */ 615 tb = tb_env->tb_offset; 616 /* Get the alternate time base from atb_offset */ 617 atb = tb_env->atb_offset; 618 /* Restore the tb frequency from the decrementer frequency */ 619 tb_env->tb_freq = tb_env->decr_freq; 620 /* Store the time base value */ 621 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 622 /* Store the alternate time base value */ 623 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 624 } 625 } 626 627 bool ppc_decr_clear_on_delivery(CPUPPCState *env) 628 { 629 ppc_tb_t *tb_env = env->tb_env; 630 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 631 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 632 } 633 634 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 635 { 636 ppc_tb_t *tb_env = env->tb_env; 637 uint32_t decr; 638 int64_t diff; 639 640 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 641 if (diff >= 0) { 642 decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); 643 } else if (tb_env->flags & PPC_TIMER_BOOKE) { 644 decr = 0; 645 } else { 646 decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); 647 } 648 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); 649 650 return decr; 651 } 652 653 uint32_t cpu_ppc_load_decr (CPUPPCState *env) 654 { 655 ppc_tb_t *tb_env = env->tb_env; 656 657 if (kvm_enabled()) { 658 return env->spr[SPR_DECR]; 659 } 660 661 return _cpu_ppc_load_decr(env, tb_env->decr_next); 662 } 663 664 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env) 665 { 666 ppc_tb_t *tb_env = env->tb_env; 667 668 return _cpu_ppc_load_decr(env, tb_env->hdecr_next); 669 } 670 671 uint64_t cpu_ppc_load_purr (CPUPPCState *env) 672 { 673 ppc_tb_t *tb_env = env->tb_env; 674 uint64_t diff; 675 676 diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start; 677 678 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec()); 679 } 680 681 /* When decrementer expires, 682 * all we need to do is generate or queue a CPU exception 683 */ 684 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 685 { 686 /* Raise it */ 687 LOG_TB("raise decrementer exception\n"); 688 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 689 } 690 691 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 692 { 693 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 694 } 695 696 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 697 { 698 /* Raise it */ 699 LOG_TB("raise decrementer exception\n"); 700 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 701 } 702 703 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 704 { 705 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 706 } 707 708 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 709 QEMUTimer *timer, 710 void (*raise_excp)(void *), 711 void (*lower_excp)(PowerPCCPU *), 712 uint32_t decr, uint32_t value) 713 { 714 CPUPPCState *env = &cpu->env; 715 ppc_tb_t *tb_env = env->tb_env; 716 uint64_t now, next; 717 718 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, 719 decr, value); 720 721 if (kvm_enabled()) { 722 /* KVM handles decrementer exceptions, we don't need our own timer */ 723 return; 724 } 725 726 /* 727 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 728 * interrupt. 729 * 730 * If we get a really small DEC value, we can assume that by the time we 731 * handled it we should inject an interrupt already. 732 * 733 * On MSB level based DEC implementations the MSB always means the interrupt 734 * is pending, so raise it on those. 735 * 736 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 737 * an edge interrupt, so raise it here too. 738 */ 739 if ((value < 3) || 740 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & 0x80000000)) || 741 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & 0x80000000) 742 && !(decr & 0x80000000))) { 743 (*raise_excp)(cpu); 744 return; 745 } 746 747 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 748 if (!(value & 0x80000000) && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 749 (*lower_excp)(cpu); 750 } 751 752 /* Calculate the next timer event */ 753 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 754 next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); 755 *nextp = next; 756 757 /* Adjust timer */ 758 timer_mod(timer, next); 759 } 760 761 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr, 762 uint32_t value) 763 { 764 ppc_tb_t *tb_env = cpu->env.tb_env; 765 766 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 767 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 768 value); 769 } 770 771 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) 772 { 773 PowerPCCPU *cpu = ppc_env_get_cpu(env); 774 775 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value); 776 } 777 778 static void cpu_ppc_decr_cb(void *opaque) 779 { 780 PowerPCCPU *cpu = opaque; 781 782 cpu_ppc_decr_excp(cpu); 783 } 784 785 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr, 786 uint32_t value) 787 { 788 ppc_tb_t *tb_env = cpu->env.tb_env; 789 790 if (tb_env->hdecr_timer != NULL) { 791 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 792 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 793 hdecr, value); 794 } 795 } 796 797 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value) 798 { 799 PowerPCCPU *cpu = ppc_env_get_cpu(env); 800 801 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value); 802 } 803 804 static void cpu_ppc_hdecr_cb(void *opaque) 805 { 806 PowerPCCPU *cpu = opaque; 807 808 cpu_ppc_hdecr_excp(cpu); 809 } 810 811 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) 812 { 813 ppc_tb_t *tb_env = cpu->env.tb_env; 814 815 tb_env->purr_load = value; 816 tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 817 } 818 819 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 820 { 821 CPUPPCState *env = opaque; 822 PowerPCCPU *cpu = ppc_env_get_cpu(env); 823 ppc_tb_t *tb_env = env->tb_env; 824 825 tb_env->tb_freq = freq; 826 tb_env->decr_freq = freq; 827 /* There is a bug in Linux 2.4 kernels: 828 * if a decrementer exception is pending when it enables msr_ee at startup, 829 * it's not ready to handle it... 830 */ 831 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF); 832 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF); 833 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); 834 } 835 836 static void timebase_pre_save(void *opaque) 837 { 838 PPCTimebase *tb = opaque; 839 uint64_t ticks = cpu_get_real_ticks(); 840 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 841 842 if (!first_ppc_cpu->env.tb_env) { 843 error_report("No timebase object"); 844 return; 845 } 846 847 tb->time_of_the_day_ns = get_clock_realtime(); 848 /* 849 * tb_offset is only expected to be changed by migration so 850 * there is no need to update it from KVM here 851 */ 852 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 853 } 854 855 static int timebase_post_load(void *opaque, int version_id) 856 { 857 PPCTimebase *tb_remote = opaque; 858 CPUState *cpu; 859 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 860 int64_t tb_off_adj, tb_off, ns_diff; 861 int64_t migration_duration_ns, migration_duration_tb, guest_tb, host_ns; 862 unsigned long freq; 863 864 if (!first_ppc_cpu->env.tb_env) { 865 error_report("No timebase object"); 866 return -1; 867 } 868 869 freq = first_ppc_cpu->env.tb_env->tb_freq; 870 /* 871 * Calculate timebase on the destination side of migration. 872 * The destination timebase must be not less than the source timebase. 873 * We try to adjust timebase by downtime if host clocks are not 874 * too much out of sync (1 second for now). 875 */ 876 host_ns = get_clock_realtime(); 877 ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns); 878 migration_duration_ns = MIN(NSEC_PER_SEC, ns_diff); 879 migration_duration_tb = muldiv64(migration_duration_ns, freq, NSEC_PER_SEC); 880 guest_tb = tb_remote->guest_timebase + MIN(0, migration_duration_tb); 881 882 tb_off_adj = guest_tb - cpu_get_real_ticks(); 883 884 tb_off = first_ppc_cpu->env.tb_env->tb_offset; 885 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 886 (tb_off_adj - tb_off) / freq); 887 888 /* Set new offset to all CPUs */ 889 CPU_FOREACH(cpu) { 890 PowerPCCPU *pcpu = POWERPC_CPU(cpu); 891 pcpu->env.tb_env->tb_offset = tb_off_adj; 892 } 893 894 return 0; 895 } 896 897 const VMStateDescription vmstate_ppc_timebase = { 898 .name = "timebase", 899 .version_id = 1, 900 .minimum_version_id = 1, 901 .minimum_version_id_old = 1, 902 .pre_save = timebase_pre_save, 903 .post_load = timebase_post_load, 904 .fields = (VMStateField []) { 905 VMSTATE_UINT64(guest_timebase, PPCTimebase), 906 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 907 VMSTATE_END_OF_LIST() 908 }, 909 }; 910 911 /* Set up (once) timebase frequency (in Hz) */ 912 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 913 { 914 PowerPCCPU *cpu = ppc_env_get_cpu(env); 915 ppc_tb_t *tb_env; 916 917 tb_env = g_malloc0(sizeof(ppc_tb_t)); 918 env->tb_env = tb_env; 919 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 920 if (env->insns_flags & PPC_SEGMENT_64B) { 921 /* All Book3S 64bit CPUs implement level based DEC logic */ 922 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 923 } 924 /* Create new timer */ 925 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 926 if (0) { 927 /* XXX: find a suitable condition to enable the hypervisor decrementer 928 */ 929 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 930 cpu); 931 } else { 932 tb_env->hdecr_timer = NULL; 933 } 934 cpu_ppc_set_tb_clk(env, freq); 935 936 return &cpu_ppc_set_tb_clk; 937 } 938 939 /* Specific helpers for POWER & PowerPC 601 RTC */ 940 #if 0 941 static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env) 942 { 943 return cpu_ppc_tb_init(env, 7812500); 944 } 945 #endif 946 947 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 948 { 949 _cpu_ppc_store_tbu(env, value); 950 } 951 952 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 953 { 954 return _cpu_ppc_load_tbu(env); 955 } 956 957 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 958 { 959 cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 960 } 961 962 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 963 { 964 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 965 } 966 967 /*****************************************************************************/ 968 /* PowerPC 40x timers */ 969 970 /* PIT, FIT & WDT */ 971 typedef struct ppc40x_timer_t ppc40x_timer_t; 972 struct ppc40x_timer_t { 973 uint64_t pit_reload; /* PIT auto-reload value */ 974 uint64_t fit_next; /* Tick for next FIT interrupt */ 975 QEMUTimer *fit_timer; 976 uint64_t wdt_next; /* Tick for next WDT interrupt */ 977 QEMUTimer *wdt_timer; 978 979 /* 405 have the PIT, 440 have a DECR. */ 980 unsigned int decr_excp; 981 }; 982 983 /* Fixed interval timer */ 984 static void cpu_4xx_fit_cb (void *opaque) 985 { 986 PowerPCCPU *cpu; 987 CPUPPCState *env; 988 ppc_tb_t *tb_env; 989 ppc40x_timer_t *ppc40x_timer; 990 uint64_t now, next; 991 992 env = opaque; 993 cpu = ppc_env_get_cpu(env); 994 tb_env = env->tb_env; 995 ppc40x_timer = tb_env->opaque; 996 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 997 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 998 case 0: 999 next = 1 << 9; 1000 break; 1001 case 1: 1002 next = 1 << 13; 1003 break; 1004 case 2: 1005 next = 1 << 17; 1006 break; 1007 case 3: 1008 next = 1 << 21; 1009 break; 1010 default: 1011 /* Cannot occur, but makes gcc happy */ 1012 return; 1013 } 1014 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); 1015 if (next == now) 1016 next++; 1017 timer_mod(ppc40x_timer->fit_timer, next); 1018 env->spr[SPR_40x_TSR] |= 1 << 26; 1019 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 1020 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 1021 } 1022 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1023 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 1024 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1025 } 1026 1027 /* Programmable interval timer */ 1028 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 1029 { 1030 ppc40x_timer_t *ppc40x_timer; 1031 uint64_t now, next; 1032 1033 ppc40x_timer = tb_env->opaque; 1034 if (ppc40x_timer->pit_reload <= 1 || 1035 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 1036 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 1037 /* Stop PIT */ 1038 LOG_TB("%s: stop PIT\n", __func__); 1039 timer_del(tb_env->decr_timer); 1040 } else { 1041 LOG_TB("%s: start PIT %016" PRIx64 "\n", 1042 __func__, ppc40x_timer->pit_reload); 1043 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1044 next = now + muldiv64(ppc40x_timer->pit_reload, 1045 get_ticks_per_sec(), tb_env->decr_freq); 1046 if (is_excp) 1047 next += tb_env->decr_next - now; 1048 if (next == now) 1049 next++; 1050 timer_mod(tb_env->decr_timer, next); 1051 tb_env->decr_next = next; 1052 } 1053 } 1054 1055 static void cpu_4xx_pit_cb (void *opaque) 1056 { 1057 PowerPCCPU *cpu; 1058 CPUPPCState *env; 1059 ppc_tb_t *tb_env; 1060 ppc40x_timer_t *ppc40x_timer; 1061 1062 env = opaque; 1063 cpu = ppc_env_get_cpu(env); 1064 tb_env = env->tb_env; 1065 ppc40x_timer = tb_env->opaque; 1066 env->spr[SPR_40x_TSR] |= 1 << 27; 1067 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 1068 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 1069 } 1070 start_stop_pit(env, tb_env, 1); 1071 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 1072 "%016" PRIx64 "\n", __func__, 1073 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 1074 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 1075 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 1076 ppc40x_timer->pit_reload); 1077 } 1078 1079 /* Watchdog timer */ 1080 static void cpu_4xx_wdt_cb (void *opaque) 1081 { 1082 PowerPCCPU *cpu; 1083 CPUPPCState *env; 1084 ppc_tb_t *tb_env; 1085 ppc40x_timer_t *ppc40x_timer; 1086 uint64_t now, next; 1087 1088 env = opaque; 1089 cpu = ppc_env_get_cpu(env); 1090 tb_env = env->tb_env; 1091 ppc40x_timer = tb_env->opaque; 1092 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1093 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 1094 case 0: 1095 next = 1 << 17; 1096 break; 1097 case 1: 1098 next = 1 << 21; 1099 break; 1100 case 2: 1101 next = 1 << 25; 1102 break; 1103 case 3: 1104 next = 1 << 29; 1105 break; 1106 default: 1107 /* Cannot occur, but makes gcc happy */ 1108 return; 1109 } 1110 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); 1111 if (next == now) 1112 next++; 1113 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1114 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1115 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 1116 case 0x0: 1117 case 0x1: 1118 timer_mod(ppc40x_timer->wdt_timer, next); 1119 ppc40x_timer->wdt_next = next; 1120 env->spr[SPR_40x_TSR] |= 1U << 31; 1121 break; 1122 case 0x2: 1123 timer_mod(ppc40x_timer->wdt_timer, next); 1124 ppc40x_timer->wdt_next = next; 1125 env->spr[SPR_40x_TSR] |= 1 << 30; 1126 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 1127 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 1128 } 1129 break; 1130 case 0x3: 1131 env->spr[SPR_40x_TSR] &= ~0x30000000; 1132 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 1133 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 1134 case 0x0: 1135 /* No reset */ 1136 break; 1137 case 0x1: /* Core reset */ 1138 ppc40x_core_reset(cpu); 1139 break; 1140 case 0x2: /* Chip reset */ 1141 ppc40x_chip_reset(cpu); 1142 break; 1143 case 0x3: /* System reset */ 1144 ppc40x_system_reset(cpu); 1145 break; 1146 } 1147 } 1148 } 1149 1150 void store_40x_pit (CPUPPCState *env, target_ulong val) 1151 { 1152 ppc_tb_t *tb_env; 1153 ppc40x_timer_t *ppc40x_timer; 1154 1155 tb_env = env->tb_env; 1156 ppc40x_timer = tb_env->opaque; 1157 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 1158 ppc40x_timer->pit_reload = val; 1159 start_stop_pit(env, tb_env, 0); 1160 } 1161 1162 target_ulong load_40x_pit (CPUPPCState *env) 1163 { 1164 return cpu_ppc_load_decr(env); 1165 } 1166 1167 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 1168 { 1169 CPUPPCState *env = opaque; 1170 ppc_tb_t *tb_env = env->tb_env; 1171 1172 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 1173 freq); 1174 tb_env->tb_freq = freq; 1175 tb_env->decr_freq = freq; 1176 /* XXX: we should also update all timers */ 1177 } 1178 1179 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 1180 unsigned int decr_excp) 1181 { 1182 ppc_tb_t *tb_env; 1183 ppc40x_timer_t *ppc40x_timer; 1184 1185 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1186 env->tb_env = tb_env; 1187 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1188 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 1189 tb_env->tb_freq = freq; 1190 tb_env->decr_freq = freq; 1191 tb_env->opaque = ppc40x_timer; 1192 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 1193 if (ppc40x_timer != NULL) { 1194 /* We use decr timer for PIT */ 1195 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 1196 ppc40x_timer->fit_timer = 1197 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 1198 ppc40x_timer->wdt_timer = 1199 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 1200 ppc40x_timer->decr_excp = decr_excp; 1201 } 1202 1203 return &ppc_40x_set_tb_clk; 1204 } 1205 1206 /*****************************************************************************/ 1207 /* Embedded PowerPC Device Control Registers */ 1208 typedef struct ppc_dcrn_t ppc_dcrn_t; 1209 struct ppc_dcrn_t { 1210 dcr_read_cb dcr_read; 1211 dcr_write_cb dcr_write; 1212 void *opaque; 1213 }; 1214 1215 /* XXX: on 460, DCR addresses are 32 bits wide, 1216 * using DCRIPR to get the 22 upper bits of the DCR address 1217 */ 1218 #define DCRN_NB 1024 1219 struct ppc_dcr_t { 1220 ppc_dcrn_t dcrn[DCRN_NB]; 1221 int (*read_error)(int dcrn); 1222 int (*write_error)(int dcrn); 1223 }; 1224 1225 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1226 { 1227 ppc_dcrn_t *dcr; 1228 1229 if (dcrn < 0 || dcrn >= DCRN_NB) 1230 goto error; 1231 dcr = &dcr_env->dcrn[dcrn]; 1232 if (dcr->dcr_read == NULL) 1233 goto error; 1234 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 1235 1236 return 0; 1237 1238 error: 1239 if (dcr_env->read_error != NULL) 1240 return (*dcr_env->read_error)(dcrn); 1241 1242 return -1; 1243 } 1244 1245 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1246 { 1247 ppc_dcrn_t *dcr; 1248 1249 if (dcrn < 0 || dcrn >= DCRN_NB) 1250 goto error; 1251 dcr = &dcr_env->dcrn[dcrn]; 1252 if (dcr->dcr_write == NULL) 1253 goto error; 1254 (*dcr->dcr_write)(dcr->opaque, dcrn, val); 1255 1256 return 0; 1257 1258 error: 1259 if (dcr_env->write_error != NULL) 1260 return (*dcr_env->write_error)(dcrn); 1261 1262 return -1; 1263 } 1264 1265 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 1266 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 1267 { 1268 ppc_dcr_t *dcr_env; 1269 ppc_dcrn_t *dcr; 1270 1271 dcr_env = env->dcr_env; 1272 if (dcr_env == NULL) 1273 return -1; 1274 if (dcrn < 0 || dcrn >= DCRN_NB) 1275 return -1; 1276 dcr = &dcr_env->dcrn[dcrn]; 1277 if (dcr->opaque != NULL || 1278 dcr->dcr_read != NULL || 1279 dcr->dcr_write != NULL) 1280 return -1; 1281 dcr->opaque = opaque; 1282 dcr->dcr_read = dcr_read; 1283 dcr->dcr_write = dcr_write; 1284 1285 return 0; 1286 } 1287 1288 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 1289 int (*write_error)(int dcrn)) 1290 { 1291 ppc_dcr_t *dcr_env; 1292 1293 dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 1294 dcr_env->read_error = read_error; 1295 dcr_env->write_error = write_error; 1296 env->dcr_env = dcr_env; 1297 1298 return 0; 1299 } 1300 1301 /*****************************************************************************/ 1302 /* Debug port */ 1303 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 1304 { 1305 addr &= 0xF; 1306 switch (addr) { 1307 case 0: 1308 printf("%c", val); 1309 break; 1310 case 1: 1311 printf("\n"); 1312 fflush(stdout); 1313 break; 1314 case 2: 1315 printf("Set loglevel to %04" PRIx32 "\n", val); 1316 qemu_set_log(val | 0x100); 1317 break; 1318 } 1319 } 1320 1321 /*****************************************************************************/ 1322 /* NVRAM helpers */ 1323 static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) 1324 { 1325 return (*nvram->read_fn)(nvram->opaque, addr); 1326 } 1327 1328 static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) 1329 { 1330 (*nvram->write_fn)(nvram->opaque, addr, val); 1331 } 1332 1333 static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value) 1334 { 1335 nvram_write(nvram, addr, value); 1336 } 1337 1338 static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr) 1339 { 1340 return nvram_read(nvram, addr); 1341 } 1342 1343 static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value) 1344 { 1345 nvram_write(nvram, addr, value >> 8); 1346 nvram_write(nvram, addr + 1, value & 0xFF); 1347 } 1348 1349 static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr) 1350 { 1351 uint16_t tmp; 1352 1353 tmp = nvram_read(nvram, addr) << 8; 1354 tmp |= nvram_read(nvram, addr + 1); 1355 1356 return tmp; 1357 } 1358 1359 static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value) 1360 { 1361 nvram_write(nvram, addr, value >> 24); 1362 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 1363 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 1364 nvram_write(nvram, addr + 3, value & 0xFF); 1365 } 1366 1367 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) 1368 { 1369 uint32_t tmp; 1370 1371 tmp = nvram_read(nvram, addr) << 24; 1372 tmp |= nvram_read(nvram, addr + 1) << 16; 1373 tmp |= nvram_read(nvram, addr + 2) << 8; 1374 tmp |= nvram_read(nvram, addr + 3); 1375 1376 return tmp; 1377 } 1378 1379 static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str, 1380 uint32_t max) 1381 { 1382 int i; 1383 1384 for (i = 0; i < max && str[i] != '\0'; i++) { 1385 nvram_write(nvram, addr + i, str[i]); 1386 } 1387 nvram_write(nvram, addr + i, str[i]); 1388 nvram_write(nvram, addr + max - 1, '\0'); 1389 } 1390 1391 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) 1392 { 1393 int i; 1394 1395 memset(dst, 0, max); 1396 for (i = 0; i < max; i++) { 1397 dst[i] = NVRAM_get_byte(nvram, addr + i); 1398 if (dst[i] == '\0') 1399 break; 1400 } 1401 1402 return i; 1403 } 1404 1405 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 1406 { 1407 uint16_t tmp; 1408 uint16_t pd, pd1, pd2; 1409 1410 tmp = prev >> 8; 1411 pd = prev ^ value; 1412 pd1 = pd & 0x000F; 1413 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 1414 tmp ^= (pd1 << 3) | (pd1 << 8); 1415 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 1416 1417 return tmp; 1418 } 1419 1420 static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) 1421 { 1422 uint32_t i; 1423 uint16_t crc = 0xFFFF; 1424 int odd; 1425 1426 odd = count & 1; 1427 count &= ~1; 1428 for (i = 0; i != count; i++) { 1429 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 1430 } 1431 if (odd) { 1432 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 1433 } 1434 1435 return crc; 1436 } 1437 1438 #define CMDLINE_ADDR 0x017ff000 1439 1440 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, 1441 const char *arch, 1442 uint32_t RAM_size, int boot_device, 1443 uint32_t kernel_image, uint32_t kernel_size, 1444 const char *cmdline, 1445 uint32_t initrd_image, uint32_t initrd_size, 1446 uint32_t NVRAM_image, 1447 int width, int height, int depth) 1448 { 1449 uint16_t crc; 1450 1451 /* Set parameters for Open Hack'Ware BIOS */ 1452 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 1453 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 1454 NVRAM_set_word(nvram, 0x14, NVRAM_size); 1455 NVRAM_set_string(nvram, 0x20, arch, 16); 1456 NVRAM_set_lword(nvram, 0x30, RAM_size); 1457 NVRAM_set_byte(nvram, 0x34, boot_device); 1458 NVRAM_set_lword(nvram, 0x38, kernel_image); 1459 NVRAM_set_lword(nvram, 0x3C, kernel_size); 1460 if (cmdline) { 1461 /* XXX: put the cmdline in NVRAM too ? */ 1462 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline); 1463 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 1464 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 1465 } else { 1466 NVRAM_set_lword(nvram, 0x40, 0); 1467 NVRAM_set_lword(nvram, 0x44, 0); 1468 } 1469 NVRAM_set_lword(nvram, 0x48, initrd_image); 1470 NVRAM_set_lword(nvram, 0x4C, initrd_size); 1471 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 1472 1473 NVRAM_set_word(nvram, 0x54, width); 1474 NVRAM_set_word(nvram, 0x56, height); 1475 NVRAM_set_word(nvram, 0x58, depth); 1476 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 1477 NVRAM_set_word(nvram, 0xFC, crc); 1478 1479 return 0; 1480 } 1481 1482 /* CPU device-tree ID helpers */ 1483 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu) 1484 { 1485 return cpu->cpu_dt_id; 1486 } 1487 1488 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id) 1489 { 1490 CPUState *cs; 1491 1492 CPU_FOREACH(cs) { 1493 PowerPCCPU *cpu = POWERPC_CPU(cs); 1494 1495 if (cpu->cpu_dt_id == cpu_dt_id) { 1496 return cpu; 1497 } 1498 } 1499 1500 return NULL; 1501 } 1502