1 /* 2 * QEMU generic PowerPC hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "hw/irq.h" 28 #include "hw/ppc/ppc.h" 29 #include "hw/ppc/ppc_e500.h" 30 #include "qemu/timer.h" 31 #include "sysemu/cpus.h" 32 #include "qemu/log.h" 33 #include "qemu/main-loop.h" 34 #include "qemu/error-report.h" 35 #include "sysemu/kvm.h" 36 #include "sysemu/runstate.h" 37 #include "kvm_ppc.h" 38 #include "migration/vmstate.h" 39 #include "trace.h" 40 41 //#define PPC_DEBUG_IRQ 42 //#define PPC_DEBUG_TB 43 44 #ifdef PPC_DEBUG_IRQ 45 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 46 #else 47 # define LOG_IRQ(...) do { } while (0) 48 #endif 49 50 51 #ifdef PPC_DEBUG_TB 52 # define LOG_TB(...) qemu_log(__VA_ARGS__) 53 #else 54 # define LOG_TB(...) do { } while (0) 55 #endif 56 57 static void cpu_ppc_tb_stop (CPUPPCState *env); 58 static void cpu_ppc_tb_start (CPUPPCState *env); 59 60 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 61 { 62 CPUState *cs = CPU(cpu); 63 CPUPPCState *env = &cpu->env; 64 unsigned int old_pending; 65 bool locked = false; 66 67 /* We may already have the BQL if coming from the reset path */ 68 if (!qemu_mutex_iothread_locked()) { 69 locked = true; 70 qemu_mutex_lock_iothread(); 71 } 72 73 old_pending = env->pending_interrupts; 74 75 if (level) { 76 env->pending_interrupts |= 1 << n_IRQ; 77 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 78 } else { 79 env->pending_interrupts &= ~(1 << n_IRQ); 80 if (env->pending_interrupts == 0) { 81 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 82 } 83 } 84 85 if (old_pending != env->pending_interrupts) { 86 kvmppc_set_interrupt(cpu, n_IRQ, level); 87 } 88 89 90 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 91 "req %08x\n", __func__, env, n_IRQ, level, 92 env->pending_interrupts, CPU(cpu)->interrupt_request); 93 94 if (locked) { 95 qemu_mutex_unlock_iothread(); 96 } 97 } 98 99 /* PowerPC 6xx / 7xx internal IRQ controller */ 100 static void ppc6xx_set_irq(void *opaque, int pin, int level) 101 { 102 PowerPCCPU *cpu = opaque; 103 CPUPPCState *env = &cpu->env; 104 int cur_level; 105 106 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 107 env, pin, level); 108 cur_level = (env->irq_input_state >> pin) & 1; 109 /* Don't generate spurious events */ 110 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 111 CPUState *cs = CPU(cpu); 112 113 switch (pin) { 114 case PPC6xx_INPUT_TBEN: 115 /* Level sensitive - active high */ 116 LOG_IRQ("%s: %s the time base\n", 117 __func__, level ? "start" : "stop"); 118 if (level) { 119 cpu_ppc_tb_start(env); 120 } else { 121 cpu_ppc_tb_stop(env); 122 } 123 case PPC6xx_INPUT_INT: 124 /* Level sensitive - active high */ 125 LOG_IRQ("%s: set the external IRQ state to %d\n", 126 __func__, level); 127 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 128 break; 129 case PPC6xx_INPUT_SMI: 130 /* Level sensitive - active high */ 131 LOG_IRQ("%s: set the SMI IRQ state to %d\n", 132 __func__, level); 133 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 134 break; 135 case PPC6xx_INPUT_MCP: 136 /* Negative edge sensitive */ 137 /* XXX: TODO: actual reaction may depends on HID0 status 138 * 603/604/740/750: check HID0[EMCP] 139 */ 140 if (cur_level == 1 && level == 0) { 141 LOG_IRQ("%s: raise machine check state\n", 142 __func__); 143 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 144 } 145 break; 146 case PPC6xx_INPUT_CKSTP_IN: 147 /* Level sensitive - active low */ 148 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 149 /* XXX: Note that the only way to restart the CPU is to reset it */ 150 if (level) { 151 LOG_IRQ("%s: stop the CPU\n", __func__); 152 cs->halted = 1; 153 } 154 break; 155 case PPC6xx_INPUT_HRESET: 156 /* Level sensitive - active low */ 157 if (level) { 158 LOG_IRQ("%s: reset the CPU\n", __func__); 159 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 160 } 161 break; 162 case PPC6xx_INPUT_SRESET: 163 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 164 __func__, level); 165 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 166 break; 167 default: 168 /* Unknown pin - do nothing */ 169 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 170 return; 171 } 172 if (level) 173 env->irq_input_state |= 1 << pin; 174 else 175 env->irq_input_state &= ~(1 << pin); 176 } 177 } 178 179 void ppc6xx_irq_init(PowerPCCPU *cpu) 180 { 181 CPUPPCState *env = &cpu->env; 182 183 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 184 PPC6xx_INPUT_NB); 185 } 186 187 #if defined(TARGET_PPC64) 188 /* PowerPC 970 internal IRQ controller */ 189 static void ppc970_set_irq(void *opaque, int pin, int level) 190 { 191 PowerPCCPU *cpu = opaque; 192 CPUPPCState *env = &cpu->env; 193 int cur_level; 194 195 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 196 env, pin, level); 197 cur_level = (env->irq_input_state >> pin) & 1; 198 /* Don't generate spurious events */ 199 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 200 CPUState *cs = CPU(cpu); 201 202 switch (pin) { 203 case PPC970_INPUT_INT: 204 /* Level sensitive - active high */ 205 LOG_IRQ("%s: set the external IRQ state to %d\n", 206 __func__, level); 207 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 208 break; 209 case PPC970_INPUT_THINT: 210 /* Level sensitive - active high */ 211 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 212 level); 213 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 214 break; 215 case PPC970_INPUT_MCP: 216 /* Negative edge sensitive */ 217 /* XXX: TODO: actual reaction may depends on HID0 status 218 * 603/604/740/750: check HID0[EMCP] 219 */ 220 if (cur_level == 1 && level == 0) { 221 LOG_IRQ("%s: raise machine check state\n", 222 __func__); 223 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 224 } 225 break; 226 case PPC970_INPUT_CKSTP: 227 /* Level sensitive - active low */ 228 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 229 if (level) { 230 LOG_IRQ("%s: stop the CPU\n", __func__); 231 cs->halted = 1; 232 } else { 233 LOG_IRQ("%s: restart the CPU\n", __func__); 234 cs->halted = 0; 235 qemu_cpu_kick(cs); 236 } 237 break; 238 case PPC970_INPUT_HRESET: 239 /* Level sensitive - active low */ 240 if (level) { 241 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 242 } 243 break; 244 case PPC970_INPUT_SRESET: 245 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 246 __func__, level); 247 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 248 break; 249 case PPC970_INPUT_TBEN: 250 LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 251 level); 252 /* XXX: TODO */ 253 break; 254 default: 255 /* Unknown pin - do nothing */ 256 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 257 return; 258 } 259 if (level) 260 env->irq_input_state |= 1 << pin; 261 else 262 env->irq_input_state &= ~(1 << pin); 263 } 264 } 265 266 void ppc970_irq_init(PowerPCCPU *cpu) 267 { 268 CPUPPCState *env = &cpu->env; 269 270 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 271 PPC970_INPUT_NB); 272 } 273 274 /* POWER7 internal IRQ controller */ 275 static void power7_set_irq(void *opaque, int pin, int level) 276 { 277 PowerPCCPU *cpu = opaque; 278 279 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 280 &cpu->env, pin, level); 281 282 switch (pin) { 283 case POWER7_INPUT_INT: 284 /* Level sensitive - active high */ 285 LOG_IRQ("%s: set the external IRQ state to %d\n", 286 __func__, level); 287 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 288 break; 289 default: 290 /* Unknown pin - do nothing */ 291 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 292 return; 293 } 294 } 295 296 void ppcPOWER7_irq_init(PowerPCCPU *cpu) 297 { 298 CPUPPCState *env = &cpu->env; 299 300 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 301 POWER7_INPUT_NB); 302 } 303 304 /* POWER9 internal IRQ controller */ 305 static void power9_set_irq(void *opaque, int pin, int level) 306 { 307 PowerPCCPU *cpu = opaque; 308 309 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 310 &cpu->env, pin, level); 311 312 switch (pin) { 313 case POWER9_INPUT_INT: 314 /* Level sensitive - active high */ 315 LOG_IRQ("%s: set the external IRQ state to %d\n", 316 __func__, level); 317 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 318 break; 319 case POWER9_INPUT_HINT: 320 /* Level sensitive - active high */ 321 LOG_IRQ("%s: set the external IRQ state to %d\n", 322 __func__, level); 323 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); 324 break; 325 default: 326 /* Unknown pin - do nothing */ 327 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 328 return; 329 } 330 } 331 332 void ppcPOWER9_irq_init(PowerPCCPU *cpu) 333 { 334 CPUPPCState *env = &cpu->env; 335 336 env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu, 337 POWER9_INPUT_NB); 338 } 339 #endif /* defined(TARGET_PPC64) */ 340 341 void ppc40x_core_reset(PowerPCCPU *cpu) 342 { 343 CPUPPCState *env = &cpu->env; 344 target_ulong dbsr; 345 346 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); 347 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 348 dbsr = env->spr[SPR_40x_DBSR]; 349 dbsr &= ~0x00000300; 350 dbsr |= 0x00000100; 351 env->spr[SPR_40x_DBSR] = dbsr; 352 } 353 354 void ppc40x_chip_reset(PowerPCCPU *cpu) 355 { 356 CPUPPCState *env = &cpu->env; 357 target_ulong dbsr; 358 359 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); 360 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 361 /* XXX: TODO reset all internal peripherals */ 362 dbsr = env->spr[SPR_40x_DBSR]; 363 dbsr &= ~0x00000300; 364 dbsr |= 0x00000200; 365 env->spr[SPR_40x_DBSR] = dbsr; 366 } 367 368 void ppc40x_system_reset(PowerPCCPU *cpu) 369 { 370 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); 371 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 372 } 373 374 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) 375 { 376 PowerPCCPU *cpu = env_archcpu(env); 377 378 switch ((val >> 28) & 0x3) { 379 case 0x0: 380 /* No action */ 381 break; 382 case 0x1: 383 /* Core reset */ 384 ppc40x_core_reset(cpu); 385 break; 386 case 0x2: 387 /* Chip reset */ 388 ppc40x_chip_reset(cpu); 389 break; 390 case 0x3: 391 /* System reset */ 392 ppc40x_system_reset(cpu); 393 break; 394 } 395 } 396 397 /* PowerPC 40x internal IRQ controller */ 398 static void ppc40x_set_irq(void *opaque, int pin, int level) 399 { 400 PowerPCCPU *cpu = opaque; 401 CPUPPCState *env = &cpu->env; 402 int cur_level; 403 404 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 405 env, pin, level); 406 cur_level = (env->irq_input_state >> pin) & 1; 407 /* Don't generate spurious events */ 408 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 409 CPUState *cs = CPU(cpu); 410 411 switch (pin) { 412 case PPC40x_INPUT_RESET_SYS: 413 if (level) { 414 LOG_IRQ("%s: reset the PowerPC system\n", 415 __func__); 416 ppc40x_system_reset(cpu); 417 } 418 break; 419 case PPC40x_INPUT_RESET_CHIP: 420 if (level) { 421 LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 422 ppc40x_chip_reset(cpu); 423 } 424 break; 425 case PPC40x_INPUT_RESET_CORE: 426 /* XXX: TODO: update DBSR[MRR] */ 427 if (level) { 428 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 429 ppc40x_core_reset(cpu); 430 } 431 break; 432 case PPC40x_INPUT_CINT: 433 /* Level sensitive - active high */ 434 LOG_IRQ("%s: set the critical IRQ state to %d\n", 435 __func__, level); 436 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 437 break; 438 case PPC40x_INPUT_INT: 439 /* Level sensitive - active high */ 440 LOG_IRQ("%s: set the external IRQ state to %d\n", 441 __func__, level); 442 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 443 break; 444 case PPC40x_INPUT_HALT: 445 /* Level sensitive - active low */ 446 if (level) { 447 LOG_IRQ("%s: stop the CPU\n", __func__); 448 cs->halted = 1; 449 } else { 450 LOG_IRQ("%s: restart the CPU\n", __func__); 451 cs->halted = 0; 452 qemu_cpu_kick(cs); 453 } 454 break; 455 case PPC40x_INPUT_DEBUG: 456 /* Level sensitive - active high */ 457 LOG_IRQ("%s: set the debug pin state to %d\n", 458 __func__, level); 459 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 460 break; 461 default: 462 /* Unknown pin - do nothing */ 463 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 464 return; 465 } 466 if (level) 467 env->irq_input_state |= 1 << pin; 468 else 469 env->irq_input_state &= ~(1 << pin); 470 } 471 } 472 473 void ppc40x_irq_init(PowerPCCPU *cpu) 474 { 475 CPUPPCState *env = &cpu->env; 476 477 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 478 cpu, PPC40x_INPUT_NB); 479 } 480 481 /* PowerPC E500 internal IRQ controller */ 482 static void ppce500_set_irq(void *opaque, int pin, int level) 483 { 484 PowerPCCPU *cpu = opaque; 485 CPUPPCState *env = &cpu->env; 486 int cur_level; 487 488 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 489 env, pin, level); 490 cur_level = (env->irq_input_state >> pin) & 1; 491 /* Don't generate spurious events */ 492 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 493 switch (pin) { 494 case PPCE500_INPUT_MCK: 495 if (level) { 496 LOG_IRQ("%s: reset the PowerPC system\n", 497 __func__); 498 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 499 } 500 break; 501 case PPCE500_INPUT_RESET_CORE: 502 if (level) { 503 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 504 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 505 } 506 break; 507 case PPCE500_INPUT_CINT: 508 /* Level sensitive - active high */ 509 LOG_IRQ("%s: set the critical IRQ state to %d\n", 510 __func__, level); 511 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 512 break; 513 case PPCE500_INPUT_INT: 514 /* Level sensitive - active high */ 515 LOG_IRQ("%s: set the core IRQ state to %d\n", 516 __func__, level); 517 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 518 break; 519 case PPCE500_INPUT_DEBUG: 520 /* Level sensitive - active high */ 521 LOG_IRQ("%s: set the debug pin state to %d\n", 522 __func__, level); 523 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 524 break; 525 default: 526 /* Unknown pin - do nothing */ 527 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 528 return; 529 } 530 if (level) 531 env->irq_input_state |= 1 << pin; 532 else 533 env->irq_input_state &= ~(1 << pin); 534 } 535 } 536 537 void ppce500_irq_init(PowerPCCPU *cpu) 538 { 539 CPUPPCState *env = &cpu->env; 540 541 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 542 cpu, PPCE500_INPUT_NB); 543 } 544 545 /* Enable or Disable the E500 EPR capability */ 546 void ppce500_set_mpic_proxy(bool enabled) 547 { 548 CPUState *cs; 549 550 CPU_FOREACH(cs) { 551 PowerPCCPU *cpu = POWERPC_CPU(cs); 552 553 cpu->env.mpic_proxy = enabled; 554 if (kvm_enabled()) { 555 kvmppc_set_mpic_proxy(cpu, enabled); 556 } 557 } 558 } 559 560 /*****************************************************************************/ 561 /* PowerPC time base and decrementer emulation */ 562 563 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 564 { 565 /* TB time in tb periods */ 566 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; 567 } 568 569 uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 570 { 571 ppc_tb_t *tb_env = env->tb_env; 572 uint64_t tb; 573 574 if (kvm_enabled()) { 575 return env->spr[SPR_TBL]; 576 } 577 578 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 579 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 580 581 return tb; 582 } 583 584 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 585 { 586 ppc_tb_t *tb_env = env->tb_env; 587 uint64_t tb; 588 589 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 590 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 591 592 return tb >> 32; 593 } 594 595 uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 596 { 597 if (kvm_enabled()) { 598 return env->spr[SPR_TBU]; 599 } 600 601 return _cpu_ppc_load_tbu(env); 602 } 603 604 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 605 int64_t *tb_offsetp, uint64_t value) 606 { 607 *tb_offsetp = value - 608 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 609 610 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 611 __func__, value, *tb_offsetp); 612 } 613 614 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 615 { 616 ppc_tb_t *tb_env = env->tb_env; 617 uint64_t tb; 618 619 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 620 tb &= 0xFFFFFFFF00000000ULL; 621 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 622 &tb_env->tb_offset, tb | (uint64_t)value); 623 } 624 625 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 626 { 627 ppc_tb_t *tb_env = env->tb_env; 628 uint64_t tb; 629 630 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 631 tb &= 0x00000000FFFFFFFFULL; 632 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 633 &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 634 } 635 636 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 637 { 638 _cpu_ppc_store_tbu(env, value); 639 } 640 641 uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 642 { 643 ppc_tb_t *tb_env = env->tb_env; 644 uint64_t tb; 645 646 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 647 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 648 649 return tb; 650 } 651 652 uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 653 { 654 ppc_tb_t *tb_env = env->tb_env; 655 uint64_t tb; 656 657 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 658 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 659 660 return tb >> 32; 661 } 662 663 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 664 { 665 ppc_tb_t *tb_env = env->tb_env; 666 uint64_t tb; 667 668 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 669 tb &= 0xFFFFFFFF00000000ULL; 670 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 671 &tb_env->atb_offset, tb | (uint64_t)value); 672 } 673 674 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 675 { 676 ppc_tb_t *tb_env = env->tb_env; 677 uint64_t tb; 678 679 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 680 tb &= 0x00000000FFFFFFFFULL; 681 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 682 &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 683 } 684 685 uint64_t cpu_ppc_load_vtb(CPUPPCState *env) 686 { 687 ppc_tb_t *tb_env = env->tb_env; 688 689 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 690 tb_env->vtb_offset); 691 } 692 693 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) 694 { 695 ppc_tb_t *tb_env = env->tb_env; 696 697 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 698 &tb_env->vtb_offset, value); 699 } 700 701 static void cpu_ppc_tb_stop (CPUPPCState *env) 702 { 703 ppc_tb_t *tb_env = env->tb_env; 704 uint64_t tb, atb, vmclk; 705 706 /* If the time base is already frozen, do nothing */ 707 if (tb_env->tb_freq != 0) { 708 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 709 /* Get the time base */ 710 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 711 /* Get the alternate time base */ 712 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 713 /* Store the time base value (ie compute the current offset) */ 714 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 715 /* Store the alternate time base value (compute the current offset) */ 716 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 717 /* Set the time base frequency to zero */ 718 tb_env->tb_freq = 0; 719 /* Now, the time bases are frozen to tb_offset / atb_offset value */ 720 } 721 } 722 723 static void cpu_ppc_tb_start (CPUPPCState *env) 724 { 725 ppc_tb_t *tb_env = env->tb_env; 726 uint64_t tb, atb, vmclk; 727 728 /* If the time base is not frozen, do nothing */ 729 if (tb_env->tb_freq == 0) { 730 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 731 /* Get the time base from tb_offset */ 732 tb = tb_env->tb_offset; 733 /* Get the alternate time base from atb_offset */ 734 atb = tb_env->atb_offset; 735 /* Restore the tb frequency from the decrementer frequency */ 736 tb_env->tb_freq = tb_env->decr_freq; 737 /* Store the time base value */ 738 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 739 /* Store the alternate time base value */ 740 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 741 } 742 } 743 744 bool ppc_decr_clear_on_delivery(CPUPPCState *env) 745 { 746 ppc_tb_t *tb_env = env->tb_env; 747 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 748 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 749 } 750 751 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 752 { 753 ppc_tb_t *tb_env = env->tb_env; 754 int64_t decr, diff; 755 756 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 757 if (diff >= 0) { 758 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 759 } else if (tb_env->flags & PPC_TIMER_BOOKE) { 760 decr = 0; 761 } else { 762 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 763 } 764 LOG_TB("%s: %016" PRIx64 "\n", __func__, decr); 765 766 return decr; 767 } 768 769 target_ulong cpu_ppc_load_decr(CPUPPCState *env) 770 { 771 ppc_tb_t *tb_env = env->tb_env; 772 uint64_t decr; 773 774 if (kvm_enabled()) { 775 return env->spr[SPR_DECR]; 776 } 777 778 decr = _cpu_ppc_load_decr(env, tb_env->decr_next); 779 780 /* 781 * If large decrementer is enabled then the decrementer is signed extened 782 * to 64 bits, otherwise it is a 32 bit value. 783 */ 784 if (env->spr[SPR_LPCR] & LPCR_LD) { 785 return decr; 786 } 787 return (uint32_t) decr; 788 } 789 790 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) 791 { 792 PowerPCCPU *cpu = env_archcpu(env); 793 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 794 ppc_tb_t *tb_env = env->tb_env; 795 uint64_t hdecr; 796 797 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); 798 799 /* 800 * If we have a large decrementer (POWER9 or later) then hdecr is sign 801 * extended to 64 bits, otherwise it is 32 bits. 802 */ 803 if (pcc->lrg_decr_bits > 32) { 804 return hdecr; 805 } 806 return (uint32_t) hdecr; 807 } 808 809 uint64_t cpu_ppc_load_purr (CPUPPCState *env) 810 { 811 ppc_tb_t *tb_env = env->tb_env; 812 813 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 814 tb_env->purr_offset); 815 } 816 817 /* When decrementer expires, 818 * all we need to do is generate or queue a CPU exception 819 */ 820 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 821 { 822 /* Raise it */ 823 LOG_TB("raise decrementer exception\n"); 824 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 825 } 826 827 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 828 { 829 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 830 } 831 832 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 833 { 834 CPUPPCState *env = &cpu->env; 835 836 /* Raise it */ 837 LOG_TB("raise hv decrementer exception\n"); 838 839 /* The architecture specifies that we don't deliver HDEC 840 * interrupts in a PM state. Not only they don't cause a 841 * wakeup but they also get effectively discarded. 842 */ 843 if (!env->resume_as_sreset) { 844 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 845 } 846 } 847 848 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 849 { 850 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 851 } 852 853 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 854 QEMUTimer *timer, 855 void (*raise_excp)(void *), 856 void (*lower_excp)(PowerPCCPU *), 857 target_ulong decr, target_ulong value, 858 int nr_bits) 859 { 860 CPUPPCState *env = &cpu->env; 861 ppc_tb_t *tb_env = env->tb_env; 862 uint64_t now, next; 863 bool negative; 864 865 /* Truncate value to decr_width and sign extend for simplicity */ 866 value &= ((1ULL << nr_bits) - 1); 867 negative = !!(value & (1ULL << (nr_bits - 1))); 868 if (negative) { 869 value |= (0xFFFFFFFFULL << nr_bits); 870 } 871 872 LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__, 873 decr, value); 874 875 if (kvm_enabled()) { 876 /* KVM handles decrementer exceptions, we don't need our own timer */ 877 return; 878 } 879 880 /* 881 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 882 * interrupt. 883 * 884 * If we get a really small DEC value, we can assume that by the time we 885 * handled it we should inject an interrupt already. 886 * 887 * On MSB level based DEC implementations the MSB always means the interrupt 888 * is pending, so raise it on those. 889 * 890 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 891 * an edge interrupt, so raise it here too. 892 */ 893 if ((value < 3) || 894 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || 895 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative 896 && !(decr & (1ULL << (nr_bits - 1))))) { 897 (*raise_excp)(cpu); 898 return; 899 } 900 901 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 902 if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 903 (*lower_excp)(cpu); 904 } 905 906 /* Calculate the next timer event */ 907 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 908 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 909 *nextp = next; 910 911 /* Adjust timer */ 912 timer_mod(timer, next); 913 } 914 915 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, 916 target_ulong value, int nr_bits) 917 { 918 ppc_tb_t *tb_env = cpu->env.tb_env; 919 920 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 921 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 922 value, nr_bits); 923 } 924 925 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) 926 { 927 PowerPCCPU *cpu = env_archcpu(env); 928 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 929 int nr_bits = 32; 930 931 if (env->spr[SPR_LPCR] & LPCR_LD) { 932 nr_bits = pcc->lrg_decr_bits; 933 } 934 935 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); 936 } 937 938 static void cpu_ppc_decr_cb(void *opaque) 939 { 940 PowerPCCPU *cpu = opaque; 941 942 cpu_ppc_decr_excp(cpu); 943 } 944 945 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, 946 target_ulong value, int nr_bits) 947 { 948 ppc_tb_t *tb_env = cpu->env.tb_env; 949 950 if (tb_env->hdecr_timer != NULL) { 951 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 952 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 953 hdecr, value, nr_bits); 954 } 955 } 956 957 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) 958 { 959 PowerPCCPU *cpu = env_archcpu(env); 960 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 961 962 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 963 pcc->lrg_decr_bits); 964 } 965 966 static void cpu_ppc_hdecr_cb(void *opaque) 967 { 968 PowerPCCPU *cpu = opaque; 969 970 cpu_ppc_hdecr_excp(cpu); 971 } 972 973 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) 974 { 975 ppc_tb_t *tb_env = env->tb_env; 976 977 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 978 &tb_env->purr_offset, value); 979 } 980 981 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 982 { 983 CPUPPCState *env = opaque; 984 PowerPCCPU *cpu = env_archcpu(env); 985 ppc_tb_t *tb_env = env->tb_env; 986 987 tb_env->tb_freq = freq; 988 tb_env->decr_freq = freq; 989 /* There is a bug in Linux 2.4 kernels: 990 * if a decrementer exception is pending when it enables msr_ee at startup, 991 * it's not ready to handle it... 992 */ 993 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 994 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 995 cpu_ppc_store_purr(env, 0x0000000000000000ULL); 996 } 997 998 static void timebase_save(PPCTimebase *tb) 999 { 1000 uint64_t ticks = cpu_get_host_ticks(); 1001 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1002 1003 if (!first_ppc_cpu->env.tb_env) { 1004 error_report("No timebase object"); 1005 return; 1006 } 1007 1008 /* not used anymore, we keep it for compatibility */ 1009 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 1010 /* 1011 * tb_offset is only expected to be changed by QEMU so 1012 * there is no need to update it from KVM here 1013 */ 1014 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 1015 1016 tb->runstate_paused = runstate_check(RUN_STATE_PAUSED); 1017 } 1018 1019 static void timebase_load(PPCTimebase *tb) 1020 { 1021 CPUState *cpu; 1022 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1023 int64_t tb_off_adj, tb_off; 1024 unsigned long freq; 1025 1026 if (!first_ppc_cpu->env.tb_env) { 1027 error_report("No timebase object"); 1028 return; 1029 } 1030 1031 freq = first_ppc_cpu->env.tb_env->tb_freq; 1032 1033 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); 1034 1035 tb_off = first_ppc_cpu->env.tb_env->tb_offset; 1036 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 1037 (tb_off_adj - tb_off) / freq); 1038 1039 /* Set new offset to all CPUs */ 1040 CPU_FOREACH(cpu) { 1041 PowerPCCPU *pcpu = POWERPC_CPU(cpu); 1042 pcpu->env.tb_env->tb_offset = tb_off_adj; 1043 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); 1044 } 1045 } 1046 1047 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 1048 RunState state) 1049 { 1050 PPCTimebase *tb = opaque; 1051 1052 if (running) { 1053 timebase_load(tb); 1054 } else { 1055 timebase_save(tb); 1056 } 1057 } 1058 1059 /* 1060 * When migrating a running guest, read the clock just 1061 * before migration, so that the guest clock counts 1062 * during the events between: 1063 * 1064 * * vm_stop() 1065 * * 1066 * * pre_save() 1067 * 1068 * This reduces clock difference on migration from 5s 1069 * to 0.1s (when max_downtime == 5s), because sending the 1070 * final pages of memory (which happens between vm_stop() 1071 * and pre_save()) takes max_downtime. 1072 */ 1073 static int timebase_pre_save(void *opaque) 1074 { 1075 PPCTimebase *tb = opaque; 1076 1077 /* guest_timebase won't be overridden in case of paused guest */ 1078 if (!tb->runstate_paused) { 1079 timebase_save(tb); 1080 } 1081 1082 return 0; 1083 } 1084 1085 const VMStateDescription vmstate_ppc_timebase = { 1086 .name = "timebase", 1087 .version_id = 1, 1088 .minimum_version_id = 1, 1089 .minimum_version_id_old = 1, 1090 .pre_save = timebase_pre_save, 1091 .fields = (VMStateField []) { 1092 VMSTATE_UINT64(guest_timebase, PPCTimebase), 1093 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 1094 VMSTATE_END_OF_LIST() 1095 }, 1096 }; 1097 1098 /* Set up (once) timebase frequency (in Hz) */ 1099 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 1100 { 1101 PowerPCCPU *cpu = env_archcpu(env); 1102 ppc_tb_t *tb_env; 1103 1104 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1105 env->tb_env = tb_env; 1106 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1107 if (is_book3s_arch2x(env)) { 1108 /* All Book3S 64bit CPUs implement level based DEC logic */ 1109 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 1110 } 1111 /* Create new timer */ 1112 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 1113 if (env->has_hv_mode) { 1114 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 1115 cpu); 1116 } else { 1117 tb_env->hdecr_timer = NULL; 1118 } 1119 cpu_ppc_set_tb_clk(env, freq); 1120 1121 return &cpu_ppc_set_tb_clk; 1122 } 1123 1124 /* Specific helpers for POWER & PowerPC 601 RTC */ 1125 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 1126 { 1127 _cpu_ppc_store_tbu(env, value); 1128 } 1129 1130 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 1131 { 1132 return _cpu_ppc_load_tbu(env); 1133 } 1134 1135 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 1136 { 1137 cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 1138 } 1139 1140 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 1141 { 1142 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1143 } 1144 1145 /*****************************************************************************/ 1146 /* PowerPC 40x timers */ 1147 1148 /* PIT, FIT & WDT */ 1149 typedef struct ppc40x_timer_t ppc40x_timer_t; 1150 struct ppc40x_timer_t { 1151 uint64_t pit_reload; /* PIT auto-reload value */ 1152 uint64_t fit_next; /* Tick for next FIT interrupt */ 1153 QEMUTimer *fit_timer; 1154 uint64_t wdt_next; /* Tick for next WDT interrupt */ 1155 QEMUTimer *wdt_timer; 1156 1157 /* 405 have the PIT, 440 have a DECR. */ 1158 unsigned int decr_excp; 1159 }; 1160 1161 /* Fixed interval timer */ 1162 static void cpu_4xx_fit_cb (void *opaque) 1163 { 1164 PowerPCCPU *cpu; 1165 CPUPPCState *env; 1166 ppc_tb_t *tb_env; 1167 ppc40x_timer_t *ppc40x_timer; 1168 uint64_t now, next; 1169 1170 env = opaque; 1171 cpu = env_archcpu(env); 1172 tb_env = env->tb_env; 1173 ppc40x_timer = tb_env->opaque; 1174 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1175 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 1176 case 0: 1177 next = 1 << 9; 1178 break; 1179 case 1: 1180 next = 1 << 13; 1181 break; 1182 case 2: 1183 next = 1 << 17; 1184 break; 1185 case 3: 1186 next = 1 << 21; 1187 break; 1188 default: 1189 /* Cannot occur, but makes gcc happy */ 1190 return; 1191 } 1192 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 1193 if (next == now) 1194 next++; 1195 timer_mod(ppc40x_timer->fit_timer, next); 1196 env->spr[SPR_40x_TSR] |= 1 << 26; 1197 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 1198 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 1199 } 1200 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1201 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 1202 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1203 } 1204 1205 /* Programmable interval timer */ 1206 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 1207 { 1208 ppc40x_timer_t *ppc40x_timer; 1209 uint64_t now, next; 1210 1211 ppc40x_timer = tb_env->opaque; 1212 if (ppc40x_timer->pit_reload <= 1 || 1213 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 1214 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 1215 /* Stop PIT */ 1216 LOG_TB("%s: stop PIT\n", __func__); 1217 timer_del(tb_env->decr_timer); 1218 } else { 1219 LOG_TB("%s: start PIT %016" PRIx64 "\n", 1220 __func__, ppc40x_timer->pit_reload); 1221 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1222 next = now + muldiv64(ppc40x_timer->pit_reload, 1223 NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1224 if (is_excp) 1225 next += tb_env->decr_next - now; 1226 if (next == now) 1227 next++; 1228 timer_mod(tb_env->decr_timer, next); 1229 tb_env->decr_next = next; 1230 } 1231 } 1232 1233 static void cpu_4xx_pit_cb (void *opaque) 1234 { 1235 PowerPCCPU *cpu; 1236 CPUPPCState *env; 1237 ppc_tb_t *tb_env; 1238 ppc40x_timer_t *ppc40x_timer; 1239 1240 env = opaque; 1241 cpu = env_archcpu(env); 1242 tb_env = env->tb_env; 1243 ppc40x_timer = tb_env->opaque; 1244 env->spr[SPR_40x_TSR] |= 1 << 27; 1245 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 1246 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 1247 } 1248 start_stop_pit(env, tb_env, 1); 1249 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 1250 "%016" PRIx64 "\n", __func__, 1251 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 1252 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 1253 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 1254 ppc40x_timer->pit_reload); 1255 } 1256 1257 /* Watchdog timer */ 1258 static void cpu_4xx_wdt_cb (void *opaque) 1259 { 1260 PowerPCCPU *cpu; 1261 CPUPPCState *env; 1262 ppc_tb_t *tb_env; 1263 ppc40x_timer_t *ppc40x_timer; 1264 uint64_t now, next; 1265 1266 env = opaque; 1267 cpu = env_archcpu(env); 1268 tb_env = env->tb_env; 1269 ppc40x_timer = tb_env->opaque; 1270 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1271 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 1272 case 0: 1273 next = 1 << 17; 1274 break; 1275 case 1: 1276 next = 1 << 21; 1277 break; 1278 case 2: 1279 next = 1 << 25; 1280 break; 1281 case 3: 1282 next = 1 << 29; 1283 break; 1284 default: 1285 /* Cannot occur, but makes gcc happy */ 1286 return; 1287 } 1288 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1289 if (next == now) 1290 next++; 1291 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1292 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1293 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 1294 case 0x0: 1295 case 0x1: 1296 timer_mod(ppc40x_timer->wdt_timer, next); 1297 ppc40x_timer->wdt_next = next; 1298 env->spr[SPR_40x_TSR] |= 1U << 31; 1299 break; 1300 case 0x2: 1301 timer_mod(ppc40x_timer->wdt_timer, next); 1302 ppc40x_timer->wdt_next = next; 1303 env->spr[SPR_40x_TSR] |= 1 << 30; 1304 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 1305 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 1306 } 1307 break; 1308 case 0x3: 1309 env->spr[SPR_40x_TSR] &= ~0x30000000; 1310 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 1311 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 1312 case 0x0: 1313 /* No reset */ 1314 break; 1315 case 0x1: /* Core reset */ 1316 ppc40x_core_reset(cpu); 1317 break; 1318 case 0x2: /* Chip reset */ 1319 ppc40x_chip_reset(cpu); 1320 break; 1321 case 0x3: /* System reset */ 1322 ppc40x_system_reset(cpu); 1323 break; 1324 } 1325 } 1326 } 1327 1328 void store_40x_pit (CPUPPCState *env, target_ulong val) 1329 { 1330 ppc_tb_t *tb_env; 1331 ppc40x_timer_t *ppc40x_timer; 1332 1333 tb_env = env->tb_env; 1334 ppc40x_timer = tb_env->opaque; 1335 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 1336 ppc40x_timer->pit_reload = val; 1337 start_stop_pit(env, tb_env, 0); 1338 } 1339 1340 target_ulong load_40x_pit (CPUPPCState *env) 1341 { 1342 return cpu_ppc_load_decr(env); 1343 } 1344 1345 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 1346 { 1347 CPUPPCState *env = opaque; 1348 ppc_tb_t *tb_env = env->tb_env; 1349 1350 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 1351 freq); 1352 tb_env->tb_freq = freq; 1353 tb_env->decr_freq = freq; 1354 /* XXX: we should also update all timers */ 1355 } 1356 1357 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 1358 unsigned int decr_excp) 1359 { 1360 ppc_tb_t *tb_env; 1361 ppc40x_timer_t *ppc40x_timer; 1362 1363 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1364 env->tb_env = tb_env; 1365 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1366 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 1367 tb_env->tb_freq = freq; 1368 tb_env->decr_freq = freq; 1369 tb_env->opaque = ppc40x_timer; 1370 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 1371 if (ppc40x_timer != NULL) { 1372 /* We use decr timer for PIT */ 1373 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 1374 ppc40x_timer->fit_timer = 1375 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 1376 ppc40x_timer->wdt_timer = 1377 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 1378 ppc40x_timer->decr_excp = decr_excp; 1379 } 1380 1381 return &ppc_40x_set_tb_clk; 1382 } 1383 1384 /*****************************************************************************/ 1385 /* Embedded PowerPC Device Control Registers */ 1386 typedef struct ppc_dcrn_t ppc_dcrn_t; 1387 struct ppc_dcrn_t { 1388 dcr_read_cb dcr_read; 1389 dcr_write_cb dcr_write; 1390 void *opaque; 1391 }; 1392 1393 /* XXX: on 460, DCR addresses are 32 bits wide, 1394 * using DCRIPR to get the 22 upper bits of the DCR address 1395 */ 1396 #define DCRN_NB 1024 1397 struct ppc_dcr_t { 1398 ppc_dcrn_t dcrn[DCRN_NB]; 1399 int (*read_error)(int dcrn); 1400 int (*write_error)(int dcrn); 1401 }; 1402 1403 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1404 { 1405 ppc_dcrn_t *dcr; 1406 1407 if (dcrn < 0 || dcrn >= DCRN_NB) 1408 goto error; 1409 dcr = &dcr_env->dcrn[dcrn]; 1410 if (dcr->dcr_read == NULL) 1411 goto error; 1412 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 1413 1414 return 0; 1415 1416 error: 1417 if (dcr_env->read_error != NULL) 1418 return (*dcr_env->read_error)(dcrn); 1419 1420 return -1; 1421 } 1422 1423 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1424 { 1425 ppc_dcrn_t *dcr; 1426 1427 if (dcrn < 0 || dcrn >= DCRN_NB) 1428 goto error; 1429 dcr = &dcr_env->dcrn[dcrn]; 1430 if (dcr->dcr_write == NULL) 1431 goto error; 1432 (*dcr->dcr_write)(dcr->opaque, dcrn, val); 1433 1434 return 0; 1435 1436 error: 1437 if (dcr_env->write_error != NULL) 1438 return (*dcr_env->write_error)(dcrn); 1439 1440 return -1; 1441 } 1442 1443 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 1444 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 1445 { 1446 ppc_dcr_t *dcr_env; 1447 ppc_dcrn_t *dcr; 1448 1449 dcr_env = env->dcr_env; 1450 if (dcr_env == NULL) 1451 return -1; 1452 if (dcrn < 0 || dcrn >= DCRN_NB) 1453 return -1; 1454 dcr = &dcr_env->dcrn[dcrn]; 1455 if (dcr->opaque != NULL || 1456 dcr->dcr_read != NULL || 1457 dcr->dcr_write != NULL) 1458 return -1; 1459 dcr->opaque = opaque; 1460 dcr->dcr_read = dcr_read; 1461 dcr->dcr_write = dcr_write; 1462 1463 return 0; 1464 } 1465 1466 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 1467 int (*write_error)(int dcrn)) 1468 { 1469 ppc_dcr_t *dcr_env; 1470 1471 dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 1472 dcr_env->read_error = read_error; 1473 dcr_env->write_error = write_error; 1474 env->dcr_env = dcr_env; 1475 1476 return 0; 1477 } 1478 1479 /*****************************************************************************/ 1480 /* Debug port */ 1481 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 1482 { 1483 addr &= 0xF; 1484 switch (addr) { 1485 case 0: 1486 printf("%c", val); 1487 break; 1488 case 1: 1489 printf("\n"); 1490 fflush(stdout); 1491 break; 1492 case 2: 1493 printf("Set loglevel to %04" PRIx32 "\n", val); 1494 qemu_set_log(val | 0x100); 1495 break; 1496 } 1497 } 1498 1499 int ppc_cpu_pir(PowerPCCPU *cpu) 1500 { 1501 CPUPPCState *env = &cpu->env; 1502 return env->spr_cb[SPR_PIR].default_value; 1503 } 1504 1505 PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1506 { 1507 CPUState *cs; 1508 1509 CPU_FOREACH(cs) { 1510 PowerPCCPU *cpu = POWERPC_CPU(cs); 1511 1512 if (ppc_cpu_pir(cpu) == pir) { 1513 return cpu; 1514 } 1515 } 1516 1517 return NULL; 1518 } 1519 1520 void ppc_irq_reset(PowerPCCPU *cpu) 1521 { 1522 CPUPPCState *env = &cpu->env; 1523 1524 env->irq_input_state = 0; 1525 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); 1526 } 1527