1 /* 2 * QEMU generic PowerPC hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/ppc/ppc.h" 28 #include "hw/ppc/ppc_e500.h" 29 #include "qemu/timer.h" 30 #include "sysemu/cpus.h" 31 #include "qemu/log.h" 32 #include "qemu/main-loop.h" 33 #include "qemu/error-report.h" 34 #include "sysemu/kvm.h" 35 #include "sysemu/runstate.h" 36 #include "kvm_ppc.h" 37 #include "migration/vmstate.h" 38 #include "trace.h" 39 40 //#define PPC_DEBUG_IRQ 41 //#define PPC_DEBUG_TB 42 43 #ifdef PPC_DEBUG_IRQ 44 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 45 #else 46 # define LOG_IRQ(...) do { } while (0) 47 #endif 48 49 50 #ifdef PPC_DEBUG_TB 51 # define LOG_TB(...) qemu_log(__VA_ARGS__) 52 #else 53 # define LOG_TB(...) do { } while (0) 54 #endif 55 56 static void cpu_ppc_tb_stop (CPUPPCState *env); 57 static void cpu_ppc_tb_start (CPUPPCState *env); 58 59 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 60 { 61 CPUState *cs = CPU(cpu); 62 CPUPPCState *env = &cpu->env; 63 unsigned int old_pending; 64 bool locked = false; 65 66 /* We may already have the BQL if coming from the reset path */ 67 if (!qemu_mutex_iothread_locked()) { 68 locked = true; 69 qemu_mutex_lock_iothread(); 70 } 71 72 old_pending = env->pending_interrupts; 73 74 if (level) { 75 env->pending_interrupts |= 1 << n_IRQ; 76 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 77 } else { 78 env->pending_interrupts &= ~(1 << n_IRQ); 79 if (env->pending_interrupts == 0) { 80 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 81 } 82 } 83 84 if (old_pending != env->pending_interrupts) { 85 kvmppc_set_interrupt(cpu, n_IRQ, level); 86 } 87 88 89 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 90 "req %08x\n", __func__, env, n_IRQ, level, 91 env->pending_interrupts, CPU(cpu)->interrupt_request); 92 93 if (locked) { 94 qemu_mutex_unlock_iothread(); 95 } 96 } 97 98 /* PowerPC 6xx / 7xx internal IRQ controller */ 99 static void ppc6xx_set_irq(void *opaque, int pin, int level) 100 { 101 PowerPCCPU *cpu = opaque; 102 CPUPPCState *env = &cpu->env; 103 int cur_level; 104 105 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 106 env, pin, level); 107 cur_level = (env->irq_input_state >> pin) & 1; 108 /* Don't generate spurious events */ 109 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 110 CPUState *cs = CPU(cpu); 111 112 switch (pin) { 113 case PPC6xx_INPUT_TBEN: 114 /* Level sensitive - active high */ 115 LOG_IRQ("%s: %s the time base\n", 116 __func__, level ? "start" : "stop"); 117 if (level) { 118 cpu_ppc_tb_start(env); 119 } else { 120 cpu_ppc_tb_stop(env); 121 } 122 break; 123 case PPC6xx_INPUT_INT: 124 /* Level sensitive - active high */ 125 LOG_IRQ("%s: set the external IRQ state to %d\n", 126 __func__, level); 127 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 128 break; 129 case PPC6xx_INPUT_SMI: 130 /* Level sensitive - active high */ 131 LOG_IRQ("%s: set the SMI IRQ state to %d\n", 132 __func__, level); 133 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 134 break; 135 case PPC6xx_INPUT_MCP: 136 /* Negative edge sensitive */ 137 /* XXX: TODO: actual reaction may depends on HID0 status 138 * 603/604/740/750: check HID0[EMCP] 139 */ 140 if (cur_level == 1 && level == 0) { 141 LOG_IRQ("%s: raise machine check state\n", 142 __func__); 143 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 144 } 145 break; 146 case PPC6xx_INPUT_CKSTP_IN: 147 /* Level sensitive - active low */ 148 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 149 /* XXX: Note that the only way to restart the CPU is to reset it */ 150 if (level) { 151 LOG_IRQ("%s: stop the CPU\n", __func__); 152 cs->halted = 1; 153 } 154 break; 155 case PPC6xx_INPUT_HRESET: 156 /* Level sensitive - active low */ 157 if (level) { 158 LOG_IRQ("%s: reset the CPU\n", __func__); 159 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 160 } 161 break; 162 case PPC6xx_INPUT_SRESET: 163 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 164 __func__, level); 165 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 166 break; 167 default: 168 g_assert_not_reached(); 169 } 170 if (level) 171 env->irq_input_state |= 1 << pin; 172 else 173 env->irq_input_state &= ~(1 << pin); 174 } 175 } 176 177 void ppc6xx_irq_init(PowerPCCPU *cpu) 178 { 179 CPUPPCState *env = &cpu->env; 180 181 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 182 PPC6xx_INPUT_NB); 183 } 184 185 #if defined(TARGET_PPC64) 186 /* PowerPC 970 internal IRQ controller */ 187 static void ppc970_set_irq(void *opaque, int pin, int level) 188 { 189 PowerPCCPU *cpu = opaque; 190 CPUPPCState *env = &cpu->env; 191 int cur_level; 192 193 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 194 env, pin, level); 195 cur_level = (env->irq_input_state >> pin) & 1; 196 /* Don't generate spurious events */ 197 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 198 CPUState *cs = CPU(cpu); 199 200 switch (pin) { 201 case PPC970_INPUT_INT: 202 /* Level sensitive - active high */ 203 LOG_IRQ("%s: set the external IRQ state to %d\n", 204 __func__, level); 205 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 206 break; 207 case PPC970_INPUT_THINT: 208 /* Level sensitive - active high */ 209 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 210 level); 211 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 212 break; 213 case PPC970_INPUT_MCP: 214 /* Negative edge sensitive */ 215 /* XXX: TODO: actual reaction may depends on HID0 status 216 * 603/604/740/750: check HID0[EMCP] 217 */ 218 if (cur_level == 1 && level == 0) { 219 LOG_IRQ("%s: raise machine check state\n", 220 __func__); 221 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 222 } 223 break; 224 case PPC970_INPUT_CKSTP: 225 /* Level sensitive - active low */ 226 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 227 if (level) { 228 LOG_IRQ("%s: stop the CPU\n", __func__); 229 cs->halted = 1; 230 } else { 231 LOG_IRQ("%s: restart the CPU\n", __func__); 232 cs->halted = 0; 233 qemu_cpu_kick(cs); 234 } 235 break; 236 case PPC970_INPUT_HRESET: 237 /* Level sensitive - active low */ 238 if (level) { 239 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 240 } 241 break; 242 case PPC970_INPUT_SRESET: 243 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 244 __func__, level); 245 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 246 break; 247 case PPC970_INPUT_TBEN: 248 LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 249 level); 250 /* XXX: TODO */ 251 break; 252 default: 253 g_assert_not_reached(); 254 } 255 if (level) 256 env->irq_input_state |= 1 << pin; 257 else 258 env->irq_input_state &= ~(1 << pin); 259 } 260 } 261 262 void ppc970_irq_init(PowerPCCPU *cpu) 263 { 264 CPUPPCState *env = &cpu->env; 265 266 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 267 PPC970_INPUT_NB); 268 } 269 270 /* POWER7 internal IRQ controller */ 271 static void power7_set_irq(void *opaque, int pin, int level) 272 { 273 PowerPCCPU *cpu = opaque; 274 275 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 276 &cpu->env, pin, level); 277 278 switch (pin) { 279 case POWER7_INPUT_INT: 280 /* Level sensitive - active high */ 281 LOG_IRQ("%s: set the external IRQ state to %d\n", 282 __func__, level); 283 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 284 break; 285 default: 286 g_assert_not_reached(); 287 } 288 } 289 290 void ppcPOWER7_irq_init(PowerPCCPU *cpu) 291 { 292 CPUPPCState *env = &cpu->env; 293 294 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 295 POWER7_INPUT_NB); 296 } 297 298 /* POWER9 internal IRQ controller */ 299 static void power9_set_irq(void *opaque, int pin, int level) 300 { 301 PowerPCCPU *cpu = opaque; 302 303 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 304 &cpu->env, pin, level); 305 306 switch (pin) { 307 case POWER9_INPUT_INT: 308 /* Level sensitive - active high */ 309 LOG_IRQ("%s: set the external IRQ state to %d\n", 310 __func__, level); 311 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 312 break; 313 case POWER9_INPUT_HINT: 314 /* Level sensitive - active high */ 315 LOG_IRQ("%s: set the external IRQ state to %d\n", 316 __func__, level); 317 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); 318 break; 319 default: 320 g_assert_not_reached(); 321 } 322 } 323 324 void ppcPOWER9_irq_init(PowerPCCPU *cpu) 325 { 326 CPUPPCState *env = &cpu->env; 327 328 env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu, 329 POWER9_INPUT_NB); 330 } 331 #endif /* defined(TARGET_PPC64) */ 332 333 void ppc40x_core_reset(PowerPCCPU *cpu) 334 { 335 CPUPPCState *env = &cpu->env; 336 target_ulong dbsr; 337 338 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); 339 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 340 dbsr = env->spr[SPR_40x_DBSR]; 341 dbsr &= ~0x00000300; 342 dbsr |= 0x00000100; 343 env->spr[SPR_40x_DBSR] = dbsr; 344 } 345 346 void ppc40x_chip_reset(PowerPCCPU *cpu) 347 { 348 CPUPPCState *env = &cpu->env; 349 target_ulong dbsr; 350 351 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); 352 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 353 /* XXX: TODO reset all internal peripherals */ 354 dbsr = env->spr[SPR_40x_DBSR]; 355 dbsr &= ~0x00000300; 356 dbsr |= 0x00000200; 357 env->spr[SPR_40x_DBSR] = dbsr; 358 } 359 360 void ppc40x_system_reset(PowerPCCPU *cpu) 361 { 362 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); 363 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 364 } 365 366 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) 367 { 368 PowerPCCPU *cpu = env_archcpu(env); 369 370 switch ((val >> 28) & 0x3) { 371 case 0x0: 372 /* No action */ 373 break; 374 case 0x1: 375 /* Core reset */ 376 ppc40x_core_reset(cpu); 377 break; 378 case 0x2: 379 /* Chip reset */ 380 ppc40x_chip_reset(cpu); 381 break; 382 case 0x3: 383 /* System reset */ 384 ppc40x_system_reset(cpu); 385 break; 386 } 387 } 388 389 /* PowerPC 40x internal IRQ controller */ 390 static void ppc40x_set_irq(void *opaque, int pin, int level) 391 { 392 PowerPCCPU *cpu = opaque; 393 CPUPPCState *env = &cpu->env; 394 int cur_level; 395 396 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 397 env, pin, level); 398 cur_level = (env->irq_input_state >> pin) & 1; 399 /* Don't generate spurious events */ 400 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 401 CPUState *cs = CPU(cpu); 402 403 switch (pin) { 404 case PPC40x_INPUT_RESET_SYS: 405 if (level) { 406 LOG_IRQ("%s: reset the PowerPC system\n", 407 __func__); 408 ppc40x_system_reset(cpu); 409 } 410 break; 411 case PPC40x_INPUT_RESET_CHIP: 412 if (level) { 413 LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 414 ppc40x_chip_reset(cpu); 415 } 416 break; 417 case PPC40x_INPUT_RESET_CORE: 418 /* XXX: TODO: update DBSR[MRR] */ 419 if (level) { 420 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 421 ppc40x_core_reset(cpu); 422 } 423 break; 424 case PPC40x_INPUT_CINT: 425 /* Level sensitive - active high */ 426 LOG_IRQ("%s: set the critical IRQ state to %d\n", 427 __func__, level); 428 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 429 break; 430 case PPC40x_INPUT_INT: 431 /* Level sensitive - active high */ 432 LOG_IRQ("%s: set the external IRQ state to %d\n", 433 __func__, level); 434 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 435 break; 436 case PPC40x_INPUT_HALT: 437 /* Level sensitive - active low */ 438 if (level) { 439 LOG_IRQ("%s: stop the CPU\n", __func__); 440 cs->halted = 1; 441 } else { 442 LOG_IRQ("%s: restart the CPU\n", __func__); 443 cs->halted = 0; 444 qemu_cpu_kick(cs); 445 } 446 break; 447 case PPC40x_INPUT_DEBUG: 448 /* Level sensitive - active high */ 449 LOG_IRQ("%s: set the debug pin state to %d\n", 450 __func__, level); 451 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 452 break; 453 default: 454 g_assert_not_reached(); 455 } 456 if (level) 457 env->irq_input_state |= 1 << pin; 458 else 459 env->irq_input_state &= ~(1 << pin); 460 } 461 } 462 463 void ppc40x_irq_init(PowerPCCPU *cpu) 464 { 465 CPUPPCState *env = &cpu->env; 466 467 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 468 cpu, PPC40x_INPUT_NB); 469 } 470 471 /* PowerPC E500 internal IRQ controller */ 472 static void ppce500_set_irq(void *opaque, int pin, int level) 473 { 474 PowerPCCPU *cpu = opaque; 475 CPUPPCState *env = &cpu->env; 476 int cur_level; 477 478 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 479 env, pin, level); 480 cur_level = (env->irq_input_state >> pin) & 1; 481 /* Don't generate spurious events */ 482 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 483 switch (pin) { 484 case PPCE500_INPUT_MCK: 485 if (level) { 486 LOG_IRQ("%s: reset the PowerPC system\n", 487 __func__); 488 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 489 } 490 break; 491 case PPCE500_INPUT_RESET_CORE: 492 if (level) { 493 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 494 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 495 } 496 break; 497 case PPCE500_INPUT_CINT: 498 /* Level sensitive - active high */ 499 LOG_IRQ("%s: set the critical IRQ state to %d\n", 500 __func__, level); 501 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 502 break; 503 case PPCE500_INPUT_INT: 504 /* Level sensitive - active high */ 505 LOG_IRQ("%s: set the core IRQ state to %d\n", 506 __func__, level); 507 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 508 break; 509 case PPCE500_INPUT_DEBUG: 510 /* Level sensitive - active high */ 511 LOG_IRQ("%s: set the debug pin state to %d\n", 512 __func__, level); 513 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 514 break; 515 default: 516 g_assert_not_reached(); 517 } 518 if (level) 519 env->irq_input_state |= 1 << pin; 520 else 521 env->irq_input_state &= ~(1 << pin); 522 } 523 } 524 525 void ppce500_irq_init(PowerPCCPU *cpu) 526 { 527 CPUPPCState *env = &cpu->env; 528 529 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 530 cpu, PPCE500_INPUT_NB); 531 } 532 533 /* Enable or Disable the E500 EPR capability */ 534 void ppce500_set_mpic_proxy(bool enabled) 535 { 536 CPUState *cs; 537 538 CPU_FOREACH(cs) { 539 PowerPCCPU *cpu = POWERPC_CPU(cs); 540 541 cpu->env.mpic_proxy = enabled; 542 if (kvm_enabled()) { 543 kvmppc_set_mpic_proxy(cpu, enabled); 544 } 545 } 546 } 547 548 /*****************************************************************************/ 549 /* PowerPC time base and decrementer emulation */ 550 551 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 552 { 553 /* TB time in tb periods */ 554 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; 555 } 556 557 uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 558 { 559 ppc_tb_t *tb_env = env->tb_env; 560 uint64_t tb; 561 562 if (kvm_enabled()) { 563 return env->spr[SPR_TBL]; 564 } 565 566 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 567 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 568 569 return tb; 570 } 571 572 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 573 { 574 ppc_tb_t *tb_env = env->tb_env; 575 uint64_t tb; 576 577 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 578 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 579 580 return tb >> 32; 581 } 582 583 uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 584 { 585 if (kvm_enabled()) { 586 return env->spr[SPR_TBU]; 587 } 588 589 return _cpu_ppc_load_tbu(env); 590 } 591 592 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 593 int64_t *tb_offsetp, uint64_t value) 594 { 595 *tb_offsetp = value - 596 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 597 598 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 599 __func__, value, *tb_offsetp); 600 } 601 602 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 603 { 604 ppc_tb_t *tb_env = env->tb_env; 605 uint64_t tb; 606 607 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 608 tb &= 0xFFFFFFFF00000000ULL; 609 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 610 &tb_env->tb_offset, tb | (uint64_t)value); 611 } 612 613 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 614 { 615 ppc_tb_t *tb_env = env->tb_env; 616 uint64_t tb; 617 618 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 619 tb &= 0x00000000FFFFFFFFULL; 620 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 621 &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 622 } 623 624 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 625 { 626 _cpu_ppc_store_tbu(env, value); 627 } 628 629 uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 630 { 631 ppc_tb_t *tb_env = env->tb_env; 632 uint64_t tb; 633 634 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 635 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 636 637 return tb; 638 } 639 640 uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 641 { 642 ppc_tb_t *tb_env = env->tb_env; 643 uint64_t tb; 644 645 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 646 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 647 648 return tb >> 32; 649 } 650 651 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 652 { 653 ppc_tb_t *tb_env = env->tb_env; 654 uint64_t tb; 655 656 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 657 tb &= 0xFFFFFFFF00000000ULL; 658 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 659 &tb_env->atb_offset, tb | (uint64_t)value); 660 } 661 662 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 663 { 664 ppc_tb_t *tb_env = env->tb_env; 665 uint64_t tb; 666 667 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 668 tb &= 0x00000000FFFFFFFFULL; 669 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 670 &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 671 } 672 673 uint64_t cpu_ppc_load_vtb(CPUPPCState *env) 674 { 675 ppc_tb_t *tb_env = env->tb_env; 676 677 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 678 tb_env->vtb_offset); 679 } 680 681 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) 682 { 683 ppc_tb_t *tb_env = env->tb_env; 684 685 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 686 &tb_env->vtb_offset, value); 687 } 688 689 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) 690 { 691 ppc_tb_t *tb_env = env->tb_env; 692 uint64_t tb; 693 694 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 695 tb_env->tb_offset); 696 tb &= 0xFFFFFFUL; 697 tb |= (value & ~0xFFFFFFUL); 698 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 699 &tb_env->tb_offset, tb); 700 } 701 702 static void cpu_ppc_tb_stop (CPUPPCState *env) 703 { 704 ppc_tb_t *tb_env = env->tb_env; 705 uint64_t tb, atb, vmclk; 706 707 /* If the time base is already frozen, do nothing */ 708 if (tb_env->tb_freq != 0) { 709 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 710 /* Get the time base */ 711 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 712 /* Get the alternate time base */ 713 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 714 /* Store the time base value (ie compute the current offset) */ 715 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 716 /* Store the alternate time base value (compute the current offset) */ 717 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 718 /* Set the time base frequency to zero */ 719 tb_env->tb_freq = 0; 720 /* Now, the time bases are frozen to tb_offset / atb_offset value */ 721 } 722 } 723 724 static void cpu_ppc_tb_start (CPUPPCState *env) 725 { 726 ppc_tb_t *tb_env = env->tb_env; 727 uint64_t tb, atb, vmclk; 728 729 /* If the time base is not frozen, do nothing */ 730 if (tb_env->tb_freq == 0) { 731 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 732 /* Get the time base from tb_offset */ 733 tb = tb_env->tb_offset; 734 /* Get the alternate time base from atb_offset */ 735 atb = tb_env->atb_offset; 736 /* Restore the tb frequency from the decrementer frequency */ 737 tb_env->tb_freq = tb_env->decr_freq; 738 /* Store the time base value */ 739 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 740 /* Store the alternate time base value */ 741 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 742 } 743 } 744 745 bool ppc_decr_clear_on_delivery(CPUPPCState *env) 746 { 747 ppc_tb_t *tb_env = env->tb_env; 748 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 749 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 750 } 751 752 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 753 { 754 ppc_tb_t *tb_env = env->tb_env; 755 int64_t decr, diff; 756 757 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 758 if (diff >= 0) { 759 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 760 } else if (tb_env->flags & PPC_TIMER_BOOKE) { 761 decr = 0; 762 } else { 763 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 764 } 765 LOG_TB("%s: %016" PRIx64 "\n", __func__, decr); 766 767 return decr; 768 } 769 770 target_ulong cpu_ppc_load_decr(CPUPPCState *env) 771 { 772 ppc_tb_t *tb_env = env->tb_env; 773 uint64_t decr; 774 775 if (kvm_enabled()) { 776 return env->spr[SPR_DECR]; 777 } 778 779 decr = _cpu_ppc_load_decr(env, tb_env->decr_next); 780 781 /* 782 * If large decrementer is enabled then the decrementer is signed extened 783 * to 64 bits, otherwise it is a 32 bit value. 784 */ 785 if (env->spr[SPR_LPCR] & LPCR_LD) { 786 return decr; 787 } 788 return (uint32_t) decr; 789 } 790 791 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) 792 { 793 PowerPCCPU *cpu = env_archcpu(env); 794 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 795 ppc_tb_t *tb_env = env->tb_env; 796 uint64_t hdecr; 797 798 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); 799 800 /* 801 * If we have a large decrementer (POWER9 or later) then hdecr is sign 802 * extended to 64 bits, otherwise it is 32 bits. 803 */ 804 if (pcc->lrg_decr_bits > 32) { 805 return hdecr; 806 } 807 return (uint32_t) hdecr; 808 } 809 810 uint64_t cpu_ppc_load_purr (CPUPPCState *env) 811 { 812 ppc_tb_t *tb_env = env->tb_env; 813 814 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 815 tb_env->purr_offset); 816 } 817 818 /* When decrementer expires, 819 * all we need to do is generate or queue a CPU exception 820 */ 821 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 822 { 823 /* Raise it */ 824 LOG_TB("raise decrementer exception\n"); 825 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 826 } 827 828 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 829 { 830 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 831 } 832 833 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 834 { 835 CPUPPCState *env = &cpu->env; 836 837 /* Raise it */ 838 LOG_TB("raise hv decrementer exception\n"); 839 840 /* The architecture specifies that we don't deliver HDEC 841 * interrupts in a PM state. Not only they don't cause a 842 * wakeup but they also get effectively discarded. 843 */ 844 if (!env->resume_as_sreset) { 845 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 846 } 847 } 848 849 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 850 { 851 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 852 } 853 854 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 855 QEMUTimer *timer, 856 void (*raise_excp)(void *), 857 void (*lower_excp)(PowerPCCPU *), 858 target_ulong decr, target_ulong value, 859 int nr_bits) 860 { 861 CPUPPCState *env = &cpu->env; 862 ppc_tb_t *tb_env = env->tb_env; 863 uint64_t now, next; 864 bool negative; 865 866 /* Truncate value to decr_width and sign extend for simplicity */ 867 value &= ((1ULL << nr_bits) - 1); 868 negative = !!(value & (1ULL << (nr_bits - 1))); 869 if (negative) { 870 value |= (0xFFFFFFFFULL << nr_bits); 871 } 872 873 LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__, 874 decr, value); 875 876 if (kvm_enabled()) { 877 /* KVM handles decrementer exceptions, we don't need our own timer */ 878 return; 879 } 880 881 /* 882 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 883 * interrupt. 884 * 885 * If we get a really small DEC value, we can assume that by the time we 886 * handled it we should inject an interrupt already. 887 * 888 * On MSB level based DEC implementations the MSB always means the interrupt 889 * is pending, so raise it on those. 890 * 891 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 892 * an edge interrupt, so raise it here too. 893 */ 894 if ((value < 3) || 895 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || 896 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative 897 && !(decr & (1ULL << (nr_bits - 1))))) { 898 (*raise_excp)(cpu); 899 return; 900 } 901 902 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 903 if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 904 (*lower_excp)(cpu); 905 } 906 907 /* Calculate the next timer event */ 908 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 909 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 910 *nextp = next; 911 912 /* Adjust timer */ 913 timer_mod(timer, next); 914 } 915 916 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, 917 target_ulong value, int nr_bits) 918 { 919 ppc_tb_t *tb_env = cpu->env.tb_env; 920 921 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 922 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 923 value, nr_bits); 924 } 925 926 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) 927 { 928 PowerPCCPU *cpu = env_archcpu(env); 929 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 930 int nr_bits = 32; 931 932 if (env->spr[SPR_LPCR] & LPCR_LD) { 933 nr_bits = pcc->lrg_decr_bits; 934 } 935 936 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); 937 } 938 939 static void cpu_ppc_decr_cb(void *opaque) 940 { 941 PowerPCCPU *cpu = opaque; 942 943 cpu_ppc_decr_excp(cpu); 944 } 945 946 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, 947 target_ulong value, int nr_bits) 948 { 949 ppc_tb_t *tb_env = cpu->env.tb_env; 950 951 if (tb_env->hdecr_timer != NULL) { 952 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 953 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 954 hdecr, value, nr_bits); 955 } 956 } 957 958 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) 959 { 960 PowerPCCPU *cpu = env_archcpu(env); 961 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 962 963 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 964 pcc->lrg_decr_bits); 965 } 966 967 static void cpu_ppc_hdecr_cb(void *opaque) 968 { 969 PowerPCCPU *cpu = opaque; 970 971 cpu_ppc_hdecr_excp(cpu); 972 } 973 974 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) 975 { 976 ppc_tb_t *tb_env = env->tb_env; 977 978 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 979 &tb_env->purr_offset, value); 980 } 981 982 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 983 { 984 CPUPPCState *env = opaque; 985 PowerPCCPU *cpu = env_archcpu(env); 986 ppc_tb_t *tb_env = env->tb_env; 987 988 tb_env->tb_freq = freq; 989 tb_env->decr_freq = freq; 990 /* There is a bug in Linux 2.4 kernels: 991 * if a decrementer exception is pending when it enables msr_ee at startup, 992 * it's not ready to handle it... 993 */ 994 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 995 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 996 cpu_ppc_store_purr(env, 0x0000000000000000ULL); 997 } 998 999 static void timebase_save(PPCTimebase *tb) 1000 { 1001 uint64_t ticks = cpu_get_host_ticks(); 1002 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1003 1004 if (!first_ppc_cpu->env.tb_env) { 1005 error_report("No timebase object"); 1006 return; 1007 } 1008 1009 /* not used anymore, we keep it for compatibility */ 1010 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 1011 /* 1012 * tb_offset is only expected to be changed by QEMU so 1013 * there is no need to update it from KVM here 1014 */ 1015 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 1016 1017 tb->runstate_paused = 1018 runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM); 1019 } 1020 1021 static void timebase_load(PPCTimebase *tb) 1022 { 1023 CPUState *cpu; 1024 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1025 int64_t tb_off_adj, tb_off; 1026 unsigned long freq; 1027 1028 if (!first_ppc_cpu->env.tb_env) { 1029 error_report("No timebase object"); 1030 return; 1031 } 1032 1033 freq = first_ppc_cpu->env.tb_env->tb_freq; 1034 1035 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); 1036 1037 tb_off = first_ppc_cpu->env.tb_env->tb_offset; 1038 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 1039 (tb_off_adj - tb_off) / freq); 1040 1041 /* Set new offset to all CPUs */ 1042 CPU_FOREACH(cpu) { 1043 PowerPCCPU *pcpu = POWERPC_CPU(cpu); 1044 pcpu->env.tb_env->tb_offset = tb_off_adj; 1045 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); 1046 } 1047 } 1048 1049 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 1050 RunState state) 1051 { 1052 PPCTimebase *tb = opaque; 1053 1054 if (running) { 1055 timebase_load(tb); 1056 } else { 1057 timebase_save(tb); 1058 } 1059 } 1060 1061 /* 1062 * When migrating a running guest, read the clock just 1063 * before migration, so that the guest clock counts 1064 * during the events between: 1065 * 1066 * * vm_stop() 1067 * * 1068 * * pre_save() 1069 * 1070 * This reduces clock difference on migration from 5s 1071 * to 0.1s (when max_downtime == 5s), because sending the 1072 * final pages of memory (which happens between vm_stop() 1073 * and pre_save()) takes max_downtime. 1074 */ 1075 static int timebase_pre_save(void *opaque) 1076 { 1077 PPCTimebase *tb = opaque; 1078 1079 /* guest_timebase won't be overridden in case of paused guest or savevm */ 1080 if (!tb->runstate_paused) { 1081 timebase_save(tb); 1082 } 1083 1084 return 0; 1085 } 1086 1087 const VMStateDescription vmstate_ppc_timebase = { 1088 .name = "timebase", 1089 .version_id = 1, 1090 .minimum_version_id = 1, 1091 .minimum_version_id_old = 1, 1092 .pre_save = timebase_pre_save, 1093 .fields = (VMStateField []) { 1094 VMSTATE_UINT64(guest_timebase, PPCTimebase), 1095 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 1096 VMSTATE_END_OF_LIST() 1097 }, 1098 }; 1099 1100 /* Set up (once) timebase frequency (in Hz) */ 1101 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 1102 { 1103 PowerPCCPU *cpu = env_archcpu(env); 1104 ppc_tb_t *tb_env; 1105 1106 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1107 env->tb_env = tb_env; 1108 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1109 if (is_book3s_arch2x(env)) { 1110 /* All Book3S 64bit CPUs implement level based DEC logic */ 1111 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 1112 } 1113 /* Create new timer */ 1114 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 1115 if (env->has_hv_mode) { 1116 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 1117 cpu); 1118 } else { 1119 tb_env->hdecr_timer = NULL; 1120 } 1121 cpu_ppc_set_tb_clk(env, freq); 1122 1123 return &cpu_ppc_set_tb_clk; 1124 } 1125 1126 /* Specific helpers for POWER & PowerPC 601 RTC */ 1127 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 1128 { 1129 _cpu_ppc_store_tbu(env, value); 1130 } 1131 1132 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 1133 { 1134 return _cpu_ppc_load_tbu(env); 1135 } 1136 1137 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 1138 { 1139 cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 1140 } 1141 1142 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 1143 { 1144 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1145 } 1146 1147 /*****************************************************************************/ 1148 /* PowerPC 40x timers */ 1149 1150 /* PIT, FIT & WDT */ 1151 typedef struct ppc40x_timer_t ppc40x_timer_t; 1152 struct ppc40x_timer_t { 1153 uint64_t pit_reload; /* PIT auto-reload value */ 1154 uint64_t fit_next; /* Tick for next FIT interrupt */ 1155 QEMUTimer *fit_timer; 1156 uint64_t wdt_next; /* Tick for next WDT interrupt */ 1157 QEMUTimer *wdt_timer; 1158 1159 /* 405 have the PIT, 440 have a DECR. */ 1160 unsigned int decr_excp; 1161 }; 1162 1163 /* Fixed interval timer */ 1164 static void cpu_4xx_fit_cb (void *opaque) 1165 { 1166 PowerPCCPU *cpu; 1167 CPUPPCState *env; 1168 ppc_tb_t *tb_env; 1169 ppc40x_timer_t *ppc40x_timer; 1170 uint64_t now, next; 1171 1172 env = opaque; 1173 cpu = env_archcpu(env); 1174 tb_env = env->tb_env; 1175 ppc40x_timer = tb_env->opaque; 1176 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1177 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 1178 case 0: 1179 next = 1 << 9; 1180 break; 1181 case 1: 1182 next = 1 << 13; 1183 break; 1184 case 2: 1185 next = 1 << 17; 1186 break; 1187 case 3: 1188 next = 1 << 21; 1189 break; 1190 default: 1191 /* Cannot occur, but makes gcc happy */ 1192 return; 1193 } 1194 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 1195 if (next == now) 1196 next++; 1197 timer_mod(ppc40x_timer->fit_timer, next); 1198 env->spr[SPR_40x_TSR] |= 1 << 26; 1199 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 1200 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 1201 } 1202 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1203 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 1204 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1205 } 1206 1207 /* Programmable interval timer */ 1208 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 1209 { 1210 ppc40x_timer_t *ppc40x_timer; 1211 uint64_t now, next; 1212 1213 ppc40x_timer = tb_env->opaque; 1214 if (ppc40x_timer->pit_reload <= 1 || 1215 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 1216 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 1217 /* Stop PIT */ 1218 LOG_TB("%s: stop PIT\n", __func__); 1219 timer_del(tb_env->decr_timer); 1220 } else { 1221 LOG_TB("%s: start PIT %016" PRIx64 "\n", 1222 __func__, ppc40x_timer->pit_reload); 1223 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1224 next = now + muldiv64(ppc40x_timer->pit_reload, 1225 NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1226 if (is_excp) 1227 next += tb_env->decr_next - now; 1228 if (next == now) 1229 next++; 1230 timer_mod(tb_env->decr_timer, next); 1231 tb_env->decr_next = next; 1232 } 1233 } 1234 1235 static void cpu_4xx_pit_cb (void *opaque) 1236 { 1237 PowerPCCPU *cpu; 1238 CPUPPCState *env; 1239 ppc_tb_t *tb_env; 1240 ppc40x_timer_t *ppc40x_timer; 1241 1242 env = opaque; 1243 cpu = env_archcpu(env); 1244 tb_env = env->tb_env; 1245 ppc40x_timer = tb_env->opaque; 1246 env->spr[SPR_40x_TSR] |= 1 << 27; 1247 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 1248 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 1249 } 1250 start_stop_pit(env, tb_env, 1); 1251 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 1252 "%016" PRIx64 "\n", __func__, 1253 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 1254 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 1255 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 1256 ppc40x_timer->pit_reload); 1257 } 1258 1259 /* Watchdog timer */ 1260 static void cpu_4xx_wdt_cb (void *opaque) 1261 { 1262 PowerPCCPU *cpu; 1263 CPUPPCState *env; 1264 ppc_tb_t *tb_env; 1265 ppc40x_timer_t *ppc40x_timer; 1266 uint64_t now, next; 1267 1268 env = opaque; 1269 cpu = env_archcpu(env); 1270 tb_env = env->tb_env; 1271 ppc40x_timer = tb_env->opaque; 1272 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1273 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 1274 case 0: 1275 next = 1 << 17; 1276 break; 1277 case 1: 1278 next = 1 << 21; 1279 break; 1280 case 2: 1281 next = 1 << 25; 1282 break; 1283 case 3: 1284 next = 1 << 29; 1285 break; 1286 default: 1287 /* Cannot occur, but makes gcc happy */ 1288 return; 1289 } 1290 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1291 if (next == now) 1292 next++; 1293 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1294 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1295 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 1296 case 0x0: 1297 case 0x1: 1298 timer_mod(ppc40x_timer->wdt_timer, next); 1299 ppc40x_timer->wdt_next = next; 1300 env->spr[SPR_40x_TSR] |= 1U << 31; 1301 break; 1302 case 0x2: 1303 timer_mod(ppc40x_timer->wdt_timer, next); 1304 ppc40x_timer->wdt_next = next; 1305 env->spr[SPR_40x_TSR] |= 1 << 30; 1306 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 1307 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 1308 } 1309 break; 1310 case 0x3: 1311 env->spr[SPR_40x_TSR] &= ~0x30000000; 1312 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 1313 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 1314 case 0x0: 1315 /* No reset */ 1316 break; 1317 case 0x1: /* Core reset */ 1318 ppc40x_core_reset(cpu); 1319 break; 1320 case 0x2: /* Chip reset */ 1321 ppc40x_chip_reset(cpu); 1322 break; 1323 case 0x3: /* System reset */ 1324 ppc40x_system_reset(cpu); 1325 break; 1326 } 1327 } 1328 } 1329 1330 void store_40x_pit (CPUPPCState *env, target_ulong val) 1331 { 1332 ppc_tb_t *tb_env; 1333 ppc40x_timer_t *ppc40x_timer; 1334 1335 tb_env = env->tb_env; 1336 ppc40x_timer = tb_env->opaque; 1337 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 1338 ppc40x_timer->pit_reload = val; 1339 start_stop_pit(env, tb_env, 0); 1340 } 1341 1342 target_ulong load_40x_pit (CPUPPCState *env) 1343 { 1344 return cpu_ppc_load_decr(env); 1345 } 1346 1347 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 1348 { 1349 CPUPPCState *env = opaque; 1350 ppc_tb_t *tb_env = env->tb_env; 1351 1352 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 1353 freq); 1354 tb_env->tb_freq = freq; 1355 tb_env->decr_freq = freq; 1356 /* XXX: we should also update all timers */ 1357 } 1358 1359 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 1360 unsigned int decr_excp) 1361 { 1362 ppc_tb_t *tb_env; 1363 ppc40x_timer_t *ppc40x_timer; 1364 1365 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1366 env->tb_env = tb_env; 1367 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1368 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 1369 tb_env->tb_freq = freq; 1370 tb_env->decr_freq = freq; 1371 tb_env->opaque = ppc40x_timer; 1372 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 1373 if (ppc40x_timer != NULL) { 1374 /* We use decr timer for PIT */ 1375 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 1376 ppc40x_timer->fit_timer = 1377 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 1378 ppc40x_timer->wdt_timer = 1379 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 1380 ppc40x_timer->decr_excp = decr_excp; 1381 } 1382 1383 return &ppc_40x_set_tb_clk; 1384 } 1385 1386 /*****************************************************************************/ 1387 /* Embedded PowerPC Device Control Registers */ 1388 typedef struct ppc_dcrn_t ppc_dcrn_t; 1389 struct ppc_dcrn_t { 1390 dcr_read_cb dcr_read; 1391 dcr_write_cb dcr_write; 1392 void *opaque; 1393 }; 1394 1395 /* XXX: on 460, DCR addresses are 32 bits wide, 1396 * using DCRIPR to get the 22 upper bits of the DCR address 1397 */ 1398 #define DCRN_NB 1024 1399 struct ppc_dcr_t { 1400 ppc_dcrn_t dcrn[DCRN_NB]; 1401 int (*read_error)(int dcrn); 1402 int (*write_error)(int dcrn); 1403 }; 1404 1405 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1406 { 1407 ppc_dcrn_t *dcr; 1408 1409 if (dcrn < 0 || dcrn >= DCRN_NB) 1410 goto error; 1411 dcr = &dcr_env->dcrn[dcrn]; 1412 if (dcr->dcr_read == NULL) 1413 goto error; 1414 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 1415 1416 return 0; 1417 1418 error: 1419 if (dcr_env->read_error != NULL) 1420 return (*dcr_env->read_error)(dcrn); 1421 1422 return -1; 1423 } 1424 1425 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1426 { 1427 ppc_dcrn_t *dcr; 1428 1429 if (dcrn < 0 || dcrn >= DCRN_NB) 1430 goto error; 1431 dcr = &dcr_env->dcrn[dcrn]; 1432 if (dcr->dcr_write == NULL) 1433 goto error; 1434 (*dcr->dcr_write)(dcr->opaque, dcrn, val); 1435 1436 return 0; 1437 1438 error: 1439 if (dcr_env->write_error != NULL) 1440 return (*dcr_env->write_error)(dcrn); 1441 1442 return -1; 1443 } 1444 1445 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 1446 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 1447 { 1448 ppc_dcr_t *dcr_env; 1449 ppc_dcrn_t *dcr; 1450 1451 dcr_env = env->dcr_env; 1452 if (dcr_env == NULL) 1453 return -1; 1454 if (dcrn < 0 || dcrn >= DCRN_NB) 1455 return -1; 1456 dcr = &dcr_env->dcrn[dcrn]; 1457 if (dcr->opaque != NULL || 1458 dcr->dcr_read != NULL || 1459 dcr->dcr_write != NULL) 1460 return -1; 1461 dcr->opaque = opaque; 1462 dcr->dcr_read = dcr_read; 1463 dcr->dcr_write = dcr_write; 1464 1465 return 0; 1466 } 1467 1468 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 1469 int (*write_error)(int dcrn)) 1470 { 1471 ppc_dcr_t *dcr_env; 1472 1473 dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 1474 dcr_env->read_error = read_error; 1475 dcr_env->write_error = write_error; 1476 env->dcr_env = dcr_env; 1477 1478 return 0; 1479 } 1480 1481 /*****************************************************************************/ 1482 1483 int ppc_cpu_pir(PowerPCCPU *cpu) 1484 { 1485 CPUPPCState *env = &cpu->env; 1486 return env->spr_cb[SPR_PIR].default_value; 1487 } 1488 1489 PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1490 { 1491 CPUState *cs; 1492 1493 CPU_FOREACH(cs) { 1494 PowerPCCPU *cpu = POWERPC_CPU(cs); 1495 1496 if (ppc_cpu_pir(cpu) == pir) { 1497 return cpu; 1498 } 1499 } 1500 1501 return NULL; 1502 } 1503 1504 void ppc_irq_reset(PowerPCCPU *cpu) 1505 { 1506 CPUPPCState *env = &cpu->env; 1507 1508 env->irq_input_state = 0; 1509 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); 1510 } 1511