1 /* 2 * QEMU generic PowerPC hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/ppc/ppc.h" 28 #include "hw/ppc/ppc_e500.h" 29 #include "qemu/timer.h" 30 #include "sysemu/cpus.h" 31 #include "qemu/log.h" 32 #include "qemu/main-loop.h" 33 #include "qemu/error-report.h" 34 #include "sysemu/kvm.h" 35 #include "sysemu/runstate.h" 36 #include "kvm_ppc.h" 37 #include "migration/vmstate.h" 38 #include "trace.h" 39 40 static void cpu_ppc_tb_stop (CPUPPCState *env); 41 static void cpu_ppc_tb_start (CPUPPCState *env); 42 43 void ppc_set_irq(PowerPCCPU *cpu, int irq, int level) 44 { 45 CPUPPCState *env = &cpu->env; 46 unsigned int old_pending; 47 48 /* We may already have the BQL if coming from the reset path */ 49 QEMU_IOTHREAD_LOCK_GUARD(); 50 51 old_pending = env->pending_interrupts; 52 53 if (level) { 54 env->pending_interrupts |= irq; 55 } else { 56 env->pending_interrupts &= ~irq; 57 } 58 59 if (old_pending != env->pending_interrupts) { 60 ppc_maybe_interrupt(env); 61 kvmppc_set_interrupt(cpu, irq, level); 62 } 63 64 trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts, 65 CPU(cpu)->interrupt_request); 66 } 67 68 /* PowerPC 6xx / 7xx internal IRQ controller */ 69 static void ppc6xx_set_irq(void *opaque, int pin, int level) 70 { 71 PowerPCCPU *cpu = opaque; 72 CPUPPCState *env = &cpu->env; 73 int cur_level; 74 75 trace_ppc_irq_set(env, pin, level); 76 77 cur_level = (env->irq_input_state >> pin) & 1; 78 /* Don't generate spurious events */ 79 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 80 CPUState *cs = CPU(cpu); 81 82 switch (pin) { 83 case PPC6xx_INPUT_TBEN: 84 /* Level sensitive - active high */ 85 trace_ppc_irq_set_state("time base", level); 86 if (level) { 87 cpu_ppc_tb_start(env); 88 } else { 89 cpu_ppc_tb_stop(env); 90 } 91 break; 92 case PPC6xx_INPUT_INT: 93 /* Level sensitive - active high */ 94 trace_ppc_irq_set_state("external IRQ", level); 95 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 96 break; 97 case PPC6xx_INPUT_SMI: 98 /* Level sensitive - active high */ 99 trace_ppc_irq_set_state("SMI IRQ", level); 100 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 101 break; 102 case PPC6xx_INPUT_MCP: 103 /* Negative edge sensitive */ 104 /* XXX: TODO: actual reaction may depends on HID0 status 105 * 603/604/740/750: check HID0[EMCP] 106 */ 107 if (cur_level == 1 && level == 0) { 108 trace_ppc_irq_set_state("machine check", 1); 109 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 110 } 111 break; 112 case PPC6xx_INPUT_CKSTP_IN: 113 /* Level sensitive - active low */ 114 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 115 /* XXX: Note that the only way to restart the CPU is to reset it */ 116 if (level) { 117 trace_ppc_irq_cpu("stop"); 118 cs->halted = 1; 119 } 120 break; 121 case PPC6xx_INPUT_HRESET: 122 /* Level sensitive - active low */ 123 if (level) { 124 trace_ppc_irq_reset("CPU"); 125 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 126 } 127 break; 128 case PPC6xx_INPUT_SRESET: 129 trace_ppc_irq_set_state("RESET IRQ", level); 130 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 131 break; 132 default: 133 g_assert_not_reached(); 134 } 135 if (level) 136 env->irq_input_state |= 1 << pin; 137 else 138 env->irq_input_state &= ~(1 << pin); 139 } 140 } 141 142 void ppc6xx_irq_init(PowerPCCPU *cpu) 143 { 144 qdev_init_gpio_in(DEVICE(cpu), ppc6xx_set_irq, PPC6xx_INPUT_NB); 145 } 146 147 #if defined(TARGET_PPC64) 148 /* PowerPC 970 internal IRQ controller */ 149 static void ppc970_set_irq(void *opaque, int pin, int level) 150 { 151 PowerPCCPU *cpu = opaque; 152 CPUPPCState *env = &cpu->env; 153 int cur_level; 154 155 trace_ppc_irq_set(env, pin, level); 156 157 cur_level = (env->irq_input_state >> pin) & 1; 158 /* Don't generate spurious events */ 159 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 160 CPUState *cs = CPU(cpu); 161 162 switch (pin) { 163 case PPC970_INPUT_INT: 164 /* Level sensitive - active high */ 165 trace_ppc_irq_set_state("external IRQ", level); 166 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 167 break; 168 case PPC970_INPUT_THINT: 169 /* Level sensitive - active high */ 170 trace_ppc_irq_set_state("SMI IRQ", level); 171 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 172 break; 173 case PPC970_INPUT_MCP: 174 /* Negative edge sensitive */ 175 /* XXX: TODO: actual reaction may depends on HID0 status 176 * 603/604/740/750: check HID0[EMCP] 177 */ 178 if (cur_level == 1 && level == 0) { 179 trace_ppc_irq_set_state("machine check", 1); 180 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 181 } 182 break; 183 case PPC970_INPUT_CKSTP: 184 /* Level sensitive - active low */ 185 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 186 if (level) { 187 trace_ppc_irq_cpu("stop"); 188 cs->halted = 1; 189 } else { 190 trace_ppc_irq_cpu("restart"); 191 cs->halted = 0; 192 qemu_cpu_kick(cs); 193 } 194 break; 195 case PPC970_INPUT_HRESET: 196 /* Level sensitive - active low */ 197 if (level) { 198 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 199 } 200 break; 201 case PPC970_INPUT_SRESET: 202 trace_ppc_irq_set_state("RESET IRQ", level); 203 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 204 break; 205 case PPC970_INPUT_TBEN: 206 trace_ppc_irq_set_state("TBEN IRQ", level); 207 /* XXX: TODO */ 208 break; 209 default: 210 g_assert_not_reached(); 211 } 212 if (level) 213 env->irq_input_state |= 1 << pin; 214 else 215 env->irq_input_state &= ~(1 << pin); 216 } 217 } 218 219 void ppc970_irq_init(PowerPCCPU *cpu) 220 { 221 qdev_init_gpio_in(DEVICE(cpu), ppc970_set_irq, PPC970_INPUT_NB); 222 } 223 224 /* POWER7 internal IRQ controller */ 225 static void power7_set_irq(void *opaque, int pin, int level) 226 { 227 PowerPCCPU *cpu = opaque; 228 229 trace_ppc_irq_set(&cpu->env, pin, level); 230 231 switch (pin) { 232 case POWER7_INPUT_INT: 233 /* Level sensitive - active high */ 234 trace_ppc_irq_set_state("external IRQ", level); 235 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 236 break; 237 default: 238 g_assert_not_reached(); 239 } 240 } 241 242 void ppcPOWER7_irq_init(PowerPCCPU *cpu) 243 { 244 qdev_init_gpio_in(DEVICE(cpu), power7_set_irq, POWER7_INPUT_NB); 245 } 246 247 /* POWER9 internal IRQ controller */ 248 static void power9_set_irq(void *opaque, int pin, int level) 249 { 250 PowerPCCPU *cpu = opaque; 251 252 trace_ppc_irq_set(&cpu->env, pin, level); 253 254 switch (pin) { 255 case POWER9_INPUT_INT: 256 /* Level sensitive - active high */ 257 trace_ppc_irq_set_state("external IRQ", level); 258 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 259 break; 260 case POWER9_INPUT_HINT: 261 /* Level sensitive - active high */ 262 trace_ppc_irq_set_state("HV external IRQ", level); 263 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); 264 break; 265 default: 266 g_assert_not_reached(); 267 return; 268 } 269 } 270 271 void ppcPOWER9_irq_init(PowerPCCPU *cpu) 272 { 273 qdev_init_gpio_in(DEVICE(cpu), power9_set_irq, POWER9_INPUT_NB); 274 } 275 #endif /* defined(TARGET_PPC64) */ 276 277 void ppc40x_core_reset(PowerPCCPU *cpu) 278 { 279 CPUPPCState *env = &cpu->env; 280 target_ulong dbsr; 281 282 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); 283 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 284 dbsr = env->spr[SPR_40x_DBSR]; 285 dbsr &= ~0x00000300; 286 dbsr |= 0x00000100; 287 env->spr[SPR_40x_DBSR] = dbsr; 288 } 289 290 void ppc40x_chip_reset(PowerPCCPU *cpu) 291 { 292 CPUPPCState *env = &cpu->env; 293 target_ulong dbsr; 294 295 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); 296 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 297 /* XXX: TODO reset all internal peripherals */ 298 dbsr = env->spr[SPR_40x_DBSR]; 299 dbsr &= ~0x00000300; 300 dbsr |= 0x00000200; 301 env->spr[SPR_40x_DBSR] = dbsr; 302 } 303 304 void ppc40x_system_reset(PowerPCCPU *cpu) 305 { 306 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); 307 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 308 } 309 310 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) 311 { 312 PowerPCCPU *cpu = env_archcpu(env); 313 314 qemu_mutex_lock_iothread(); 315 316 switch ((val >> 28) & 0x3) { 317 case 0x0: 318 /* No action */ 319 break; 320 case 0x1: 321 /* Core reset */ 322 ppc40x_core_reset(cpu); 323 break; 324 case 0x2: 325 /* Chip reset */ 326 ppc40x_chip_reset(cpu); 327 break; 328 case 0x3: 329 /* System reset */ 330 ppc40x_system_reset(cpu); 331 break; 332 } 333 334 qemu_mutex_unlock_iothread(); 335 } 336 337 /* PowerPC 40x internal IRQ controller */ 338 static void ppc40x_set_irq(void *opaque, int pin, int level) 339 { 340 PowerPCCPU *cpu = opaque; 341 CPUPPCState *env = &cpu->env; 342 int cur_level; 343 344 trace_ppc_irq_set(env, pin, level); 345 346 cur_level = (env->irq_input_state >> pin) & 1; 347 /* Don't generate spurious events */ 348 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 349 CPUState *cs = CPU(cpu); 350 351 switch (pin) { 352 case PPC40x_INPUT_RESET_SYS: 353 if (level) { 354 trace_ppc_irq_reset("system"); 355 ppc40x_system_reset(cpu); 356 } 357 break; 358 case PPC40x_INPUT_RESET_CHIP: 359 if (level) { 360 trace_ppc_irq_reset("chip"); 361 ppc40x_chip_reset(cpu); 362 } 363 break; 364 case PPC40x_INPUT_RESET_CORE: 365 /* XXX: TODO: update DBSR[MRR] */ 366 if (level) { 367 trace_ppc_irq_reset("core"); 368 ppc40x_core_reset(cpu); 369 } 370 break; 371 case PPC40x_INPUT_CINT: 372 /* Level sensitive - active high */ 373 trace_ppc_irq_set_state("critical IRQ", level); 374 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 375 break; 376 case PPC40x_INPUT_INT: 377 /* Level sensitive - active high */ 378 trace_ppc_irq_set_state("external IRQ", level); 379 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 380 break; 381 case PPC40x_INPUT_HALT: 382 /* Level sensitive - active low */ 383 if (level) { 384 trace_ppc_irq_cpu("stop"); 385 cs->halted = 1; 386 } else { 387 trace_ppc_irq_cpu("restart"); 388 cs->halted = 0; 389 qemu_cpu_kick(cs); 390 } 391 break; 392 case PPC40x_INPUT_DEBUG: 393 /* Level sensitive - active high */ 394 trace_ppc_irq_set_state("debug pin", level); 395 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 396 break; 397 default: 398 g_assert_not_reached(); 399 } 400 if (level) 401 env->irq_input_state |= 1 << pin; 402 else 403 env->irq_input_state &= ~(1 << pin); 404 } 405 } 406 407 void ppc40x_irq_init(PowerPCCPU *cpu) 408 { 409 qdev_init_gpio_in(DEVICE(cpu), ppc40x_set_irq, PPC40x_INPUT_NB); 410 } 411 412 /* PowerPC E500 internal IRQ controller */ 413 static void ppce500_set_irq(void *opaque, int pin, int level) 414 { 415 PowerPCCPU *cpu = opaque; 416 CPUPPCState *env = &cpu->env; 417 int cur_level; 418 419 trace_ppc_irq_set(env, pin, level); 420 421 cur_level = (env->irq_input_state >> pin) & 1; 422 /* Don't generate spurious events */ 423 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 424 switch (pin) { 425 case PPCE500_INPUT_MCK: 426 if (level) { 427 trace_ppc_irq_reset("system"); 428 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 429 } 430 break; 431 case PPCE500_INPUT_RESET_CORE: 432 if (level) { 433 trace_ppc_irq_reset("core"); 434 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 435 } 436 break; 437 case PPCE500_INPUT_CINT: 438 /* Level sensitive - active high */ 439 trace_ppc_irq_set_state("critical IRQ", level); 440 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 441 break; 442 case PPCE500_INPUT_INT: 443 /* Level sensitive - active high */ 444 trace_ppc_irq_set_state("core IRQ", level); 445 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 446 break; 447 case PPCE500_INPUT_DEBUG: 448 /* Level sensitive - active high */ 449 trace_ppc_irq_set_state("debug pin", level); 450 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 451 break; 452 default: 453 g_assert_not_reached(); 454 } 455 if (level) 456 env->irq_input_state |= 1 << pin; 457 else 458 env->irq_input_state &= ~(1 << pin); 459 } 460 } 461 462 void ppce500_irq_init(PowerPCCPU *cpu) 463 { 464 qdev_init_gpio_in(DEVICE(cpu), ppce500_set_irq, PPCE500_INPUT_NB); 465 } 466 467 /* Enable or Disable the E500 EPR capability */ 468 void ppce500_set_mpic_proxy(bool enabled) 469 { 470 CPUState *cs; 471 472 CPU_FOREACH(cs) { 473 PowerPCCPU *cpu = POWERPC_CPU(cs); 474 475 cpu->env.mpic_proxy = enabled; 476 if (kvm_enabled()) { 477 kvmppc_set_mpic_proxy(cpu, enabled); 478 } 479 } 480 } 481 482 /*****************************************************************************/ 483 /* PowerPC time base and decrementer emulation */ 484 485 /* 486 * Conversion between QEMU_CLOCK_VIRTUAL ns and timebase (TB) ticks: 487 * TB ticks are arrived at by multiplying tb_freq then dividing by 488 * ns per second, and rounding down. TB ticks drive all clocks and 489 * timers in the target machine. 490 * 491 * Converting TB intervals to ns for the purpose of setting a 492 * QEMU_CLOCK_VIRTUAL timer should go the other way, but rounding 493 * up. Rounding down could cause the timer to fire before the TB 494 * value has been reached. 495 */ 496 static uint64_t ns_to_tb(uint32_t freq, int64_t clock) 497 { 498 return muldiv64(clock, freq, NANOSECONDS_PER_SECOND); 499 } 500 501 /* virtual clock in TB ticks, not adjusted by TB offset */ 502 static int64_t tb_to_ns_round_up(uint32_t freq, uint64_t tb) 503 { 504 return muldiv64_round_up(tb, NANOSECONDS_PER_SECOND, freq); 505 } 506 507 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 508 { 509 /* TB time in tb periods */ 510 return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset; 511 } 512 513 uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 514 { 515 ppc_tb_t *tb_env = env->tb_env; 516 uint64_t tb; 517 518 if (kvm_enabled()) { 519 return env->spr[SPR_TBL]; 520 } 521 522 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 523 tb_env->tb_offset); 524 trace_ppc_tb_load(tb); 525 526 return tb; 527 } 528 529 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 530 { 531 ppc_tb_t *tb_env = env->tb_env; 532 uint64_t tb; 533 534 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 535 tb_env->tb_offset); 536 trace_ppc_tb_load(tb); 537 538 return tb >> 32; 539 } 540 541 uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 542 { 543 if (kvm_enabled()) { 544 return env->spr[SPR_TBU]; 545 } 546 547 return _cpu_ppc_load_tbu(env); 548 } 549 550 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 551 int64_t *tb_offsetp, uint64_t value) 552 { 553 *tb_offsetp = value - ns_to_tb(tb_env->tb_freq, vmclk); 554 555 trace_ppc_tb_store(value, *tb_offsetp); 556 } 557 558 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 559 { 560 ppc_tb_t *tb_env = env->tb_env; 561 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 562 uint64_t tb; 563 564 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); 565 tb &= 0xFFFFFFFF00000000ULL; 566 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb | (uint64_t)value); 567 } 568 569 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 570 { 571 ppc_tb_t *tb_env = env->tb_env; 572 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 573 uint64_t tb; 574 575 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); 576 tb &= 0x00000000FFFFFFFFULL; 577 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, 578 ((uint64_t)value << 32) | tb); 579 } 580 581 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 582 { 583 _cpu_ppc_store_tbu(env, value); 584 } 585 586 uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 587 { 588 ppc_tb_t *tb_env = env->tb_env; 589 uint64_t tb; 590 591 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 592 tb_env->atb_offset); 593 trace_ppc_tb_load(tb); 594 595 return tb; 596 } 597 598 uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 599 { 600 ppc_tb_t *tb_env = env->tb_env; 601 uint64_t tb; 602 603 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 604 tb_env->atb_offset); 605 trace_ppc_tb_load(tb); 606 607 return tb >> 32; 608 } 609 610 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 611 { 612 ppc_tb_t *tb_env = env->tb_env; 613 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 614 uint64_t tb; 615 616 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset); 617 tb &= 0xFFFFFFFF00000000ULL; 618 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, tb | (uint64_t)value); 619 } 620 621 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 622 { 623 ppc_tb_t *tb_env = env->tb_env; 624 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 625 uint64_t tb; 626 627 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset); 628 tb &= 0x00000000FFFFFFFFULL; 629 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, 630 ((uint64_t)value << 32) | tb); 631 } 632 633 uint64_t cpu_ppc_load_vtb(CPUPPCState *env) 634 { 635 ppc_tb_t *tb_env = env->tb_env; 636 637 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 638 tb_env->vtb_offset); 639 } 640 641 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) 642 { 643 ppc_tb_t *tb_env = env->tb_env; 644 645 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 646 &tb_env->vtb_offset, value); 647 } 648 649 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) 650 { 651 ppc_tb_t *tb_env = env->tb_env; 652 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 653 uint64_t tb; 654 655 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset); 656 tb &= 0xFFFFFFUL; 657 tb |= (value & ~0xFFFFFFUL); 658 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb); 659 } 660 661 static void cpu_ppc_tb_stop (CPUPPCState *env) 662 { 663 ppc_tb_t *tb_env = env->tb_env; 664 uint64_t tb, atb, vmclk; 665 666 /* If the time base is already frozen, do nothing */ 667 if (tb_env->tb_freq != 0) { 668 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 669 /* Get the time base */ 670 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 671 /* Get the alternate time base */ 672 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 673 /* Store the time base value (ie compute the current offset) */ 674 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 675 /* Store the alternate time base value (compute the current offset) */ 676 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 677 /* Set the time base frequency to zero */ 678 tb_env->tb_freq = 0; 679 /* Now, the time bases are frozen to tb_offset / atb_offset value */ 680 } 681 } 682 683 static void cpu_ppc_tb_start (CPUPPCState *env) 684 { 685 ppc_tb_t *tb_env = env->tb_env; 686 uint64_t tb, atb, vmclk; 687 688 /* If the time base is not frozen, do nothing */ 689 if (tb_env->tb_freq == 0) { 690 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 691 /* Get the time base from tb_offset */ 692 tb = tb_env->tb_offset; 693 /* Get the alternate time base from atb_offset */ 694 atb = tb_env->atb_offset; 695 /* Restore the tb frequency from the decrementer frequency */ 696 tb_env->tb_freq = tb_env->decr_freq; 697 /* Store the time base value */ 698 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 699 /* Store the alternate time base value */ 700 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 701 } 702 } 703 704 bool ppc_decr_clear_on_delivery(CPUPPCState *env) 705 { 706 ppc_tb_t *tb_env = env->tb_env; 707 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 708 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 709 } 710 711 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 712 { 713 ppc_tb_t *tb_env = env->tb_env; 714 uint64_t now, n; 715 int64_t decr; 716 717 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 718 n = ns_to_tb(tb_env->decr_freq, now); 719 if (next > n && tb_env->flags & PPC_TIMER_BOOKE) { 720 decr = 0; 721 } else { 722 decr = next - n; 723 } 724 725 trace_ppc_decr_load(decr); 726 727 return decr; 728 } 729 730 target_ulong cpu_ppc_load_decr(CPUPPCState *env) 731 { 732 ppc_tb_t *tb_env = env->tb_env; 733 uint64_t decr; 734 735 if (kvm_enabled()) { 736 return env->spr[SPR_DECR]; 737 } 738 739 decr = _cpu_ppc_load_decr(env, tb_env->decr_next); 740 741 /* 742 * If large decrementer is enabled then the decrementer is signed extened 743 * to 64 bits, otherwise it is a 32 bit value. 744 */ 745 if (env->spr[SPR_LPCR] & LPCR_LD) { 746 PowerPCCPU *cpu = env_archcpu(env); 747 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 748 return sextract64(decr, 0, pcc->lrg_decr_bits); 749 } 750 return (uint32_t) decr; 751 } 752 753 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) 754 { 755 PowerPCCPU *cpu = env_archcpu(env); 756 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 757 ppc_tb_t *tb_env = env->tb_env; 758 uint64_t hdecr; 759 760 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); 761 762 /* 763 * If we have a large decrementer (POWER9 or later) then hdecr is sign 764 * extended to 64 bits, otherwise it is 32 bits. 765 */ 766 if (pcc->lrg_decr_bits > 32) { 767 return sextract64(hdecr, 0, pcc->lrg_decr_bits); 768 } 769 return (uint32_t) hdecr; 770 } 771 772 uint64_t cpu_ppc_load_purr (CPUPPCState *env) 773 { 774 ppc_tb_t *tb_env = env->tb_env; 775 776 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 777 tb_env->purr_offset); 778 } 779 780 /* When decrementer expires, 781 * all we need to do is generate or queue a CPU exception 782 */ 783 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 784 { 785 /* Raise it */ 786 trace_ppc_decr_excp("raise"); 787 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 788 } 789 790 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 791 { 792 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 793 } 794 795 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 796 { 797 CPUPPCState *env = &cpu->env; 798 799 /* Raise it */ 800 trace_ppc_decr_excp("raise HV"); 801 802 /* The architecture specifies that we don't deliver HDEC 803 * interrupts in a PM state. Not only they don't cause a 804 * wakeup but they also get effectively discarded. 805 */ 806 if (!env->resume_as_sreset) { 807 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 808 } 809 } 810 811 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 812 { 813 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 814 } 815 816 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 817 QEMUTimer *timer, 818 void (*raise_excp)(void *), 819 void (*lower_excp)(PowerPCCPU *), 820 uint32_t flags, target_ulong decr, 821 target_ulong value, int nr_bits) 822 { 823 CPUPPCState *env = &cpu->env; 824 ppc_tb_t *tb_env = env->tb_env; 825 uint64_t now, next; 826 int64_t signed_value; 827 int64_t signed_decr; 828 829 /* Truncate value to decr_width and sign extend for simplicity */ 830 value = extract64(value, 0, nr_bits); 831 decr = extract64(decr, 0, nr_bits); 832 signed_value = sextract64(value, 0, nr_bits); 833 signed_decr = sextract64(decr, 0, nr_bits); 834 835 trace_ppc_decr_store(nr_bits, decr, value); 836 837 if (kvm_enabled()) { 838 /* KVM handles decrementer exceptions, we don't need our own timer */ 839 return; 840 } 841 842 /* 843 * Calculate the next decrementer event and set a timer. 844 * decr_next is in timebase units to keep rounding simple. Note it is 845 * not adjusted by tb_offset because if TB changes via tb_offset changing, 846 * decrementer does not change, so not directly comparable with TB. 847 */ 848 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 849 next = ns_to_tb(tb_env->decr_freq, now) + value; 850 *nextp = next; /* nextp is in timebase units */ 851 852 /* 853 * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interrupt. 854 * 855 * On MSB level based DEC implementations the MSB always means the interrupt 856 * is pending, so raise it on those. 857 * 858 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 859 * an edge interrupt, so raise it here too. 860 */ 861 if (((flags & PPC_DECR_UNDERFLOW_LEVEL) && signed_value < 0) || 862 ((flags & PPC_DECR_UNDERFLOW_TRIGGERED) && signed_value < 0 863 && signed_decr >= 0)) { 864 (*raise_excp)(cpu); 865 return; 866 } 867 868 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 869 if (signed_value >= 0 && (flags & PPC_DECR_UNDERFLOW_LEVEL)) { 870 (*lower_excp)(cpu); 871 } 872 873 /* Adjust timer */ 874 timer_mod(timer, tb_to_ns_round_up(tb_env->decr_freq, next)); 875 } 876 877 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, 878 target_ulong value, int nr_bits) 879 { 880 ppc_tb_t *tb_env = cpu->env.tb_env; 881 882 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 883 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, 884 tb_env->flags, decr, value, nr_bits); 885 } 886 887 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) 888 { 889 PowerPCCPU *cpu = env_archcpu(env); 890 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 891 int nr_bits = 32; 892 893 if (env->spr[SPR_LPCR] & LPCR_LD) { 894 nr_bits = pcc->lrg_decr_bits; 895 } 896 897 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); 898 } 899 900 static void cpu_ppc_decr_cb(void *opaque) 901 { 902 PowerPCCPU *cpu = opaque; 903 904 cpu_ppc_decr_excp(cpu); 905 } 906 907 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, 908 target_ulong value, int nr_bits) 909 { 910 ppc_tb_t *tb_env = cpu->env.tb_env; 911 912 if (tb_env->hdecr_timer != NULL) { 913 /* HDECR (Book3S 64bit) is edge-based, not level like DECR */ 914 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 915 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 916 PPC_DECR_UNDERFLOW_TRIGGERED, 917 hdecr, value, nr_bits); 918 } 919 } 920 921 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) 922 { 923 PowerPCCPU *cpu = env_archcpu(env); 924 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 925 926 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 927 pcc->lrg_decr_bits); 928 } 929 930 static void cpu_ppc_hdecr_cb(void *opaque) 931 { 932 PowerPCCPU *cpu = opaque; 933 934 cpu_ppc_hdecr_excp(cpu); 935 } 936 937 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) 938 { 939 ppc_tb_t *tb_env = env->tb_env; 940 941 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 942 &tb_env->purr_offset, value); 943 } 944 945 static void timebase_save(PPCTimebase *tb) 946 { 947 uint64_t ticks = cpu_get_host_ticks(); 948 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 949 950 if (!first_ppc_cpu->env.tb_env) { 951 error_report("No timebase object"); 952 return; 953 } 954 955 /* not used anymore, we keep it for compatibility */ 956 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 957 /* 958 * tb_offset is only expected to be changed by QEMU so 959 * there is no need to update it from KVM here 960 */ 961 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 962 963 tb->runstate_paused = 964 runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM); 965 } 966 967 static void timebase_load(PPCTimebase *tb) 968 { 969 CPUState *cpu; 970 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 971 int64_t tb_off_adj, tb_off; 972 unsigned long freq; 973 974 if (!first_ppc_cpu->env.tb_env) { 975 error_report("No timebase object"); 976 return; 977 } 978 979 freq = first_ppc_cpu->env.tb_env->tb_freq; 980 981 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); 982 983 tb_off = first_ppc_cpu->env.tb_env->tb_offset; 984 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 985 (tb_off_adj - tb_off) / freq); 986 987 /* Set new offset to all CPUs */ 988 CPU_FOREACH(cpu) { 989 PowerPCCPU *pcpu = POWERPC_CPU(cpu); 990 pcpu->env.tb_env->tb_offset = tb_off_adj; 991 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); 992 } 993 } 994 995 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 996 RunState state) 997 { 998 PPCTimebase *tb = opaque; 999 1000 if (running) { 1001 timebase_load(tb); 1002 } else { 1003 timebase_save(tb); 1004 } 1005 } 1006 1007 /* 1008 * When migrating a running guest, read the clock just 1009 * before migration, so that the guest clock counts 1010 * during the events between: 1011 * 1012 * * vm_stop() 1013 * * 1014 * * pre_save() 1015 * 1016 * This reduces clock difference on migration from 5s 1017 * to 0.1s (when max_downtime == 5s), because sending the 1018 * final pages of memory (which happens between vm_stop() 1019 * and pre_save()) takes max_downtime. 1020 */ 1021 static int timebase_pre_save(void *opaque) 1022 { 1023 PPCTimebase *tb = opaque; 1024 1025 /* guest_timebase won't be overridden in case of paused guest or savevm */ 1026 if (!tb->runstate_paused) { 1027 timebase_save(tb); 1028 } 1029 1030 return 0; 1031 } 1032 1033 const VMStateDescription vmstate_ppc_timebase = { 1034 .name = "timebase", 1035 .version_id = 1, 1036 .minimum_version_id = 1, 1037 .pre_save = timebase_pre_save, 1038 .fields = (VMStateField []) { 1039 VMSTATE_UINT64(guest_timebase, PPCTimebase), 1040 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 1041 VMSTATE_END_OF_LIST() 1042 }, 1043 }; 1044 1045 /* Set up (once) timebase frequency (in Hz) */ 1046 void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq) 1047 { 1048 PowerPCCPU *cpu = env_archcpu(env); 1049 ppc_tb_t *tb_env; 1050 1051 tb_env = g_new0(ppc_tb_t, 1); 1052 env->tb_env = tb_env; 1053 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1054 if (is_book3s_arch2x(env)) { 1055 /* All Book3S 64bit CPUs implement level based DEC logic */ 1056 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 1057 } 1058 /* Create new timer */ 1059 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1060 &cpu_ppc_decr_cb, cpu); 1061 if (env->has_hv_mode && !cpu->vhyp) { 1062 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1063 &cpu_ppc_hdecr_cb, cpu); 1064 } else { 1065 tb_env->hdecr_timer = NULL; 1066 } 1067 1068 tb_env->tb_freq = freq; 1069 tb_env->decr_freq = freq; 1070 } 1071 1072 void cpu_ppc_tb_reset(CPUPPCState *env) 1073 { 1074 PowerPCCPU *cpu = env_archcpu(env); 1075 ppc_tb_t *tb_env = env->tb_env; 1076 1077 timer_del(tb_env->decr_timer); 1078 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 1079 tb_env->decr_next = 0; 1080 if (tb_env->hdecr_timer != NULL) { 1081 timer_del(tb_env->hdecr_timer); 1082 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 1083 tb_env->hdecr_next = 0; 1084 } 1085 1086 /* 1087 * There is a bug in Linux 2.4 kernels: 1088 * if a decrementer exception is pending when it enables msr_ee at startup, 1089 * it's not ready to handle it... 1090 */ 1091 cpu_ppc_store_decr(env, -1); 1092 cpu_ppc_store_hdecr(env, -1); 1093 cpu_ppc_store_purr(env, 0x0000000000000000ULL); 1094 } 1095 1096 void cpu_ppc_tb_free(CPUPPCState *env) 1097 { 1098 timer_free(env->tb_env->decr_timer); 1099 timer_free(env->tb_env->hdecr_timer); 1100 g_free(env->tb_env); 1101 } 1102 1103 /* cpu_ppc_hdecr_init may be used if the timer is not used by HDEC emulation */ 1104 void cpu_ppc_hdecr_init(CPUPPCState *env) 1105 { 1106 PowerPCCPU *cpu = env_archcpu(env); 1107 1108 assert(env->tb_env->hdecr_timer == NULL); 1109 1110 env->tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1111 &cpu_ppc_hdecr_cb, cpu); 1112 } 1113 1114 void cpu_ppc_hdecr_exit(CPUPPCState *env) 1115 { 1116 PowerPCCPU *cpu = env_archcpu(env); 1117 1118 timer_free(env->tb_env->hdecr_timer); 1119 env->tb_env->hdecr_timer = NULL; 1120 1121 cpu_ppc_hdecr_lower(cpu); 1122 } 1123 1124 /*****************************************************************************/ 1125 /* PowerPC 40x timers */ 1126 1127 /* PIT, FIT & WDT */ 1128 typedef struct ppc40x_timer_t ppc40x_timer_t; 1129 struct ppc40x_timer_t { 1130 uint64_t pit_reload; /* PIT auto-reload value */ 1131 uint64_t fit_next; /* Tick for next FIT interrupt */ 1132 QEMUTimer *fit_timer; 1133 uint64_t wdt_next; /* Tick for next WDT interrupt */ 1134 QEMUTimer *wdt_timer; 1135 1136 /* 405 have the PIT, 440 have a DECR. */ 1137 unsigned int decr_excp; 1138 }; 1139 1140 /* Fixed interval timer */ 1141 static void cpu_4xx_fit_cb (void *opaque) 1142 { 1143 PowerPCCPU *cpu = opaque; 1144 CPUPPCState *env = &cpu->env; 1145 ppc_tb_t *tb_env; 1146 ppc40x_timer_t *ppc40x_timer; 1147 uint64_t now, next; 1148 1149 tb_env = env->tb_env; 1150 ppc40x_timer = tb_env->opaque; 1151 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1152 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 1153 case 0: 1154 next = 1 << 9; 1155 break; 1156 case 1: 1157 next = 1 << 13; 1158 break; 1159 case 2: 1160 next = 1 << 17; 1161 break; 1162 case 3: 1163 next = 1 << 21; 1164 break; 1165 default: 1166 /* Cannot occur, but makes gcc happy */ 1167 return; 1168 } 1169 next = now + tb_to_ns_round_up(tb_env->tb_freq, next); 1170 timer_mod(ppc40x_timer->fit_timer, next); 1171 env->spr[SPR_40x_TSR] |= 1 << 26; 1172 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 1173 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 1174 } 1175 trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 1176 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1177 } 1178 1179 /* Programmable interval timer */ 1180 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 1181 { 1182 ppc40x_timer_t *ppc40x_timer; 1183 uint64_t now, next; 1184 1185 ppc40x_timer = tb_env->opaque; 1186 if (ppc40x_timer->pit_reload <= 1 || 1187 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 1188 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 1189 /* Stop PIT */ 1190 trace_ppc4xx_pit_stop(); 1191 timer_del(tb_env->decr_timer); 1192 } else { 1193 trace_ppc4xx_pit_start(ppc40x_timer->pit_reload); 1194 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1195 1196 if (is_excp) { 1197 tb_env->decr_next += ppc40x_timer->pit_reload; 1198 } else { 1199 tb_env->decr_next = ns_to_tb(tb_env->decr_freq, now) 1200 + ppc40x_timer->pit_reload; 1201 } 1202 next = tb_to_ns_round_up(tb_env->decr_freq, tb_env->decr_next); 1203 timer_mod(tb_env->decr_timer, next); 1204 } 1205 } 1206 1207 static void cpu_4xx_pit_cb (void *opaque) 1208 { 1209 PowerPCCPU *cpu = opaque; 1210 CPUPPCState *env = &cpu->env; 1211 ppc_tb_t *tb_env; 1212 ppc40x_timer_t *ppc40x_timer; 1213 1214 tb_env = env->tb_env; 1215 ppc40x_timer = tb_env->opaque; 1216 env->spr[SPR_40x_TSR] |= 1 << 27; 1217 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 1218 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 1219 } 1220 start_stop_pit(env, tb_env, 1); 1221 trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 1222 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 1223 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 1224 ppc40x_timer->pit_reload); 1225 } 1226 1227 /* Watchdog timer */ 1228 static void cpu_4xx_wdt_cb (void *opaque) 1229 { 1230 PowerPCCPU *cpu = opaque; 1231 CPUPPCState *env = &cpu->env; 1232 ppc_tb_t *tb_env; 1233 ppc40x_timer_t *ppc40x_timer; 1234 uint64_t now, next; 1235 1236 tb_env = env->tb_env; 1237 ppc40x_timer = tb_env->opaque; 1238 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1239 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 1240 case 0: 1241 next = 1 << 17; 1242 break; 1243 case 1: 1244 next = 1 << 21; 1245 break; 1246 case 2: 1247 next = 1 << 25; 1248 break; 1249 case 3: 1250 next = 1 << 29; 1251 break; 1252 default: 1253 /* Cannot occur, but makes gcc happy */ 1254 return; 1255 } 1256 next = now + tb_to_ns_round_up(tb_env->decr_freq, next); 1257 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1258 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 1259 case 0x0: 1260 case 0x1: 1261 timer_mod(ppc40x_timer->wdt_timer, next); 1262 ppc40x_timer->wdt_next = next; 1263 env->spr[SPR_40x_TSR] |= 1U << 31; 1264 break; 1265 case 0x2: 1266 timer_mod(ppc40x_timer->wdt_timer, next); 1267 ppc40x_timer->wdt_next = next; 1268 env->spr[SPR_40x_TSR] |= 1 << 30; 1269 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 1270 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 1271 } 1272 break; 1273 case 0x3: 1274 env->spr[SPR_40x_TSR] &= ~0x30000000; 1275 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 1276 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 1277 case 0x0: 1278 /* No reset */ 1279 break; 1280 case 0x1: /* Core reset */ 1281 ppc40x_core_reset(cpu); 1282 break; 1283 case 0x2: /* Chip reset */ 1284 ppc40x_chip_reset(cpu); 1285 break; 1286 case 0x3: /* System reset */ 1287 ppc40x_system_reset(cpu); 1288 break; 1289 } 1290 } 1291 } 1292 1293 void store_40x_pit (CPUPPCState *env, target_ulong val) 1294 { 1295 ppc_tb_t *tb_env; 1296 ppc40x_timer_t *ppc40x_timer; 1297 1298 tb_env = env->tb_env; 1299 ppc40x_timer = tb_env->opaque; 1300 trace_ppc40x_store_pit(val); 1301 ppc40x_timer->pit_reload = val; 1302 start_stop_pit(env, tb_env, 0); 1303 } 1304 1305 target_ulong load_40x_pit (CPUPPCState *env) 1306 { 1307 return cpu_ppc_load_decr(env); 1308 } 1309 1310 void store_40x_tsr(CPUPPCState *env, target_ulong val) 1311 { 1312 PowerPCCPU *cpu = env_archcpu(env); 1313 1314 trace_ppc40x_store_tcr(val); 1315 1316 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); 1317 if (val & 0x80000000) { 1318 ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0); 1319 } 1320 } 1321 1322 void store_40x_tcr(CPUPPCState *env, target_ulong val) 1323 { 1324 PowerPCCPU *cpu = env_archcpu(env); 1325 ppc_tb_t *tb_env; 1326 1327 trace_ppc40x_store_tsr(val); 1328 1329 tb_env = env->tb_env; 1330 env->spr[SPR_40x_TCR] = val & 0xFFC00000; 1331 start_stop_pit(env, tb_env, 1); 1332 cpu_4xx_wdt_cb(cpu); 1333 } 1334 1335 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 1336 { 1337 CPUPPCState *env = opaque; 1338 ppc_tb_t *tb_env = env->tb_env; 1339 1340 trace_ppc40x_set_tb_clk(freq); 1341 tb_env->tb_freq = freq; 1342 tb_env->decr_freq = freq; 1343 /* XXX: we should also update all timers */ 1344 } 1345 1346 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 1347 unsigned int decr_excp) 1348 { 1349 ppc_tb_t *tb_env; 1350 ppc40x_timer_t *ppc40x_timer; 1351 PowerPCCPU *cpu = env_archcpu(env); 1352 1353 trace_ppc40x_timers_init(freq); 1354 1355 tb_env = g_new0(ppc_tb_t, 1); 1356 ppc40x_timer = g_new0(ppc40x_timer_t, 1); 1357 1358 env->tb_env = tb_env; 1359 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1360 tb_env->tb_freq = freq; 1361 tb_env->decr_freq = freq; 1362 tb_env->opaque = ppc40x_timer; 1363 1364 /* We use decr timer for PIT */ 1365 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, cpu); 1366 ppc40x_timer->fit_timer = 1367 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, cpu); 1368 ppc40x_timer->wdt_timer = 1369 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, cpu); 1370 ppc40x_timer->decr_excp = decr_excp; 1371 1372 return &ppc_40x_set_tb_clk; 1373 } 1374 1375 /*****************************************************************************/ 1376 /* Embedded PowerPC Device Control Registers */ 1377 typedef struct ppc_dcrn_t ppc_dcrn_t; 1378 struct ppc_dcrn_t { 1379 dcr_read_cb dcr_read; 1380 dcr_write_cb dcr_write; 1381 void *opaque; 1382 }; 1383 1384 /* XXX: on 460, DCR addresses are 32 bits wide, 1385 * using DCRIPR to get the 22 upper bits of the DCR address 1386 */ 1387 #define DCRN_NB 1024 1388 struct ppc_dcr_t { 1389 ppc_dcrn_t dcrn[DCRN_NB]; 1390 int (*read_error)(int dcrn); 1391 int (*write_error)(int dcrn); 1392 }; 1393 1394 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1395 { 1396 ppc_dcrn_t *dcr; 1397 1398 if (dcrn < 0 || dcrn >= DCRN_NB) 1399 goto error; 1400 dcr = &dcr_env->dcrn[dcrn]; 1401 if (dcr->dcr_read == NULL) 1402 goto error; 1403 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 1404 trace_ppc_dcr_read(dcrn, *valp); 1405 1406 return 0; 1407 1408 error: 1409 if (dcr_env->read_error != NULL) 1410 return (*dcr_env->read_error)(dcrn); 1411 1412 return -1; 1413 } 1414 1415 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1416 { 1417 ppc_dcrn_t *dcr; 1418 1419 if (dcrn < 0 || dcrn >= DCRN_NB) 1420 goto error; 1421 dcr = &dcr_env->dcrn[dcrn]; 1422 if (dcr->dcr_write == NULL) 1423 goto error; 1424 trace_ppc_dcr_write(dcrn, val); 1425 (*dcr->dcr_write)(dcr->opaque, dcrn, val); 1426 1427 return 0; 1428 1429 error: 1430 if (dcr_env->write_error != NULL) 1431 return (*dcr_env->write_error)(dcrn); 1432 1433 return -1; 1434 } 1435 1436 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 1437 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 1438 { 1439 ppc_dcr_t *dcr_env; 1440 ppc_dcrn_t *dcr; 1441 1442 dcr_env = env->dcr_env; 1443 if (dcr_env == NULL) 1444 return -1; 1445 if (dcrn < 0 || dcrn >= DCRN_NB) 1446 return -1; 1447 dcr = &dcr_env->dcrn[dcrn]; 1448 if (dcr->opaque != NULL || 1449 dcr->dcr_read != NULL || 1450 dcr->dcr_write != NULL) 1451 return -1; 1452 dcr->opaque = opaque; 1453 dcr->dcr_read = dcr_read; 1454 dcr->dcr_write = dcr_write; 1455 1456 return 0; 1457 } 1458 1459 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 1460 int (*write_error)(int dcrn)) 1461 { 1462 ppc_dcr_t *dcr_env; 1463 1464 dcr_env = g_new0(ppc_dcr_t, 1); 1465 dcr_env->read_error = read_error; 1466 dcr_env->write_error = write_error; 1467 env->dcr_env = dcr_env; 1468 1469 return 0; 1470 } 1471 1472 /*****************************************************************************/ 1473 1474 int ppc_cpu_pir(PowerPCCPU *cpu) 1475 { 1476 CPUPPCState *env = &cpu->env; 1477 return env->spr_cb[SPR_PIR].default_value; 1478 } 1479 1480 int ppc_cpu_tir(PowerPCCPU *cpu) 1481 { 1482 CPUPPCState *env = &cpu->env; 1483 return env->spr_cb[SPR_TIR].default_value; 1484 } 1485 1486 PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1487 { 1488 CPUState *cs; 1489 1490 CPU_FOREACH(cs) { 1491 PowerPCCPU *cpu = POWERPC_CPU(cs); 1492 1493 if (ppc_cpu_pir(cpu) == pir) { 1494 return cpu; 1495 } 1496 } 1497 1498 return NULL; 1499 } 1500 1501 void ppc_irq_reset(PowerPCCPU *cpu) 1502 { 1503 CPUPPCState *env = &cpu->env; 1504 1505 env->irq_input_state = 0; 1506 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); 1507 } 1508